1/* 2 * Copyright (c) 2014 MediaTek Inc. 3 * Author: Eddie Huang <eddie.huang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <dt-bindings/clock/mt8173-clk.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/memory/mt8173-larb-port.h> 18#include <dt-bindings/phy/phy.h> 19#include <dt-bindings/power/mt8173-power.h> 20#include <dt-bindings/reset/mt8173-resets.h> 21#include "mt8173-pinfunc.h" 22 23/ { 24 compatible = "mediatek,mt8173"; 25 interrupt-parent = <&sysirq>; 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 aliases { 30 ovl0 = &ovl0; 31 ovl1 = &ovl1; 32 rdma0 = &rdma0; 33 rdma1 = &rdma1; 34 rdma2 = &rdma2; 35 wdma0 = &wdma0; 36 wdma1 = &wdma1; 37 color0 = &color0; 38 color1 = &color1; 39 split0 = &split0; 40 split1 = &split1; 41 dpi0 = &dpi0; 42 dsi0 = &dsi0; 43 dsi1 = &dsi1; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 cpu-map { 51 cluster0 { 52 core0 { 53 cpu = <&cpu0>; 54 }; 55 core1 { 56 cpu = <&cpu1>; 57 }; 58 }; 59 60 cluster1 { 61 core0 { 62 cpu = <&cpu2>; 63 }; 64 core1 { 65 cpu = <&cpu3>; 66 }; 67 }; 68 }; 69 70 cpu0: cpu@0 { 71 device_type = "cpu"; 72 compatible = "arm,cortex-a53"; 73 reg = <0x000>; 74 enable-method = "psci"; 75 cpu-idle-states = <&CPU_SLEEP_0>; 76 #cooling-cells = <2>; 77 }; 78 79 cpu1: cpu@1 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a53"; 82 reg = <0x001>; 83 enable-method = "psci"; 84 cpu-idle-states = <&CPU_SLEEP_0>; 85 }; 86 87 cpu2: cpu@100 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a57"; 90 reg = <0x100>; 91 enable-method = "psci"; 92 cpu-idle-states = <&CPU_SLEEP_0>; 93 #cooling-cells = <2>; 94 }; 95 96 cpu3: cpu@101 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a57"; 99 reg = <0x101>; 100 enable-method = "psci"; 101 cpu-idle-states = <&CPU_SLEEP_0>; 102 }; 103 104 idle-states { 105 entry-method = "psci"; 106 107 CPU_SLEEP_0: cpu-sleep-0 { 108 compatible = "arm,idle-state"; 109 local-timer-stop; 110 entry-latency-us = <639>; 111 exit-latency-us = <680>; 112 min-residency-us = <1088>; 113 arm,psci-suspend-param = <0x0010000>; 114 }; 115 }; 116 }; 117 118 psci { 119 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 120 method = "smc"; 121 cpu_suspend = <0x84000001>; 122 cpu_off = <0x84000002>; 123 cpu_on = <0x84000003>; 124 }; 125 126 clk26m: oscillator@0 { 127 compatible = "fixed-clock"; 128 #clock-cells = <0>; 129 clock-frequency = <26000000>; 130 clock-output-names = "clk26m"; 131 }; 132 133 clk32k: oscillator@1 { 134 compatible = "fixed-clock"; 135 #clock-cells = <0>; 136 clock-frequency = <32000>; 137 clock-output-names = "clk32k"; 138 }; 139 140 cpum_ck: oscillator@2 { 141 compatible = "fixed-clock"; 142 #clock-cells = <0>; 143 clock-frequency = <0>; 144 clock-output-names = "cpum_ck"; 145 }; 146 147 thermal-zones { 148 cpu_thermal: cpu_thermal { 149 polling-delay-passive = <1000>; /* milliseconds */ 150 polling-delay = <1000>; /* milliseconds */ 151 152 thermal-sensors = <&thermal>; 153 sustainable-power = <1500>; /* milliwatts */ 154 155 trips { 156 threshold: trip-point@0 { 157 temperature = <68000>; 158 hysteresis = <2000>; 159 type = "passive"; 160 }; 161 162 target: trip-point@1 { 163 temperature = <85000>; 164 hysteresis = <2000>; 165 type = "passive"; 166 }; 167 168 cpu_crit: cpu_crit@0 { 169 temperature = <115000>; 170 hysteresis = <2000>; 171 type = "critical"; 172 }; 173 }; 174 175 cooling-maps { 176 map@0 { 177 trip = <&target>; 178 cooling-device = <&cpu0 0 0>; 179 contribution = <1024>; 180 }; 181 map@1 { 182 trip = <&target>; 183 cooling-device = <&cpu2 0 0>; 184 contribution = <2048>; 185 }; 186 }; 187 }; 188 }; 189 190 reserved-memory { 191 #address-cells = <2>; 192 #size-cells = <2>; 193 ranges; 194 vpu_dma_reserved: vpu_dma_mem_region { 195 compatible = "shared-dma-pool"; 196 reg = <0 0xb7000000 0 0x500000>; 197 alignment = <0x1000>; 198 no-map; 199 }; 200 }; 201 202 timer { 203 compatible = "arm,armv8-timer"; 204 interrupt-parent = <&gic>; 205 interrupts = <GIC_PPI 13 206 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 207 <GIC_PPI 14 208 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 209 <GIC_PPI 11 210 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 211 <GIC_PPI 10 212 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 213 }; 214 215 soc { 216 #address-cells = <2>; 217 #size-cells = <2>; 218 compatible = "simple-bus"; 219 ranges; 220 221 topckgen: clock-controller@10000000 { 222 compatible = "mediatek,mt8173-topckgen"; 223 reg = <0 0x10000000 0 0x1000>; 224 #clock-cells = <1>; 225 }; 226 227 infracfg: power-controller@10001000 { 228 compatible = "mediatek,mt8173-infracfg", "syscon"; 229 reg = <0 0x10001000 0 0x1000>; 230 #clock-cells = <1>; 231 #reset-cells = <1>; 232 }; 233 234 pericfg: power-controller@10003000 { 235 compatible = "mediatek,mt8173-pericfg", "syscon"; 236 reg = <0 0x10003000 0 0x1000>; 237 #clock-cells = <1>; 238 #reset-cells = <1>; 239 }; 240 241 syscfg_pctl_a: syscfg_pctl_a@10005000 { 242 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 243 reg = <0 0x10005000 0 0x1000>; 244 }; 245 246 pio: pinctrl@0x10005000 { 247 compatible = "mediatek,mt8173-pinctrl"; 248 reg = <0 0x1000b000 0 0x1000>; 249 mediatek,pctl-regmap = <&syscfg_pctl_a>; 250 pins-are-numbered; 251 gpio-controller; 252 #gpio-cells = <2>; 253 interrupt-controller; 254 #interrupt-cells = <2>; 255 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 258 259 hdmi_pin: xxx { 260 261 /*hdmi htplg pin*/ 262 pins1 { 263 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 264 input-enable; 265 bias-pull-down; 266 }; 267 }; 268 269 i2c0_pins_a: i2c0 { 270 pins1 { 271 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 272 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 273 bias-disable; 274 }; 275 }; 276 277 i2c1_pins_a: i2c1 { 278 pins1 { 279 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 280 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 281 bias-disable; 282 }; 283 }; 284 285 i2c2_pins_a: i2c2 { 286 pins1 { 287 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 288 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 289 bias-disable; 290 }; 291 }; 292 293 i2c3_pins_a: i2c3 { 294 pins1 { 295 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 296 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 297 bias-disable; 298 }; 299 }; 300 301 i2c4_pins_a: i2c4 { 302 pins1 { 303 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 304 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 305 bias-disable; 306 }; 307 }; 308 309 i2c6_pins_a: i2c6 { 310 pins1 { 311 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 312 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 313 bias-disable; 314 }; 315 }; 316 }; 317 318 scpsys: scpsys@10006000 { 319 compatible = "mediatek,mt8173-scpsys"; 320 #power-domain-cells = <1>; 321 reg = <0 0x10006000 0 0x1000>; 322 clocks = <&clk26m>, 323 <&topckgen CLK_TOP_MM_SEL>, 324 <&topckgen CLK_TOP_VENC_SEL>, 325 <&topckgen CLK_TOP_VENC_LT_SEL>; 326 clock-names = "mfg", "mm", "venc", "venc_lt"; 327 infracfg = <&infracfg>; 328 }; 329 330 watchdog: watchdog@10007000 { 331 compatible = "mediatek,mt8173-wdt", 332 "mediatek,mt6589-wdt"; 333 reg = <0 0x10007000 0 0x100>; 334 }; 335 336 timer: timer@10008000 { 337 compatible = "mediatek,mt8173-timer", 338 "mediatek,mt6577-timer"; 339 reg = <0 0x10008000 0 0x1000>; 340 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 341 clocks = <&infracfg CLK_INFRA_CLK_13M>, 342 <&topckgen CLK_TOP_RTC_SEL>; 343 }; 344 345 pwrap: pwrap@1000d000 { 346 compatible = "mediatek,mt8173-pwrap"; 347 reg = <0 0x1000d000 0 0x1000>; 348 reg-names = "pwrap"; 349 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 350 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 351 reset-names = "pwrap"; 352 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 353 clock-names = "spi", "wrap"; 354 }; 355 356 cec: cec@10013000 { 357 compatible = "mediatek,mt8173-cec"; 358 reg = <0 0x10013000 0 0xbc>; 359 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 360 clocks = <&infracfg CLK_INFRA_CEC>; 361 status = "disabled"; 362 }; 363 364 vpu: vpu@10020000 { 365 compatible = "mediatek,mt8173-vpu"; 366 reg = <0 0x10020000 0 0x30000>, 367 <0 0x10050000 0 0x100>; 368 reg-names = "tcm", "cfg_reg"; 369 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&topckgen CLK_TOP_SCP_SEL>; 371 clock-names = "main"; 372 memory-region = <&vpu_dma_reserved>; 373 }; 374 375 sysirq: intpol-controller@10200620 { 376 compatible = "mediatek,mt8173-sysirq", 377 "mediatek,mt6577-sysirq"; 378 interrupt-controller; 379 #interrupt-cells = <3>; 380 interrupt-parent = <&gic>; 381 reg = <0 0x10200620 0 0x20>; 382 }; 383 384 iommu: iommu@10205000 { 385 compatible = "mediatek,mt8173-m4u"; 386 reg = <0 0x10205000 0 0x1000>; 387 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 388 clocks = <&infracfg CLK_INFRA_M4U>; 389 clock-names = "bclk"; 390 mediatek,larbs = <&larb0 &larb1 &larb2 391 &larb3 &larb4 &larb5>; 392 #iommu-cells = <1>; 393 }; 394 395 efuse: efuse@10206000 { 396 compatible = "mediatek,mt8173-efuse"; 397 reg = <0 0x10206000 0 0x1000>; 398 }; 399 400 apmixedsys: clock-controller@10209000 { 401 compatible = "mediatek,mt8173-apmixedsys"; 402 reg = <0 0x10209000 0 0x1000>; 403 #clock-cells = <1>; 404 }; 405 406 hdmi_phy: hdmi-phy@10209100 { 407 compatible = "mediatek,mt8173-hdmi-phy"; 408 reg = <0 0x10209100 0 0x24>; 409 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 410 clock-names = "pll_ref"; 411 clock-output-names = "hdmitx_dig_cts"; 412 mediatek,ibias = <0xa>; 413 mediatek,ibias_up = <0x1c>; 414 #clock-cells = <0>; 415 #phy-cells = <0>; 416 status = "disabled"; 417 }; 418 419 mipi_tx0: mipi-dphy@10215000 { 420 compatible = "mediatek,mt8173-mipi-tx"; 421 reg = <0 0x10215000 0 0x1000>; 422 clocks = <&clk26m>; 423 clock-output-names = "mipi_tx0_pll"; 424 #clock-cells = <0>; 425 #phy-cells = <0>; 426 status = "disabled"; 427 }; 428 429 mipi_tx1: mipi-dphy@10216000 { 430 compatible = "mediatek,mt8173-mipi-tx"; 431 reg = <0 0x10216000 0 0x1000>; 432 clocks = <&clk26m>; 433 clock-output-names = "mipi_tx1_pll"; 434 #clock-cells = <0>; 435 #phy-cells = <0>; 436 status = "disabled"; 437 }; 438 439 gic: interrupt-controller@10220000 { 440 compatible = "arm,gic-400"; 441 #interrupt-cells = <3>; 442 interrupt-parent = <&gic>; 443 interrupt-controller; 444 reg = <0 0x10221000 0 0x1000>, 445 <0 0x10222000 0 0x2000>, 446 <0 0x10224000 0 0x2000>, 447 <0 0x10226000 0 0x2000>; 448 interrupts = <GIC_PPI 9 449 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 450 }; 451 452 auxadc: auxadc@11001000 { 453 compatible = "mediatek,mt8173-auxadc"; 454 reg = <0 0x11001000 0 0x1000>; 455 clocks = <&pericfg CLK_PERI_AUXADC>; 456 clock-names = "main"; 457 #io-channel-cells = <1>; 458 }; 459 460 uart0: serial@11002000 { 461 compatible = "mediatek,mt8173-uart", 462 "mediatek,mt6577-uart"; 463 reg = <0 0x11002000 0 0x400>; 464 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 465 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 466 clock-names = "baud", "bus"; 467 status = "disabled"; 468 }; 469 470 uart1: serial@11003000 { 471 compatible = "mediatek,mt8173-uart", 472 "mediatek,mt6577-uart"; 473 reg = <0 0x11003000 0 0x400>; 474 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 475 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 476 clock-names = "baud", "bus"; 477 status = "disabled"; 478 }; 479 480 uart2: serial@11004000 { 481 compatible = "mediatek,mt8173-uart", 482 "mediatek,mt6577-uart"; 483 reg = <0 0x11004000 0 0x400>; 484 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 485 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 486 clock-names = "baud", "bus"; 487 status = "disabled"; 488 }; 489 490 uart3: serial@11005000 { 491 compatible = "mediatek,mt8173-uart", 492 "mediatek,mt6577-uart"; 493 reg = <0 0x11005000 0 0x400>; 494 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 495 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 496 clock-names = "baud", "bus"; 497 status = "disabled"; 498 }; 499 500 i2c0: i2c@11007000 { 501 compatible = "mediatek,mt8173-i2c"; 502 reg = <0 0x11007000 0 0x70>, 503 <0 0x11000100 0 0x80>; 504 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 505 clock-div = <16>; 506 clocks = <&pericfg CLK_PERI_I2C0>, 507 <&pericfg CLK_PERI_AP_DMA>; 508 clock-names = "main", "dma"; 509 pinctrl-names = "default"; 510 pinctrl-0 = <&i2c0_pins_a>; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 status = "disabled"; 514 }; 515 516 i2c1: i2c@11008000 { 517 compatible = "mediatek,mt8173-i2c"; 518 reg = <0 0x11008000 0 0x70>, 519 <0 0x11000180 0 0x80>; 520 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 521 clock-div = <16>; 522 clocks = <&pericfg CLK_PERI_I2C1>, 523 <&pericfg CLK_PERI_AP_DMA>; 524 clock-names = "main", "dma"; 525 pinctrl-names = "default"; 526 pinctrl-0 = <&i2c1_pins_a>; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 status = "disabled"; 530 }; 531 532 i2c2: i2c@11009000 { 533 compatible = "mediatek,mt8173-i2c"; 534 reg = <0 0x11009000 0 0x70>, 535 <0 0x11000200 0 0x80>; 536 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 537 clock-div = <16>; 538 clocks = <&pericfg CLK_PERI_I2C2>, 539 <&pericfg CLK_PERI_AP_DMA>; 540 clock-names = "main", "dma"; 541 pinctrl-names = "default"; 542 pinctrl-0 = <&i2c2_pins_a>; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 status = "disabled"; 546 }; 547 548 spi: spi@1100a000 { 549 compatible = "mediatek,mt8173-spi"; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 reg = <0 0x1100a000 0 0x1000>; 553 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 554 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 555 <&topckgen CLK_TOP_SPI_SEL>, 556 <&pericfg CLK_PERI_SPI0>; 557 clock-names = "parent-clk", "sel-clk", "spi-clk"; 558 status = "disabled"; 559 }; 560 561 thermal: thermal@1100b000 { 562 #thermal-sensor-cells = <0>; 563 compatible = "mediatek,mt8173-thermal"; 564 reg = <0 0x1100b000 0 0x1000>; 565 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 566 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 567 clock-names = "therm", "auxadc"; 568 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 569 mediatek,auxadc = <&auxadc>; 570 mediatek,apmixedsys = <&apmixedsys>; 571 }; 572 573 nor_flash: spi@1100d000 { 574 compatible = "mediatek,mt8173-nor"; 575 reg = <0 0x1100d000 0 0xe0>; 576 clocks = <&pericfg CLK_PERI_SPI>, 577 <&topckgen CLK_TOP_SPINFI_IFR_SEL>; 578 clock-names = "spi", "sf"; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 status = "disabled"; 582 }; 583 584 i2c3: i2c@11010000 { 585 compatible = "mediatek,mt8173-i2c"; 586 reg = <0 0x11010000 0 0x70>, 587 <0 0x11000280 0 0x80>; 588 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 589 clock-div = <16>; 590 clocks = <&pericfg CLK_PERI_I2C3>, 591 <&pericfg CLK_PERI_AP_DMA>; 592 clock-names = "main", "dma"; 593 pinctrl-names = "default"; 594 pinctrl-0 = <&i2c3_pins_a>; 595 #address-cells = <1>; 596 #size-cells = <0>; 597 status = "disabled"; 598 }; 599 600 i2c4: i2c@11011000 { 601 compatible = "mediatek,mt8173-i2c"; 602 reg = <0 0x11011000 0 0x70>, 603 <0 0x11000300 0 0x80>; 604 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 605 clock-div = <16>; 606 clocks = <&pericfg CLK_PERI_I2C4>, 607 <&pericfg CLK_PERI_AP_DMA>; 608 clock-names = "main", "dma"; 609 pinctrl-names = "default"; 610 pinctrl-0 = <&i2c4_pins_a>; 611 #address-cells = <1>; 612 #size-cells = <0>; 613 status = "disabled"; 614 }; 615 616 hdmiddc0: i2c@11012000 { 617 compatible = "mediatek,mt8173-hdmi-ddc"; 618 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 619 reg = <0 0x11012000 0 0x1C>; 620 clocks = <&pericfg CLK_PERI_I2C5>; 621 clock-names = "ddc-i2c"; 622 }; 623 624 i2c6: i2c@11013000 { 625 compatible = "mediatek,mt8173-i2c"; 626 reg = <0 0x11013000 0 0x70>, 627 <0 0x11000080 0 0x80>; 628 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 629 clock-div = <16>; 630 clocks = <&pericfg CLK_PERI_I2C6>, 631 <&pericfg CLK_PERI_AP_DMA>; 632 clock-names = "main", "dma"; 633 pinctrl-names = "default"; 634 pinctrl-0 = <&i2c6_pins_a>; 635 #address-cells = <1>; 636 #size-cells = <0>; 637 status = "disabled"; 638 }; 639 640 afe: audio-controller@11220000 { 641 compatible = "mediatek,mt8173-afe-pcm"; 642 reg = <0 0x11220000 0 0x1000>; 643 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 644 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; 645 clocks = <&infracfg CLK_INFRA_AUDIO>, 646 <&topckgen CLK_TOP_AUDIO_SEL>, 647 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 648 <&topckgen CLK_TOP_APLL1_DIV0>, 649 <&topckgen CLK_TOP_APLL2_DIV0>, 650 <&topckgen CLK_TOP_I2S0_M_SEL>, 651 <&topckgen CLK_TOP_I2S1_M_SEL>, 652 <&topckgen CLK_TOP_I2S2_M_SEL>, 653 <&topckgen CLK_TOP_I2S3_M_SEL>, 654 <&topckgen CLK_TOP_I2S3_B_SEL>; 655 clock-names = "infra_sys_audio_clk", 656 "top_pdn_audio", 657 "top_pdn_aud_intbus", 658 "bck0", 659 "bck1", 660 "i2s0_m", 661 "i2s1_m", 662 "i2s2_m", 663 "i2s3_m", 664 "i2s3_b"; 665 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 666 <&topckgen CLK_TOP_AUD_2_SEL>; 667 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 668 <&topckgen CLK_TOP_APLL2>; 669 }; 670 671 mmc0: mmc@11230000 { 672 compatible = "mediatek,mt8173-mmc", 673 "mediatek,mt8135-mmc"; 674 reg = <0 0x11230000 0 0x1000>; 675 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 676 clocks = <&pericfg CLK_PERI_MSDC30_0>, 677 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 678 clock-names = "source", "hclk"; 679 status = "disabled"; 680 }; 681 682 mmc1: mmc@11240000 { 683 compatible = "mediatek,mt8173-mmc", 684 "mediatek,mt8135-mmc"; 685 reg = <0 0x11240000 0 0x1000>; 686 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 687 clocks = <&pericfg CLK_PERI_MSDC30_1>, 688 <&topckgen CLK_TOP_AXI_SEL>; 689 clock-names = "source", "hclk"; 690 status = "disabled"; 691 }; 692 693 mmc2: mmc@11250000 { 694 compatible = "mediatek,mt8173-mmc", 695 "mediatek,mt8135-mmc"; 696 reg = <0 0x11250000 0 0x1000>; 697 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 698 clocks = <&pericfg CLK_PERI_MSDC30_2>, 699 <&topckgen CLK_TOP_AXI_SEL>; 700 clock-names = "source", "hclk"; 701 status = "disabled"; 702 }; 703 704 mmc3: mmc@11260000 { 705 compatible = "mediatek,mt8173-mmc", 706 "mediatek,mt8135-mmc"; 707 reg = <0 0x11260000 0 0x1000>; 708 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 709 clocks = <&pericfg CLK_PERI_MSDC30_3>, 710 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 711 clock-names = "source", "hclk"; 712 status = "disabled"; 713 }; 714 715 usb30: usb@11270000 { 716 compatible = "mediatek,mt8173-xhci"; 717 reg = <0 0x11270000 0 0x1000>, 718 <0 0x11280700 0 0x0100>; 719 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 720 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>; 721 clocks = <&topckgen CLK_TOP_USB30_SEL>, 722 <&pericfg CLK_PERI_USB0>, 723 <&pericfg CLK_PERI_USB1>; 724 clock-names = "sys_ck", 725 "wakeup_deb_p0", 726 "wakeup_deb_p1"; 727 phys = <&phy_port0 PHY_TYPE_USB3>, 728 <&phy_port1 PHY_TYPE_USB2>; 729 mediatek,syscon-wakeup = <&pericfg>; 730 status = "okay"; 731 }; 732 733 u3phy: usb-phy@11290000 { 734 compatible = "mediatek,mt8173-u3phy"; 735 reg = <0 0x11290000 0 0x800>; 736 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 737 clock-names = "u3phya_ref"; 738 #address-cells = <2>; 739 #size-cells = <2>; 740 ranges; 741 status = "okay"; 742 743 phy_port0: port@11290800 { 744 reg = <0 0x11290800 0 0x800>; 745 #phy-cells = <1>; 746 status = "okay"; 747 }; 748 749 phy_port1: port@11291000 { 750 reg = <0 0x11291000 0 0x800>; 751 #phy-cells = <1>; 752 status = "okay"; 753 }; 754 }; 755 756 mmsys: clock-controller@14000000 { 757 compatible = "mediatek,mt8173-mmsys", "syscon"; 758 reg = <0 0x14000000 0 0x1000>; 759 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 760 #clock-cells = <1>; 761 }; 762 763 ovl0: ovl@1400c000 { 764 compatible = "mediatek,mt8173-disp-ovl"; 765 reg = <0 0x1400c000 0 0x1000>; 766 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 767 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 768 clocks = <&mmsys CLK_MM_DISP_OVL0>; 769 iommus = <&iommu M4U_PORT_DISP_OVL0>; 770 mediatek,larb = <&larb0>; 771 }; 772 773 ovl1: ovl@1400d000 { 774 compatible = "mediatek,mt8173-disp-ovl"; 775 reg = <0 0x1400d000 0 0x1000>; 776 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 777 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 778 clocks = <&mmsys CLK_MM_DISP_OVL1>; 779 iommus = <&iommu M4U_PORT_DISP_OVL1>; 780 mediatek,larb = <&larb4>; 781 }; 782 783 rdma0: rdma@1400e000 { 784 compatible = "mediatek,mt8173-disp-rdma"; 785 reg = <0 0x1400e000 0 0x1000>; 786 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 787 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 788 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 789 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 790 mediatek,larb = <&larb0>; 791 }; 792 793 rdma1: rdma@1400f000 { 794 compatible = "mediatek,mt8173-disp-rdma"; 795 reg = <0 0x1400f000 0 0x1000>; 796 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 797 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 798 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 799 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 800 mediatek,larb = <&larb4>; 801 }; 802 803 rdma2: rdma@14010000 { 804 compatible = "mediatek,mt8173-disp-rdma"; 805 reg = <0 0x14010000 0 0x1000>; 806 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 807 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 808 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 809 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 810 mediatek,larb = <&larb4>; 811 }; 812 813 wdma0: wdma@14011000 { 814 compatible = "mediatek,mt8173-disp-wdma"; 815 reg = <0 0x14011000 0 0x1000>; 816 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 817 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 818 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 819 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 820 mediatek,larb = <&larb0>; 821 }; 822 823 wdma1: wdma@14012000 { 824 compatible = "mediatek,mt8173-disp-wdma"; 825 reg = <0 0x14012000 0 0x1000>; 826 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 827 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 828 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 829 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 830 mediatek,larb = <&larb4>; 831 }; 832 833 color0: color@14013000 { 834 compatible = "mediatek,mt8173-disp-color"; 835 reg = <0 0x14013000 0 0x1000>; 836 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 837 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 838 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 839 }; 840 841 color1: color@14014000 { 842 compatible = "mediatek,mt8173-disp-color"; 843 reg = <0 0x14014000 0 0x1000>; 844 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 845 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 846 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 847 }; 848 849 aal@14015000 { 850 compatible = "mediatek,mt8173-disp-aal"; 851 reg = <0 0x14015000 0 0x1000>; 852 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 853 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 854 clocks = <&mmsys CLK_MM_DISP_AAL>; 855 }; 856 857 gamma@14016000 { 858 compatible = "mediatek,mt8173-disp-gamma"; 859 reg = <0 0x14016000 0 0x1000>; 860 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 861 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 862 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 863 }; 864 865 merge@14017000 { 866 compatible = "mediatek,mt8173-disp-merge"; 867 reg = <0 0x14017000 0 0x1000>; 868 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 869 clocks = <&mmsys CLK_MM_DISP_MERGE>; 870 }; 871 872 split0: split@14018000 { 873 compatible = "mediatek,mt8173-disp-split"; 874 reg = <0 0x14018000 0 0x1000>; 875 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 876 clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 877 }; 878 879 split1: split@14019000 { 880 compatible = "mediatek,mt8173-disp-split"; 881 reg = <0 0x14019000 0 0x1000>; 882 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 883 clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 884 }; 885 886 ufoe@1401a000 { 887 compatible = "mediatek,mt8173-disp-ufoe"; 888 reg = <0 0x1401a000 0 0x1000>; 889 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 890 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 891 clocks = <&mmsys CLK_MM_DISP_UFOE>; 892 }; 893 894 dsi0: dsi@1401b000 { 895 compatible = "mediatek,mt8173-dsi"; 896 reg = <0 0x1401b000 0 0x1000>; 897 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 898 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 899 clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 900 <&mmsys CLK_MM_DSI0_DIGITAL>, 901 <&mipi_tx0>; 902 clock-names = "engine", "digital", "hs"; 903 phys = <&mipi_tx0>; 904 phy-names = "dphy"; 905 status = "disabled"; 906 }; 907 908 dsi1: dsi@1401c000 { 909 compatible = "mediatek,mt8173-dsi"; 910 reg = <0 0x1401c000 0 0x1000>; 911 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 912 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 913 clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 914 <&mmsys CLK_MM_DSI1_DIGITAL>, 915 <&mipi_tx1>; 916 clock-names = "engine", "digital", "hs"; 917 phy = <&mipi_tx1>; 918 phy-names = "dphy"; 919 status = "disabled"; 920 }; 921 922 dpi0: dpi@1401d000 { 923 compatible = "mediatek,mt8173-dpi"; 924 reg = <0 0x1401d000 0 0x1000>; 925 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 926 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 927 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 928 <&mmsys CLK_MM_DPI_ENGINE>, 929 <&apmixedsys CLK_APMIXED_TVDPLL>; 930 clock-names = "pixel", "engine", "pll"; 931 status = "disabled"; 932 933 port { 934 dpi0_out: endpoint { 935 remote-endpoint = <&hdmi0_in>; 936 }; 937 }; 938 }; 939 940 pwm0: pwm@1401e000 { 941 compatible = "mediatek,mt8173-disp-pwm", 942 "mediatek,mt6595-disp-pwm"; 943 reg = <0 0x1401e000 0 0x1000>; 944 #pwm-cells = <2>; 945 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 946 <&mmsys CLK_MM_DISP_PWM0MM>; 947 clock-names = "main", "mm"; 948 status = "disabled"; 949 }; 950 951 pwm1: pwm@1401f000 { 952 compatible = "mediatek,mt8173-disp-pwm", 953 "mediatek,mt6595-disp-pwm"; 954 reg = <0 0x1401f000 0 0x1000>; 955 #pwm-cells = <2>; 956 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 957 <&mmsys CLK_MM_DISP_PWM1MM>; 958 clock-names = "main", "mm"; 959 status = "disabled"; 960 }; 961 962 mutex: mutex@14020000 { 963 compatible = "mediatek,mt8173-disp-mutex"; 964 reg = <0 0x14020000 0 0x1000>; 965 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 966 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 967 clocks = <&mmsys CLK_MM_MUTEX_32K>; 968 }; 969 970 larb0: larb@14021000 { 971 compatible = "mediatek,mt8173-smi-larb"; 972 reg = <0 0x14021000 0 0x1000>; 973 mediatek,smi = <&smi_common>; 974 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 975 clocks = <&mmsys CLK_MM_SMI_LARB0>, 976 <&mmsys CLK_MM_SMI_LARB0>; 977 clock-names = "apb", "smi"; 978 }; 979 980 smi_common: smi@14022000 { 981 compatible = "mediatek,mt8173-smi-common"; 982 reg = <0 0x14022000 0 0x1000>; 983 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 984 clocks = <&mmsys CLK_MM_SMI_COMMON>, 985 <&mmsys CLK_MM_SMI_COMMON>; 986 clock-names = "apb", "smi"; 987 }; 988 989 od@14023000 { 990 compatible = "mediatek,mt8173-disp-od"; 991 reg = <0 0x14023000 0 0x1000>; 992 clocks = <&mmsys CLK_MM_DISP_OD>; 993 }; 994 995 hdmi0: hdmi@14025000 { 996 compatible = "mediatek,mt8173-hdmi"; 997 reg = <0 0x14025000 0 0x400>; 998 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 999 clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1000 <&mmsys CLK_MM_HDMI_PLLCK>, 1001 <&mmsys CLK_MM_HDMI_AUDIO>, 1002 <&mmsys CLK_MM_HDMI_SPDIF>; 1003 clock-names = "pixel", "pll", "bclk", "spdif"; 1004 pinctrl-names = "default"; 1005 pinctrl-0 = <&hdmi_pin>; 1006 phys = <&hdmi_phy>; 1007 phy-names = "hdmi"; 1008 mediatek,syscon-hdmi = <&mmsys 0x900>; 1009 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1010 assigned-clock-parents = <&hdmi_phy>; 1011 status = "disabled"; 1012 1013 ports { 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 1017 port@0 { 1018 reg = <0>; 1019 1020 hdmi0_in: endpoint { 1021 remote-endpoint = <&dpi0_out>; 1022 }; 1023 }; 1024 }; 1025 }; 1026 1027 larb4: larb@14027000 { 1028 compatible = "mediatek,mt8173-smi-larb"; 1029 reg = <0 0x14027000 0 0x1000>; 1030 mediatek,smi = <&smi_common>; 1031 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 1032 clocks = <&mmsys CLK_MM_SMI_LARB4>, 1033 <&mmsys CLK_MM_SMI_LARB4>; 1034 clock-names = "apb", "smi"; 1035 }; 1036 1037 imgsys: clock-controller@15000000 { 1038 compatible = "mediatek,mt8173-imgsys", "syscon"; 1039 reg = <0 0x15000000 0 0x1000>; 1040 #clock-cells = <1>; 1041 }; 1042 1043 larb2: larb@15001000 { 1044 compatible = "mediatek,mt8173-smi-larb"; 1045 reg = <0 0x15001000 0 0x1000>; 1046 mediatek,smi = <&smi_common>; 1047 power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>; 1048 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 1049 <&imgsys CLK_IMG_LARB2_SMI>; 1050 clock-names = "apb", "smi"; 1051 }; 1052 1053 vdecsys: clock-controller@16000000 { 1054 compatible = "mediatek,mt8173-vdecsys", "syscon"; 1055 reg = <0 0x16000000 0 0x1000>; 1056 #clock-cells = <1>; 1057 }; 1058 1059 larb1: larb@16010000 { 1060 compatible = "mediatek,mt8173-smi-larb"; 1061 reg = <0 0x16010000 0 0x1000>; 1062 mediatek,smi = <&smi_common>; 1063 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; 1064 clocks = <&vdecsys CLK_VDEC_CKEN>, 1065 <&vdecsys CLK_VDEC_LARB_CKEN>; 1066 clock-names = "apb", "smi"; 1067 }; 1068 1069 vencsys: clock-controller@18000000 { 1070 compatible = "mediatek,mt8173-vencsys", "syscon"; 1071 reg = <0 0x18000000 0 0x1000>; 1072 #clock-cells = <1>; 1073 }; 1074 1075 larb3: larb@18001000 { 1076 compatible = "mediatek,mt8173-smi-larb"; 1077 reg = <0 0x18001000 0 0x1000>; 1078 mediatek,smi = <&smi_common>; 1079 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; 1080 clocks = <&vencsys CLK_VENC_CKE1>, 1081 <&vencsys CLK_VENC_CKE0>; 1082 clock-names = "apb", "smi"; 1083 }; 1084 1085 vcodec_enc: vcodec@18002000 { 1086 compatible = "mediatek,mt8173-vcodec-enc"; 1087 reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ 1088 <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 1089 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>, 1090 <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 1091 mediatek,larb = <&larb3>, 1092 <&larb5>; 1093 iommus = <&iommu M4U_PORT_VENC_RCPU>, 1094 <&iommu M4U_PORT_VENC_REC>, 1095 <&iommu M4U_PORT_VENC_BSDMA>, 1096 <&iommu M4U_PORT_VENC_SV_COMV>, 1097 <&iommu M4U_PORT_VENC_RD_COMV>, 1098 <&iommu M4U_PORT_VENC_CUR_LUMA>, 1099 <&iommu M4U_PORT_VENC_CUR_CHROMA>, 1100 <&iommu M4U_PORT_VENC_REF_LUMA>, 1101 <&iommu M4U_PORT_VENC_REF_CHROMA>, 1102 <&iommu M4U_PORT_VENC_NBM_RDMA>, 1103 <&iommu M4U_PORT_VENC_NBM_WDMA>, 1104 <&iommu M4U_PORT_VENC_RCPU_SET2>, 1105 <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 1106 <&iommu M4U_PORT_VENC_BSDMA_SET2>, 1107 <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 1108 <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 1109 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 1110 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 1111 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 1112 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 1113 mediatek,vpu = <&vpu>; 1114 clocks = <&topckgen CLK_TOP_VENCPLL_D2>, 1115 <&topckgen CLK_TOP_VENC_SEL>, 1116 <&topckgen CLK_TOP_UNIVPLL1_D2>, 1117 <&topckgen CLK_TOP_VENC_LT_SEL>; 1118 clock-names = "venc_sel_src", 1119 "venc_sel", 1120 "venc_lt_sel_src", 1121 "venc_lt_sel"; 1122 }; 1123 1124 vencltsys: clock-controller@19000000 { 1125 compatible = "mediatek,mt8173-vencltsys", "syscon"; 1126 reg = <0 0x19000000 0 0x1000>; 1127 #clock-cells = <1>; 1128 }; 1129 1130 larb5: larb@19001000 { 1131 compatible = "mediatek,mt8173-smi-larb"; 1132 reg = <0 0x19001000 0 0x1000>; 1133 mediatek,smi = <&smi_common>; 1134 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; 1135 clocks = <&vencltsys CLK_VENCLT_CKE1>, 1136 <&vencltsys CLK_VENCLT_CKE0>; 1137 clock-names = "apb", "smi"; 1138 }; 1139 }; 1140}; 1141 1142