| /arch/powerpc/platforms/powernv/ |
| D | idle.c | 53 uint64_t pir = get_hard_smp_processor_id(cpu); in pnv_save_sprs_for_deep_states() local
69 rc = opal_slw_set_reg(pir, SPRN_HSPRG0, hsprg0_val); in pnv_save_sprs_for_deep_states()
73 rc = opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val); in pnv_save_sprs_for_deep_states()
80 rc = opal_slw_set_reg(pir, SPRN_HMEER, hmeer_val); in pnv_save_sprs_for_deep_states()
84 rc = opal_slw_set_reg(pir, SPRN_HID0, hid0_val); in pnv_save_sprs_for_deep_states()
88 rc = opal_slw_set_reg(pir, SPRN_HID1, hid1_val); in pnv_save_sprs_for_deep_states()
92 rc = opal_slw_set_reg(pir, SPRN_HID4, hid4_val); in pnv_save_sprs_for_deep_states()
96 rc = opal_slw_set_reg(pir, SPRN_HID5, hid5_val); in pnv_save_sprs_for_deep_states()
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| D | opal-hmi.c | 90 be32_to_cpu(hmi_evt->u.xstop_error.u.pir)); in print_core_checkstop_reason()
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| /arch/powerpc/include/uapi/asm/ |
| D | kvm_para.h | 58 __u32 pir; member
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| D | kvm.h | 200 __u32 pir; /* read-only */ member
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| /arch/powerpc/kvm/ |
| D | e500_emulate.c | 70 int pir = param & PPC_DBELL_PIR_MASK; in kvmppc_e500_emul_msgsnd() local
78 int cpir = cvcpu->arch.shared->pir; in kvmppc_e500_emul_msgsnd()
79 if ((param & PPC_DBELL_MSG_BRDCAST) || (cpir == pir)) { in kvmppc_e500_emul_msgsnd()
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| D | booke.c | 1383 vcpu->arch.shared->pir = vcpu->vcpu_id; in kvm_arch_vcpu_setup()
1531 sregs->u.e.pir = vcpu->vcpu_id; in get_sregs_arch206()
1544 if (sregs->u.e.pir != vcpu->vcpu_id) in set_sregs_arch206()
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| D | mpic.c | 218 uint32_t pir; /* Processor initialization register */ member
522 opp->pir = 0; in openpic_reset()
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| /arch/x86/kvm/ |
| D | lapic.h | 73 void __kvm_apic_update_irr(u32 *pir, void *regs);
74 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir);
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| D | lapic.c | 345 void __kvm_apic_update_irr(u32 *pir, void *regs) in __kvm_apic_update_irr() argument
350 pir_val = xchg(&pir[i], 0); in __kvm_apic_update_irr()
357 void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir) in kvm_apic_update_irr() argument
361 __kvm_apic_update_irr(pir, apic->regs); in kvm_apic_update_irr()
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| D | vmx.c | 481 u32 pir[8]; /* Posted interrupt requested */ member
516 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir); in pi_test_and_set_pir()
4922 max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256); in vmx_complete_nested_posted_interrupt()
4925 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page); in vmx_complete_nested_posted_interrupt()
5028 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir); in vmx_sync_pir_to_irr()
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| /arch/powerpc/platforms/85xx/ |
| D | smp.c | 43 u32 pir; member
253 out_be32(&spin_table->pir, hw_cpu); in smp_85xx_start_cpu()
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| /arch/powerpc/sysdev/ |
| D | mpic.c | 1909 u32 pir; in mpic_reset_core() local
1914 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); in mpic_reset_core()
1915 pir |= (1 << cpuid); in mpic_reset_core()
1916 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); in mpic_reset_core()
1920 pir &= ~(1 << cpuid); in mpic_reset_core()
1921 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); in mpic_reset_core()
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| /arch/powerpc/kernel/ |
| D | sysfs.c | 487 SYSFS_SPRSETUP(pir, SPRN_PIR);
497 static DEVICE_ATTR(pir, 0400, show_pir, NULL);
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| D | kvm.c | 536 kvm_patch_ins_lwz(inst, magic_var(pir), inst_rt); in kvm_check_ins()
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| /arch/powerpc/include/asm/ |
| D | opal-api.h | 581 __be32 pir; /* for CHECKSTOP_TYPE_CORE */ member
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| /arch/powerpc/boot/dts/ |
| D | virtex440-ml507.dts | 128 xlnx,pir = <0xf>;
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| D | virtex440-ml510.dts | 123 xlnx,pir = <0xf>;
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