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Searched refs:BLC_PWM_CTL (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/gma500/
Dpsb_intel_lvds.c77 ret = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_get_max_backlight()
89 REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL); in psb_intel_lvds_get_max_backlight()
159 REG_WRITE(BLC_PWM_CTL, in psb_lvds_pwm_set_brightness()
201 blc_pwm_ctl = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_set_backlight()
203 REG_WRITE(BLC_PWM_CTL, in psb_intel_lvds_set_backlight()
280 lvds_priv->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_save()
321 REG_WRITE(BLC_PWM_CTL, lvds_priv->saveBLC_PWM_CTL); in psb_intel_lvds_restore()
447 mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_prepare()
Dcdv_device.c91 u32 max = REG_READ(BLC_PWM_CTL); in cdv_get_max_backlight()
109 u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in cdv_get_brightness()
145 blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in cdv_set_brightness()
146 REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl | in cdv_set_brightness()
289 regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); in cdv_save_display_registers()
362 REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL); in cdv_restore_display_registers()
Dcdv_intel_lvds.c75 retval = ((REG_READ(BLC_PWM_CTL) & in cdv_intel_lvds_get_max_backlight()
145 REG_WRITE(BLC_PWM_CTL,
183 REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in cdv_intel_lvds_set_backlight()
184 REG_WRITE(BLC_PWM_CTL, in cdv_intel_lvds_set_backlight()
331 mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); in cdv_intel_lvds_prepare()
Doaktrail_device.c78 max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16; in oaktrail_set_brightness()
95 REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl); in oaktrail_set_brightness()
136 REG_WRITE(BLC_PWM_CTL, value | (value << 16)); in device_backlight_init()
246 regs->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL); in oaktrail_save_display_registers()
376 PSB_WVDC32(regs->saveBLC_PWM_CTL, BLC_PWM_CTL); in oaktrail_restore_display_registers()
Doaktrail_lvds.c174 mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); in oaktrail_lvds_prepare()
187 ret = ((REG_READ(BLC_PWM_CTL) & in oaktrail_lvds_get_max_backlight()
Dpsb_device.c98 REG_WRITE(BLC_PWM_CTL, in psb_backlight_setup()
Dpsb_intel_reg.h92 #define BLC_PWM_CTL 0x61254 macro
/drivers/gpu/drm/i915/
Dintel_panel.c500 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in i9xx_get_backlight()
586 tmp = I915_READ(BLC_PWM_CTL) & ~mask; in i9xx_set_backlight()
587 I915_WRITE(BLC_PWM_CTL, tmp | level); in i9xx_set_backlight()
897 ctl = I915_READ(BLC_PWM_CTL); in i9xx_enable_backlight()
900 I915_WRITE(BLC_PWM_CTL, 0); in i9xx_enable_backlight()
913 I915_WRITE(BLC_PWM_CTL, ctl); in i9xx_enable_backlight()
914 POSTING_READ(BLC_PWM_CTL); in i9xx_enable_backlight()
947 I915_WRITE(BLC_PWM_CTL, ctl); in i965_enable_backlight()
1504 ctl = I915_READ(BLC_PWM_CTL); in i9xx_setup_backlight()
1547 ctl = I915_READ(BLC_PWM_CTL); in i965_setup_backlight()
Di915_reg.h3811 #define BLC_PWM_CTL _MMIO(dev_priv->info.display_mmio_offset + 0x61254) macro