Searched refs:CGU_CLK_DIV (Results 1 – 4 of 4) sorted by relevance
| /drivers/clk/ingenic/ |
| D | jz4780-cgu.c | 297 "cpu", CGU_CLK_DIV,
303 "l2cache", CGU_CLK_DIV,
309 "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
324 "ahb2", CGU_CLK_DIV,
330 "pclk", CGU_CLK_DIV,
336 "ddr", CGU_CLK_MUX | CGU_CLK_DIV,
343 "vpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
352 "i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV,
365 "lcd0pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
373 "lcd1pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
[all …]
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| D | jz4740-cgu.c | 91 "pll half", CGU_CLK_DIV,
97 "cclk", CGU_CLK_DIV,
103 "hclk", CGU_CLK_DIV,
109 "pclk", CGU_CLK_DIV,
115 "mclk", CGU_CLK_DIV,
121 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
128 "lcd_pclk", CGU_CLK_DIV,
134 "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
142 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
150 "mmc", CGU_CLK_DIV | CGU_CLK_GATE,
[all …]
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| D | cgu.c | 323 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_recalc_rate()
371 if (clk_info->type & CGU_CLK_DIV) in ingenic_clk_round_rate()
394 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_set_rate()
623 if (caps & CGU_CLK_DIV) { in ingenic_register_clock()
624 caps &= ~CGU_CLK_DIV; in ingenic_register_clock()
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| D | cgu.h | 150 CGU_CLK_DIV = BIT(5), enumerator
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