| /drivers/clk/samsung/ |
| D | clk-exynos5420.c | 346 PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
348 PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
349 PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
350 PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
351 PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
352 PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
353 PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
354 PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
355 PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
356 PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
[all …]
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| D | clk-exynos5260.c | 91 PNAME(mout_aud_pll_user_p) = {"fin_pll", "fout_aud_pll"};
92 PNAME(mout_sclk_aud_i2s_p) = {"mout_aud_pll_user", "ioclk_i2s_cdclk"};
93 PNAME(mout_sclk_aud_pcm_p) = {"mout_aud_pll_user", "ioclk_pcm_extclk"};
172 PNAME(mout_phyclk_dptx_phy_ch3_txd_clk_user_p) = {"fin_pll",
174 PNAME(mout_phyclk_dptx_phy_ch2_txd_clk_user_p) = {"fin_pll",
176 PNAME(mout_phyclk_dptx_phy_ch1_txd_clk_user_p) = {"fin_pll",
178 PNAME(mout_phyclk_dptx_phy_ch0_txd_clk_user_p) = {"fin_pll",
180 PNAME(mout_aclk_disp_222_user_p) = {"fin_pll", "dout_aclk_disp_222"};
181 PNAME(mout_sclk_disp_pixel_user_p) = {"fin_pll", "dout_sclk_disp_pixel"};
182 PNAME(mout_aclk_disp_333_user_p) = {"fin_pll", "dout_aclk_disp_333"};
[all …]
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| D | clk-exynos7.c | 49 PNAME(mout_topc_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" };
50 PNAME(mout_topc_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" };
51 PNAME(mout_topc_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" };
52 PNAME(mout_topc_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" };
53 PNAME(mout_topc_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" };
55 PNAME(mout_topc_group2) = { "mout_topc_bus0_pll_half",
59 PNAME(mout_topc_bus0_pll_half_p) = { "mout_topc_bus0_pll",
61 PNAME(mout_topc_bus1_pll_half_p) = { "mout_topc_bus1_pll",
63 PNAME(mout_topc_cc_pll_half_p) = { "mout_topc_cc_pll",
65 PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll",
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| D | clk-exynos5433.c | 177 PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", };
178 PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", };
179 PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", };
180 PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", };
181 PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", };
182 PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", };
183 PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", };
184 PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", };
186 PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",};
187 PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",};
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| D | clk-exynos5250.c | 210 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
211 PNAME(mout_cpu_p) = { "mout_apll", "mout_mpll", };
212 PNAME(mout_mpll_fout_p) = { "fout_mplldiv2", "fout_mpll" };
213 PNAME(mout_mpll_p) = { "fin_pll", "mout_mpll_fout" };
214 PNAME(mout_bpll_fout_p) = { "fout_bplldiv2", "fout_bpll" };
215 PNAME(mout_bpll_p) = { "fin_pll", "mout_bpll_fout" };
216 PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi27m" };
217 PNAME(mout_vpll_p) = { "mout_vpllsrc", "fout_vpll" };
218 PNAME(mout_cpll_p) = { "fin_pll", "fout_cpll" };
219 PNAME(mout_epll_p) = { "fin_pll", "fout_epll" };
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| D | clk-exynos4415.c | 208 PNAME(mout_g3d_pllsrc_p) = { "fin_pll", };
210 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
211 PNAME(mout_g3d_pll_p) = { "fin_pll", "fout_g3d_pll", };
212 PNAME(mout_isp_pll_p) = { "fin_pll", "fout_isp_pll", };
213 PNAME(mout_disp_pll_p) = { "fin_pll", "fout_disp_pll", };
215 PNAME(mout_mpll_user_p) = { "fin_pll", "div_mpll_pre", };
216 PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
217 PNAME(mout_core_p) = { "mout_apll", "mout_mpll_user_c", };
218 PNAME(mout_hpm_p) = { "mout_apll", "mout_mpll_user_c", };
220 PNAME(mout_ebi_p) = { "div_aclk_200", "div_aclk_160", };
[all …]
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| D | clk-exynos4.c | 397 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
398 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
399 PNAME(mout_epll_p) = { "fin_pll", "fout_epll", };
400 PNAME(mout_vpllsrc_p) = { "fin_pll", "sclk_hdmi24m", };
401 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
402 PNAME(sclk_evpll_p) = { "sclk_epll", "sclk_vpll", };
403 PNAME(mout_mfc_p) = { "mout_mfc0", "mout_mfc1", };
404 PNAME(mout_g3d_p) = { "mout_g3d0", "mout_g3d1", };
405 PNAME(mout_g2d_p) = { "mout_g2d0", "mout_g2d1", };
406 PNAME(mout_hdmi_p) = { "sclk_pixel", "sclk_hdmiphy", };
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| D | clk-exynos5410.c | 70 PNAME(apll_p) = { "fin_pll", "fout_apll", };
71 PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
72 PNAME(cpll_p) = { "fin_pll", "fout_cpll" };
73 PNAME(epll_p) = { "fin_pll", "fout_epll" };
74 PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
75 PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
77 PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", };
78 PNAME(mout_kfc_p) = { "mout_kpll", "sclk_mpll", };
80 PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", };
81 PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", };
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| D | clk-exynos3250.c | 177 PNAME(mout_vpllsrc_p) = { "fin_pll", };
179 PNAME(mout_apll_p) = { "fin_pll", "fout_apll", };
180 PNAME(mout_mpll_p) = { "fin_pll", "fout_mpll", };
181 PNAME(mout_vpll_p) = { "fin_pll", "fout_vpll", };
182 PNAME(mout_upll_p) = { "fin_pll", "fout_upll", };
184 PNAME(mout_mpll_user_p) = { "fin_pll", "div_mpll_pre", };
185 PNAME(mout_epll_user_p) = { "fin_pll", "mout_epll", };
186 PNAME(mout_core_p) = { "mout_apll", "mout_mpll_user_c", };
187 PNAME(mout_hpm_p) = { "mout_apll", "mout_mpll_user_c", };
189 PNAME(mout_ebi_p) = { "div_aclk_200", "div_aclk_160", };
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| D | clk-s3c2412.c | 121 PNAME(erefclk_p) = { "xti", "xti", "xti", "ext" };
122 PNAME(urefclk_p) = { "xti", "xti", "xti", "ext" };
124 PNAME(camclk_p) = { "usysclk", "hclk" };
125 PNAME(usbclk_p) = { "usysclk", "hclk" };
126 PNAME(i2sclk_p) = { "erefclk", "mpll" };
127 PNAME(uartclk_p) = { "erefclk", "mpll" };
128 PNAME(usysclk_p) = { "urefclk", "upll" };
129 PNAME(msysclk_p) = { "mdivclk", "mpll" };
130 PNAME(mdivclk_p) = { "xti", "div_xti" };
131 PNAME(armclk_p) = { "armdiv", "hclk" };
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| D | clk-s3c64xx.c | 152 PNAME(spi_mmc_p) = { "mout_epll", "dout_mpll", "fin_pll", "clk27m" };
153 PNAME(uart_p) = { "mout_epll", "dout_mpll" };
154 PNAME(audio0_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk0",
156 PNAME(audio1_p) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk1",
158 PNAME(mfc_p) = { "hclkx2", "mout_epll" };
159 PNAME(apll_p) = { "fin_pll", "fout_apll" };
160 PNAME(mpll_p) = { "fin_pll", "fout_mpll" };
161 PNAME(epll_p) = { "fin_pll", "fout_epll" };
162 PNAME(hclkx2_p) = { "mout_mpll", "mout_apll" };
165 PNAME(scaler_lcd_p6400) = { "mout_epll", "dout_mpll", "none", "none" };
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| D | clk-s3c2443.c | 109 PNAME(epllref_p) = { "mpllref", "mpllref", "xti", "ext" };
110 PNAME(esysclk_p) = { "epllref", "epll" };
111 PNAME(mpllref_p) = { "xti", "mdivclk" };
112 PNAME(msysclk_p) = { "mpllref", "mpll" };
113 PNAME(armclk_p) = { "armdiv" , "hclk" };
114 PNAME(i2s0_p) = { "div_i2s0", "ext_i2s", "epllref", "epllref" };
230 PNAME(s3c2416_hsmmc0_p) = { "sclk_hsmmc0", "sclk_hsmmcext" };
231 PNAME(s3c2416_hsmmc1_p) = { "sclk_hsmmc1", "sclk_hsmmcext" };
232 PNAME(s3c2416_hsspi0_p) = { "hsspi0_epll", "hsspi0_mpll" };
322 PNAME(s3c2450_cam_p) = { "div_cam", "hclk" };
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| D | clk-s3c2410.c | 96 PNAME(fclk_p) = { "mpll", "div_slow" };
269 PNAME(hclk_p) = { "fclk", "div_hclk_2", "div_hclk_4", "div_hclk_3" };
270 PNAME(armclk_p) = { "fclk", "hclk" };
319 PNAME(s3c2440_camif_p) = { "upll", "ff_cam" };
335 PNAME(s3c2442_camif_p) = { "upll", "ff_cam", "upll", "upll_3" };
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| D | clk-exynos5440.c | 29 PNAME(mout_armclk_p) = { "cplla", "cpllb" };
30 PNAME(mout_spi_p) = { "div125", "div200" };
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| D | clk.h | 264 #define PNAME(x) static const char * const x[] __initconst macro
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| /drivers/clk/zte/ |
| D | clk-zx296718.c | 104 PNAME(osc) = {
109 PNAME(dbg_wclk_p) = {
116 PNAME(a72_coreclk_p) = {
127 PNAME(cpu_periclk_p) = {
138 PNAME(a53_coreclk_p) = {
149 PNAME(sec_wclk_p) = {
160 PNAME(sd_nand_wclk_p) = {
171 PNAME(emmc_wclk_p) = {
182 PNAME(clk32_p) = {
187 PNAME(usb_ref24m_p) = {
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| D | clk.h | 15 #define PNAME(x) static const char *x[] macro
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| /drivers/clk/pistachio/ |
| D | clk-pistachio.c | 108 PNAME(mux_xtal_audio_refclk) = { "xtal", "audio_clk_in_gate" };
109 PNAME(mux_xtal_mips) = { "xtal", "mips_pll" };
110 PNAME(mux_xtal_audio) = { "xtal", "audio_pll", "audio_in" };
111 PNAME(mux_audio_debug) = { "audio_pll_mux", "debug_mux" };
112 PNAME(mux_xtal_rpu_v) = { "xtal", "rpu_v_pll" };
113 PNAME(mux_xtal_rpu_l) = { "xtal", "rpu_l_pll" };
114 PNAME(mux_rpu_l_mips) = { "rpu_l_pll_mux", "mips_pll_mux" };
115 PNAME(mux_xtal_wifi) = { "xtal", "wifi_pll" };
116 PNAME(mux_xtal_wifi_div4) = { "xtal", "wifi_div4" };
117 PNAME(mux_xtal_wifi_div8) = { "xtal", "wifi_div8" };
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| D | clk.h | 40 #define PNAME(x) static const char *x[] __initconst macro
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| /drivers/clk/rockchip/ |
| D | clk-rk3228.c | 120 PNAME(mux_pll_p) = { "clk_24m", "xin24m" };
122 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr", "apll_ddr" };
123 PNAME(mux_armclk_p) = { "apll_core", "gpll_core", "dpll_core" };
124 PNAME(mux_usb480m_phy_p) = { "usb480m_phy0", "usb480m_phy1" };
125 PNAME(mux_usb480m_p) = { "usb480m_phy", "xin24m" };
126 PNAME(mux_hdmiphy_p) = { "hdmiphy_phy", "xin24m" };
127 PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu", "hdmiphy_aclk_cpu" };
129 PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy" "usb480m" };
130 PNAME(mux_pll_src_3plls_p) = { "cpll", "gpll", "hdmiphy" };
131 PNAME(mux_pll_src_2plls_p) = { "cpll", "gpll" };
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| D | clk-rk3399.c | 113 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
115 PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src",
119 PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src",
123 PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src",
127 PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
131 PNAME(mux_cci_trace_p) = { "cpll_cci_trace",
133 PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs",
135 PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src",
138 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
139 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
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| D | clk-rk3368.c | 98 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
99 PNAME(mux_armclkb_p) = { "apllb_core", "gpllb_core" };
100 PNAME(mux_armclkl_p) = { "aplll_core", "gplll_core" };
101 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
102 PNAME(mux_cs_src_p) = { "apllb_cs", "aplll_cs", "gpll_cs"};
103 PNAME(mux_aclk_bus_src_p) = { "cpll_aclk_bus", "gpll_aclk_bus" };
105 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
106 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
107 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
108 PNAME(mux_pll_src_cpll_gpll_usb_p) = { "cpll", "gpll", "usbphy_480m" };
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| D | clk-rk3036.c | 122 PNAME(mux_pll_p) = { "xin24m", "xin24m" };
124 PNAME(mux_armclk_p) = { "apll", "gpll_armclk" };
125 PNAME(mux_busclk_p) = { "apll", "dpll_cpu", "gpll_cpu" };
126 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
127 PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" };
128 PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" };
130 PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" };
132 PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
133 PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
134 PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
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| D | clk-rk3288.c | 174 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
175 PNAME(mux_armclk_p) = { "apll_core", "gpll_core" };
176 PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
177 PNAME(mux_aclk_cpu_src_p) = { "cpll_aclk_cpu", "gpll_aclk_cpu" };
179 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
180 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
181 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
182 PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usbphy480m_src" };
183 PNAME(mux_pll_src_cpll_gll_usb_npll_p) = { "cpll", "gpll", "usbphy480m_src", "npll" };
185 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "xin24m" };
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| D | clk-rk3188.c | 203 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
204 PNAME(mux_armclk_p) = { "apll", "gpll_armclk" };
205 PNAME(mux_ddrphy_p) = { "dpll", "gpll_ddr" };
206 PNAME(mux_pll_src_gpll_cpll_p) = { "gpll", "cpll" };
207 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
208 PNAME(mux_aclk_cpu_p) = { "apll", "gpll" };
209 PNAME(mux_sclk_cif0_p) = { "cif0_pre", "xin24m" };
210 PNAME(mux_sclk_i2s0_p) = { "i2s0_pre", "i2s0_frac", "xin12m" };
211 PNAME(mux_sclk_spdif_p) = { "spdif_pre", "spdif_frac", "xin12m" };
212 PNAME(mux_sclk_uart0_p) = { "uart0_pre", "uart0_frac", "xin24m" };
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