| /drivers/clk/zte/ |
| D | clk.h | 17 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ argument
21 .parent_names = (const char *[]) { _parent }, \
58 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \ argument
65 .hw.init = CLK_HW_INIT(_name, _parent, &zx_pll_ops, \
69 #define ZX296718_PLL(_name, _parent, _reg, _table) \ argument
70 ZX_PLL(_name, _parent, _reg, _table, 0, 30)
77 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \ argument
85 _parent, \
97 #define FFACTOR(_id, _name, _parent, _mult, _div, _flag) \ argument
103 _parent, \
[all …]
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| /drivers/clk/renesas/ |
| D | renesas-cpg-mssr.h | 48 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
49 DEF_TYPE(_name, _id, _type, .parent = _parent)
53 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ argument
54 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
55 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
56 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
57 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
58 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
75 #define DEF_MOD(_name, _mod, _parent...) \ argument
76 { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
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| D | rcar-gen3-cpg.h | 25 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
26 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
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| /drivers/clk/sunxi-ng/ |
| D | ccu_div.h | 86 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
96 _parent, \
103 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
106 SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
148 #define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ argument
157 _parent, \
163 #define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \ argument
165 SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \
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| D | ccu_common.h | 27 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \ argument
31 .parent_names = (const char *[]) { _parent }, \
45 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \ argument
51 _parent, \
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| D | ccu_nm.h | 40 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
58 _parent, \
64 #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
76 _parent, \
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| D | ccu_phase.h | 28 #define SUNXI_CCU_PHASE(_struct, _name, _parent, _reg, _shift, _width, _flags) \ argument
35 _parent, \
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| D | ccu_gate.h | 27 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
33 _parent, \
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| D | ccu_mult.h | 26 #define SUNXI_CCU_N_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
35 _parent, \
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| D | ccu_nk.h | 41 #define SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(_struct, _name, _parent, _reg, \ argument
56 _parent, \
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| D | ccu_nkmp.h | 40 #define SUNXI_CCU_NKMP_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
56 _parent, \
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| D | ccu_nkm.h | 62 #define SUNXI_CCU_NKM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
76 _parent, \
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| /drivers/clk/mediatek/ |
| D | clk-mt8173.c | 610 #define GATE_ICG(_id, _name, _parent, _shift) { \ argument
613 .parent_name = _parent, \
649 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
652 .parent_name = _parent, \
658 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
661 .parent_name = _parent, \
725 #define GATE_IMG(_id, _name, _parent, _shift) { \ argument
728 .parent_name = _parent, \
756 #define GATE_MM0(_id, _name, _parent, _shift) { \ argument
759 .parent_name = _parent, \
[all …]
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| D | clk-mtk.h | 36 #define FIXED_CLK(_id, _name, _parent, _rate) { \ argument
39 .parent = _parent, \
54 #define FACTOR(_id, _name, _parent, _mult, _div) { \ argument
57 .parent_name = _parent, \
124 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, _div_width, _div_shift) { \ argument
126 .parent = _parent, \
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| D | clk-mt8135.c | 411 #define GATE_ICG(_id, _name, _parent, _shift) { \ argument
414 .parent_name = _parent, \
448 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
451 .parent_name = _parent, \
457 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
460 .parent_name = _parent, \
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| /drivers/clk/uniphier/ |
| D | clk-uniphier.h | 68 #define UNIPHIER_CLK_FACTOR(_name, _idx, _parent, _mult, _div) \ argument
74 .parent_name = (_parent), \
81 #define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit) \ argument
87 .parent_name = (_parent), \
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| /drivers/clk/pxa/ |
| D | clk-pxa25x.c | 220 #define DUMMY_CLK(_con_id, _dev_id, _parent) \ argument
221 { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
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| D | clk-pxa3xx.c | 301 #define DUMMY_CLK(_con_id, _dev_id, _parent) \ argument
302 { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
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| D | clk-pxa27x.c | 356 #define DUMMY_CLK(_con_id, _dev_id, _parent) \ argument
357 { .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
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| /drivers/iio/pressure/ |
| D | zpa2326.c | 742 #define zpa2326_init_runtime(_parent) argument
743 #define zpa2326_fini_runtime(_parent) argument
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| /drivers/platform/x86/ |
| D | thinkpad_acpi.c | 523 static const acpi_handle * const object##_parent __initconst = \
671 drv_acpi_handle_init(#object, &object##_handle, *object##_parent, \
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