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Searched refs:bus_width (Results 1 – 25 of 82) sorted by relevance

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/drivers/mtd/lpddr/
Dlpddr2_nvm.c85 int bus_width; member
103 static inline u_int build_mr_cfgmask(u_int bus_width) in build_mr_cfgmask() argument
107 if (bus_width == 0x0004) /* x32 device */ in build_mr_cfgmask()
116 static inline u_int build_sr_ok_datamask(u_int bus_width) in build_sr_ok_datamask() argument
120 if (bus_width == 0x0004) /* x32 device */ in build_sr_ok_datamask()
134 val = map->pfow_base + offset*pcm_data->bus_width; in ow_reg_add()
149 writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18, in ow_enable()
164 writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18, in ow_disable()
181 u_int sr_ok_datamask = build_sr_ok_datamask(pcm_data->bus_width); in lpddr2_nvm_do_op()
200 if (pcm_data->bus_width == 0x0004) { /* 2x16 devices stacked */ in lpddr2_nvm_do_op()
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/drivers/memory/
Dmvebu-devbus.c76 u32 bus_width; member
127 err = of_property_read_u32(node, "devbus,bus-width", &r->bus_width); in devbus_get_timing_params()
139 if (r->bus_width == 8) in devbus_get_timing_params()
140 r->bus_width = 0; in devbus_get_timing_params()
141 else if (r->bus_width == 16) in devbus_get_timing_params()
142 r->bus_width = 1; in devbus_get_timing_params()
144 dev_err(devbus->dev, "invalid bus width %d\n", r->bus_width); in devbus_get_timing_params()
227 r->bus_width << ORION_DEV_WIDTH_SHIFT | in devbus_orion_set_timing_params()
248 value = r->bus_width << ARMADA_DEV_WIDTH_SHIFT | in devbus_armada_set_timing_params()
/drivers/mmc/core/
Dmmc.c669 static int mmc_compare_ext_csds(struct mmc_card *card, unsigned bus_width) in mmc_compare_ext_csds() argument
674 if (bus_width == MMC_BUS_WIDTH_1) in mmc_compare_ext_csds()
838 unsigned int bus_width) in __mmc_select_powerclass() argument
850 pwrclass_val = (bus_width <= EXT_CSD_BUS_WIDTH_8) ? in __mmc_select_powerclass()
868 pwrclass_val = (bus_width <= EXT_CSD_BUS_WIDTH_8) ? in __mmc_select_powerclass()
872 pwrclass_val = (bus_width == EXT_CSD_DDR_BUS_WIDTH_8) ? in __mmc_select_powerclass()
882 if (bus_width & (EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_BUS_WIDTH_8)) in __mmc_select_powerclass()
903 u32 bus_width, ext_csd_bits; in mmc_select_powerclass() local
910 bus_width = host->ios.bus_width; in mmc_select_powerclass()
912 if (bus_width == MMC_BUS_WIDTH_1) in mmc_select_powerclass()
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Dhost.c181 u32 bus_width; in mmc_of_parse() local
190 if (device_property_read_u32(dev, "bus-width", &bus_width) < 0) { in mmc_of_parse()
193 bus_width = 1; in mmc_of_parse()
196 switch (bus_width) { in mmc_of_parse()
207 "Invalid \"bus-width\" value %u!\n", bus_width); in mmc_of_parse()
Dmmc_ops.c606 if (ios->bus_width == MMC_BUS_WIDTH_8) { in mmc_send_tuning()
609 } else if (ios->bus_width == MMC_BUS_WIDTH_4) { in mmc_send_tuning()
741 int mmc_bus_test(struct mmc_card *card, u8 bus_width) in mmc_bus_test() argument
745 if (bus_width == MMC_BUS_WIDTH_8) in mmc_bus_test()
747 else if (bus_width == MMC_BUS_WIDTH_4) in mmc_bus_test()
749 else if (bus_width == MMC_BUS_WIDTH_1) in mmc_bus_test()
Ddebugfs.c117 ios->bus_width, 1 << ios->bus_width); in mmc_ios_show()
Dmmc_ops.h27 int mmc_bus_test(struct mmc_card *card, u8 bus_width);
/drivers/dma/
Dimg-mdc-dma.c144 unsigned int bus_width; member
231 if (IS_ALIGNED(dst, mdma->bus_width) && in mdc_list_desc_config()
232 IS_ALIGNED(src, mdma->bus_width)) in mdc_list_desc_config()
233 max_burst = mdma->bus_width * mdma->max_burst_mult; in mdc_list_desc_config()
235 max_burst = mdma->bus_width * (mdma->max_burst_mult - 1); in mdc_list_desc_config()
240 mdc_set_read_width(ldesc, mdma->bus_width); in mdc_list_desc_config()
248 mdc_set_write_width(ldesc, mdma->bus_width); in mdc_list_desc_config()
254 mdc_set_read_width(ldesc, mdma->bus_width); in mdc_list_desc_config()
255 mdc_set_write_width(ldesc, mdma->bus_width); in mdc_list_desc_config()
363 if (width > mchan->mdma->bus_width) in mdc_check_slave_width()
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/drivers/staging/rts5208/
Dsd.c285 u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len, argument
319 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
356 u8 *cmd, int cmd_len, u16 byte_cnt, u16 blk_cnt, u8 bus_width, argument
400 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
1061 static int sd_check_spec(struct rtsx_chip *chip, u8 bus_width) argument
1080 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width,
1218 u8 func_group, u8 func_to_switch, u8 bus_width) argument
1249 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, bus_width,
1329 u8 func_group, u8 func_to_switch, u8 bus_width) argument
1343 func_to_switch, bus_width);
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/drivers/mmc/host/
Dsdhci-pltfm.c74 u32 bus_width; in sdhci_get_of_property() local
80 (of_property_read_u32(np, "bus-width", &bus_width) == 0 && in sdhci_get_of_property()
81 bus_width == 1)) in sdhci_get_of_property()
Dmxs-mmc.c70 unsigned char bus_width; member
390 ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) | in mxs_mmc_adtc()
505 if (ios->bus_width == MMC_BUS_WIDTH_8) in mxs_mmc_set_ios()
506 host->bus_width = 2; in mxs_mmc_set_ios()
507 else if (ios->bus_width == MMC_BUS_WIDTH_4) in mxs_mmc_set_ios()
508 host->bus_width = 1; in mxs_mmc_set_ios()
510 host->bus_width = 0; in mxs_mmc_set_ios()
Dsdhci-pxav2.c135 u32 bus_width; in pxav2_get_mmc_pdata() local
145 of_property_read_u32(np, "bus-width", &bus_width); in pxav2_get_mmc_pdata()
146 if (bus_width == 8) in pxav2_get_mmc_pdata()
Dtmio_mmc_pio.c736 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4 || in tmio_mmc_start_data()
737 host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) { in tmio_mmc_start_data()
861 unsigned char bus_width) in tmio_mmc_set_bus_width() argument
867 if (bus_width == MMC_BUS_WIDTH_1) in tmio_mmc_set_bus_width()
869 else if (bus_width == MMC_BUS_WIDTH_8) in tmio_mmc_set_bus_width()
921 tmio_mmc_set_bus_width(host, ios->bus_width); in tmio_mmc_set_ios()
925 tmio_mmc_set_bus_width(host, ios->bus_width); in tmio_mmc_set_ios()
Dsdhci-tegra.c190 static void tegra_sdhci_set_bus_width(struct sdhci_host *host, int bus_width) in tegra_sdhci_set_bus_width() argument
196 (bus_width == MMC_BUS_WIDTH_8)) { in tegra_sdhci_set_bus_width()
201 if (bus_width == MMC_BUS_WIDTH_4) in tegra_sdhci_set_bus_width()
Ddw_mmc-rockchip.c49 if (ios->bus_width == MMC_BUS_WIDTH_8 && in dw_mci_rk3288_set_ios()
114 if (ios->bus_width == MMC_BUS_WIDTH_8) in dw_mci_rk3288_set_ios()
Ds3cmci.h62 int bus_width; member
/drivers/usb/isp1760/
Disp1760-if.c207 u32 bus_width = 0; in isp1760_plat_probe() local
213 of_property_read_u32(dp, "bus-width", &bus_width); in isp1760_plat_probe()
214 if (bus_width == 16) in isp1760_plat_probe()
/drivers/staging/greybus/
Dsdio.c594 u8 bus_width; in gb_mmc_set_ios() local
628 switch (ios->bus_width) { in gb_mmc_set_ios()
630 bus_width = GB_SDIO_BUS_WIDTH_1; in gb_mmc_set_ios()
634 bus_width = GB_SDIO_BUS_WIDTH_4; in gb_mmc_set_ios()
637 bus_width = GB_SDIO_BUS_WIDTH_8; in gb_mmc_set_ios()
640 request.bus_width = bus_width; in gb_mmc_set_ios()
/drivers/block/
Dxsysace.c203 int bus_width; /* 0 := 8 bit; 1 := 16 bit */ member
1012 if (ace->bus_width == ACE_BUS_WIDTH_16) { in ace_setup()
1095 int irq, int bus_width) in ace_alloc() argument
1117 ace->bus_width = bus_width; in ace_alloc()
1155 int bus_width = ACE_BUS_WIDTH_16; /* FIXME: should not be hard coded */ in ace_probe() local
1166 bus_width = ACE_BUS_WIDTH_8; in ace_probe()
1176 return ace_alloc(&dev->dev, id, physaddr, irq, bus_width); in ace_probe()
/drivers/dma/xilinx/
Dzynqmp_dma.c237 u32 bus_width; member
970 chan->bus_width = ZYNQMP_DMA_BUS_WIDTH_64; in zynqmp_dma_chan_probe()
973 err = of_property_read_u32(node, "xlnx,bus-width", &chan->bus_width); in zynqmp_dma_chan_probe()
979 if (chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_64 && in zynqmp_dma_chan_probe()
980 chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_128) { in zynqmp_dma_chan_probe()
1093 p->dst_addr_widths = BIT(zdev->chan->bus_width / 8); in zynqmp_dma_probe()
1094 p->src_addr_widths = BIT(zdev->chan->bus_width / 8); in zynqmp_dma_probe()
/drivers/edac/
Dfsl_ddr_edac.c278 u32 bus_width; in fsl_mc_check() local
305 bus_width = (ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG) & in fsl_mc_check()
307 if (bus_width == 64) in fsl_mc_check()
330 if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) { in fsl_mc_check()
/drivers/media/platform/exynos4-is/
Dfimc-reg.c591 u16 bus_width; member
606 u32 bus_width, cfg = 0; in fimc_hw_set_camera_source() local
615 bus_width = pix_desc[i].bus_width; in fimc_hw_set_camera_source()
628 if (bus_width == 8) in fimc_hw_set_camera_source()
630 else if (bus_width == 16) in fimc_hw_set_camera_source()
/drivers/scsi/aic7xxx/
Daic7xxx_core.c173 u_int bus_width);
177 u_int bus_width, u_int ppr_options);
2421 u_int *bus_width, role_t role) in ahc_validate_width() argument
2423 switch (*bus_width) { in ahc_validate_width()
2427 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; in ahc_validate_width()
2432 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; in ahc_validate_width()
2437 *bus_width = min((u_int)tinfo->user.width, *bus_width); in ahc_validate_width()
2439 *bus_width = min((u_int)tinfo->goal.width, *bus_width); in ahc_validate_width()
3081 u_int bus_width) in ahc_construct_wdtr() argument
3084 ahc->msgout_buf + ahc->msgout_index, bus_width); in ahc_construct_wdtr()
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/drivers/gpio/
Dgpio-htc-egpio.c295 if ((pdata->bus_width != 16) && (pdata->bus_width != 32)) in egpio_probe()
297 ei->bus_shift = fls(pdata->bus_width - 1) - 3; in egpio_probe()
/drivers/media/i2c/
Dsmiapp-pll.h45 uint8_t bus_width; member

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