Searched refs:cache_line_size (Results 1 – 23 of 23) sorted by relevance
112 u32 db_per_page = PAGE_SIZE / cache_line_size(); in mlx5_alloc_db_pgdir()144 u32 db_per_page = PAGE_SIZE / cache_line_size(); in mlx5_alloc_db_from_pgdir()156 offset = db->index * cache_line_size(); in mlx5_alloc_db_from_pgdir()203 u32 db_per_page = PAGE_SIZE / cache_line_size(); in mlx5_db_free()
118 if (elem_size < cache_line_size()) in rxe_queue_init()119 elem_size = cache_line_size(); in rxe_queue_init()
148 } __aligned(cache_line_size());
397 char carea[cache_line_size()]; /* 128B each */
161 uint16_t cache_line_size; member
241 props->cacheline_size = cache->cache_line_size; in kfd_parse_subtype_cache()
62 hpx->t0->cache_line_size = fields[2].integer.value; in decode_type0_hpx_record()241 hpp->t0->cache_line_size = fields[0].integer.value; in acpi_run_hpp()
1398 .cache_line_size = 8,1418 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size); in program_hpp_type0()
98 u8 cache_line_size; member494 bridge->cache_line_size = 0x10; in mvebu_sw_pci_bridge_init()529 bridge->latency_timer << 8 | bridge->cache_line_size; in mvebu_sw_pci_bridge_read()
1977 const int cache_line_size = 64; in set_sdram_scrub_rate() local1985 cache_line_size * 1000000; in set_sdram_scrub_rate()2017 const u32 cache_line_size = 64; in get_sdram_scrub_rate() local2037 1000000 * cache_line_size; in get_sdram_scrub_rate()
727 rcache->cpu_rcaches = __alloc_percpu(sizeof(*cpu_rcache), cache_line_size()); in init_iova_rcaches()
273 const uint32_t cacheline_size = cache_line_size(); in select_doorbell_cacheline()
266 if (cache_line_size() == 128 || cache_line_size() == 256) { in mlx4_enable_cqe_eqe_stride()275 if (cache_line_size() != 32 && cache_line_size() != 64) in mlx4_enable_cqe_eqe_stride()
1878 (ilog2(cache_line_size()) - 4) << 5; in mlx4_INIT_HCA()1927 dev->caps.eqe_size = cache_line_size(); in mlx4_INIT_HCA()1928 dev->caps.cqe_size = cache_line_size(); in mlx4_INIT_HCA()
6287 unsigned int cache_line_size) in t4_fixup_host_params() argument6291 unsigned int stat_len = cache_line_size > 64 ? 128 : 64; in t4_fixup_host_params()6292 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size; in t4_fixup_host_params()
1575 unsigned int cache_line_size);
1407 u8 cache_line_size; member
110 .cache_line_size = 0x20,135 .cache_line_size = 0x20,160 .cache_line_size = 0x20,10167 ioa_cfg->chip_cfg->cache_line_size); in ipr_probe_ioa()
948 cqe_size = cache_line_size() == 128 ? 128 : 64; in mlx5_ib_create_cq()
1045 resp.cache_line_size = cache_line_size(); in mlx5_ib_alloc_ucontext()
998 cache_line_size(), in fwtty_port_activate()
303 cache_line_size())
379 ETH_HLEN + ETH_FCS_LEN, cache_line_size())