1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #if defined(CONFIG_X86)
41 #include <asm/pat.h>
42 #endif
43 #include <linux/sched.h>
44 #include <linux/delay.h>
45 #include <rdma/ib_user_verbs.h>
46 #include <rdma/ib_addr.h>
47 #include <rdma/ib_cache.h>
48 #include <linux/mlx5/port.h>
49 #include <linux/mlx5/vport.h>
50 #include <linux/list.h>
51 #include <rdma/ib_smi.h>
52 #include <rdma/ib_umem.h>
53 #include <linux/in.h>
54 #include <linux/etherdevice.h>
55 #include <linux/mlx5/fs.h>
56 #include "mlx5_ib.h"
57
58 #define DRIVER_NAME "mlx5_ib"
59 #define DRIVER_VERSION "2.2-1"
60 #define DRIVER_RELDATE "Feb 2014"
61
62 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
63 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
64 MODULE_LICENSE("Dual BSD/GPL");
65 MODULE_VERSION(DRIVER_VERSION);
66
67 static int deprecated_prof_sel = 2;
68 module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
69 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
70
71 static char mlx5_version[] =
72 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
73 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
74
75 enum {
76 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
77 };
78
79 static enum rdma_link_layer
mlx5_port_type_cap_to_rdma_ll(int port_type_cap)80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
81 {
82 switch (port_type_cap) {
83 case MLX5_CAP_PORT_TYPE_IB:
84 return IB_LINK_LAYER_INFINIBAND;
85 case MLX5_CAP_PORT_TYPE_ETH:
86 return IB_LINK_LAYER_ETHERNET;
87 default:
88 return IB_LINK_LAYER_UNSPECIFIED;
89 }
90 }
91
92 static enum rdma_link_layer
mlx5_ib_port_link_layer(struct ib_device * device,u8 port_num)93 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
94 {
95 struct mlx5_ib_dev *dev = to_mdev(device);
96 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
97
98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
99 }
100
mlx5_netdev_event(struct notifier_block * this,unsigned long event,void * ptr)101 static int mlx5_netdev_event(struct notifier_block *this,
102 unsigned long event, void *ptr)
103 {
104 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
105 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
106 roce.nb);
107
108 switch (event) {
109 case NETDEV_REGISTER:
110 case NETDEV_UNREGISTER:
111 write_lock(&ibdev->roce.netdev_lock);
112 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
113 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
114 NULL : ndev;
115 write_unlock(&ibdev->roce.netdev_lock);
116 break;
117
118 case NETDEV_UP:
119 case NETDEV_DOWN: {
120 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
121 struct net_device *upper = NULL;
122
123 if (lag_ndev) {
124 upper = netdev_master_upper_dev_get(lag_ndev);
125 dev_put(lag_ndev);
126 }
127
128 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
129 && ibdev->ib_active) {
130 struct ib_event ibev = {0};
131
132 ibev.device = &ibdev->ib_dev;
133 ibev.event = (event == NETDEV_UP) ?
134 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
135 ibev.element.port_num = 1;
136 ib_dispatch_event(&ibev);
137 }
138 break;
139 }
140
141 default:
142 break;
143 }
144
145 return NOTIFY_DONE;
146 }
147
mlx5_ib_get_netdev(struct ib_device * device,u8 port_num)148 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
149 u8 port_num)
150 {
151 struct mlx5_ib_dev *ibdev = to_mdev(device);
152 struct net_device *ndev;
153
154 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
155 if (ndev)
156 return ndev;
157
158 /* Ensure ndev does not disappear before we invoke dev_hold()
159 */
160 read_lock(&ibdev->roce.netdev_lock);
161 ndev = ibdev->roce.netdev;
162 if (ndev)
163 dev_hold(ndev);
164 read_unlock(&ibdev->roce.netdev_lock);
165
166 return ndev;
167 }
168
mlx5_query_port_roce(struct ib_device * device,u8 port_num,struct ib_port_attr * props)169 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
170 struct ib_port_attr *props)
171 {
172 struct mlx5_ib_dev *dev = to_mdev(device);
173 struct net_device *ndev, *upper;
174 enum ib_mtu ndev_ib_mtu;
175 u16 qkey_viol_cntr;
176
177 memset(props, 0, sizeof(*props));
178
179 props->port_cap_flags |= IB_PORT_CM_SUP;
180 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
181
182 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
183 roce_address_table_size);
184 props->max_mtu = IB_MTU_4096;
185 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
186 props->pkey_tbl_len = 1;
187 props->state = IB_PORT_DOWN;
188 props->phys_state = 3;
189
190 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
191 props->qkey_viol_cntr = qkey_viol_cntr;
192
193 ndev = mlx5_ib_get_netdev(device, port_num);
194 if (!ndev)
195 return 0;
196
197 if (mlx5_lag_is_active(dev->mdev)) {
198 rcu_read_lock();
199 upper = netdev_master_upper_dev_get_rcu(ndev);
200 if (upper) {
201 dev_put(ndev);
202 ndev = upper;
203 dev_hold(ndev);
204 }
205 rcu_read_unlock();
206 }
207
208 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
209 props->state = IB_PORT_ACTIVE;
210 props->phys_state = 5;
211 }
212
213 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
214
215 dev_put(ndev);
216
217 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
218
219 props->active_width = IB_WIDTH_4X; /* TODO */
220 props->active_speed = IB_SPEED_QDR; /* TODO */
221
222 return 0;
223 }
224
ib_gid_to_mlx5_roce_addr(const union ib_gid * gid,const struct ib_gid_attr * attr,void * mlx5_addr)225 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
226 const struct ib_gid_attr *attr,
227 void *mlx5_addr)
228 {
229 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
230 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
231 source_l3_address);
232 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
233 source_mac_47_32);
234
235 if (!gid)
236 return;
237
238 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
239
240 if (is_vlan_dev(attr->ndev)) {
241 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
242 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
243 }
244
245 switch (attr->gid_type) {
246 case IB_GID_TYPE_IB:
247 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
248 break;
249 case IB_GID_TYPE_ROCE_UDP_ENCAP:
250 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
251 break;
252
253 default:
254 WARN_ON(true);
255 }
256
257 if (attr->gid_type != IB_GID_TYPE_IB) {
258 if (ipv6_addr_v4mapped((void *)gid))
259 MLX5_SET_RA(mlx5_addr, roce_l3_type,
260 MLX5_ROCE_L3_TYPE_IPV4);
261 else
262 MLX5_SET_RA(mlx5_addr, roce_l3_type,
263 MLX5_ROCE_L3_TYPE_IPV6);
264 }
265
266 if ((attr->gid_type == IB_GID_TYPE_IB) ||
267 !ipv6_addr_v4mapped((void *)gid))
268 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
269 else
270 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
271 }
272
set_roce_addr(struct ib_device * device,u8 port_num,unsigned int index,const union ib_gid * gid,const struct ib_gid_attr * attr)273 static int set_roce_addr(struct ib_device *device, u8 port_num,
274 unsigned int index,
275 const union ib_gid *gid,
276 const struct ib_gid_attr *attr)
277 {
278 struct mlx5_ib_dev *dev = to_mdev(device);
279 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
280 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
281 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
282 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
283
284 if (ll != IB_LINK_LAYER_ETHERNET)
285 return -EINVAL;
286
287 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
288
289 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
290 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
291 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
292 }
293
mlx5_ib_add_gid(struct ib_device * device,u8 port_num,unsigned int index,const union ib_gid * gid,const struct ib_gid_attr * attr,__always_unused void ** context)294 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
295 unsigned int index, const union ib_gid *gid,
296 const struct ib_gid_attr *attr,
297 __always_unused void **context)
298 {
299 return set_roce_addr(device, port_num, index, gid, attr);
300 }
301
mlx5_ib_del_gid(struct ib_device * device,u8 port_num,unsigned int index,__always_unused void ** context)302 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
303 unsigned int index, __always_unused void **context)
304 {
305 return set_roce_addr(device, port_num, index, NULL, NULL);
306 }
307
mlx5_get_roce_udp_sport(struct mlx5_ib_dev * dev,u8 port_num,int index)308 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
309 int index)
310 {
311 struct ib_gid_attr attr;
312 union ib_gid gid;
313
314 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
315 return 0;
316
317 if (!attr.ndev)
318 return 0;
319
320 dev_put(attr.ndev);
321
322 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
323 return 0;
324
325 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
326 }
327
mlx5_get_roce_gid_type(struct mlx5_ib_dev * dev,u8 port_num,int index,enum ib_gid_type * gid_type)328 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
329 int index, enum ib_gid_type *gid_type)
330 {
331 struct ib_gid_attr attr;
332 union ib_gid gid;
333 int ret;
334
335 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
336 if (ret)
337 return ret;
338
339 if (!attr.ndev)
340 return -ENODEV;
341
342 dev_put(attr.ndev);
343
344 *gid_type = attr.gid_type;
345
346 return 0;
347 }
348
mlx5_use_mad_ifc(struct mlx5_ib_dev * dev)349 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
350 {
351 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
352 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
353 return 0;
354 }
355
356 enum {
357 MLX5_VPORT_ACCESS_METHOD_MAD,
358 MLX5_VPORT_ACCESS_METHOD_HCA,
359 MLX5_VPORT_ACCESS_METHOD_NIC,
360 };
361
mlx5_get_vport_access_method(struct ib_device * ibdev)362 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
363 {
364 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
365 return MLX5_VPORT_ACCESS_METHOD_MAD;
366
367 if (mlx5_ib_port_link_layer(ibdev, 1) ==
368 IB_LINK_LAYER_ETHERNET)
369 return MLX5_VPORT_ACCESS_METHOD_NIC;
370
371 return MLX5_VPORT_ACCESS_METHOD_HCA;
372 }
373
get_atomic_caps(struct mlx5_ib_dev * dev,struct ib_device_attr * props)374 static void get_atomic_caps(struct mlx5_ib_dev *dev,
375 struct ib_device_attr *props)
376 {
377 u8 tmp;
378 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
379 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
380 u8 atomic_req_8B_endianness_mode =
381 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
382
383 /* Check if HW supports 8 bytes standard atomic operations and capable
384 * of host endianness respond
385 */
386 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
387 if (((atomic_operations & tmp) == tmp) &&
388 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
389 (atomic_req_8B_endianness_mode)) {
390 props->atomic_cap = IB_ATOMIC_HCA;
391 } else {
392 props->atomic_cap = IB_ATOMIC_NONE;
393 }
394 }
395
mlx5_query_system_image_guid(struct ib_device * ibdev,__be64 * sys_image_guid)396 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
397 __be64 *sys_image_guid)
398 {
399 struct mlx5_ib_dev *dev = to_mdev(ibdev);
400 struct mlx5_core_dev *mdev = dev->mdev;
401 u64 tmp;
402 int err;
403
404 switch (mlx5_get_vport_access_method(ibdev)) {
405 case MLX5_VPORT_ACCESS_METHOD_MAD:
406 return mlx5_query_mad_ifc_system_image_guid(ibdev,
407 sys_image_guid);
408
409 case MLX5_VPORT_ACCESS_METHOD_HCA:
410 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
411 break;
412
413 case MLX5_VPORT_ACCESS_METHOD_NIC:
414 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
415 break;
416
417 default:
418 return -EINVAL;
419 }
420
421 if (!err)
422 *sys_image_guid = cpu_to_be64(tmp);
423
424 return err;
425
426 }
427
mlx5_query_max_pkeys(struct ib_device * ibdev,u16 * max_pkeys)428 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
429 u16 *max_pkeys)
430 {
431 struct mlx5_ib_dev *dev = to_mdev(ibdev);
432 struct mlx5_core_dev *mdev = dev->mdev;
433
434 switch (mlx5_get_vport_access_method(ibdev)) {
435 case MLX5_VPORT_ACCESS_METHOD_MAD:
436 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
437
438 case MLX5_VPORT_ACCESS_METHOD_HCA:
439 case MLX5_VPORT_ACCESS_METHOD_NIC:
440 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
441 pkey_table_size));
442 return 0;
443
444 default:
445 return -EINVAL;
446 }
447 }
448
mlx5_query_vendor_id(struct ib_device * ibdev,u32 * vendor_id)449 static int mlx5_query_vendor_id(struct ib_device *ibdev,
450 u32 *vendor_id)
451 {
452 struct mlx5_ib_dev *dev = to_mdev(ibdev);
453
454 switch (mlx5_get_vport_access_method(ibdev)) {
455 case MLX5_VPORT_ACCESS_METHOD_MAD:
456 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
457
458 case MLX5_VPORT_ACCESS_METHOD_HCA:
459 case MLX5_VPORT_ACCESS_METHOD_NIC:
460 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
461
462 default:
463 return -EINVAL;
464 }
465 }
466
mlx5_query_node_guid(struct mlx5_ib_dev * dev,__be64 * node_guid)467 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
468 __be64 *node_guid)
469 {
470 u64 tmp;
471 int err;
472
473 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
474 case MLX5_VPORT_ACCESS_METHOD_MAD:
475 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
476
477 case MLX5_VPORT_ACCESS_METHOD_HCA:
478 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
479 break;
480
481 case MLX5_VPORT_ACCESS_METHOD_NIC:
482 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
483 break;
484
485 default:
486 return -EINVAL;
487 }
488
489 if (!err)
490 *node_guid = cpu_to_be64(tmp);
491
492 return err;
493 }
494
495 struct mlx5_reg_node_desc {
496 u8 desc[IB_DEVICE_NODE_DESC_MAX];
497 };
498
mlx5_query_node_desc(struct mlx5_ib_dev * dev,char * node_desc)499 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
500 {
501 struct mlx5_reg_node_desc in;
502
503 if (mlx5_use_mad_ifc(dev))
504 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
505
506 memset(&in, 0, sizeof(in));
507
508 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
509 sizeof(struct mlx5_reg_node_desc),
510 MLX5_REG_NODE_DESC, 0, 0);
511 }
512
mlx5_ib_query_device(struct ib_device * ibdev,struct ib_device_attr * props,struct ib_udata * uhw)513 static int mlx5_ib_query_device(struct ib_device *ibdev,
514 struct ib_device_attr *props,
515 struct ib_udata *uhw)
516 {
517 struct mlx5_ib_dev *dev = to_mdev(ibdev);
518 struct mlx5_core_dev *mdev = dev->mdev;
519 int err = -ENOMEM;
520 int max_sq_desc;
521 int max_rq_sg;
522 int max_sq_sg;
523 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
524 struct mlx5_ib_query_device_resp resp = {};
525 size_t resp_len;
526 u64 max_tso;
527
528 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
529 if (uhw->outlen && uhw->outlen < resp_len)
530 return -EINVAL;
531 else
532 resp.response_length = resp_len;
533
534 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
535 return -EINVAL;
536
537 memset(props, 0, sizeof(*props));
538 err = mlx5_query_system_image_guid(ibdev,
539 &props->sys_image_guid);
540 if (err)
541 return err;
542
543 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
544 if (err)
545 return err;
546
547 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
548 if (err)
549 return err;
550
551 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
552 (fw_rev_min(dev->mdev) << 16) |
553 fw_rev_sub(dev->mdev);
554 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
555 IB_DEVICE_PORT_ACTIVE_EVENT |
556 IB_DEVICE_SYS_IMAGE_GUID |
557 IB_DEVICE_RC_RNR_NAK_GEN;
558
559 if (MLX5_CAP_GEN(mdev, pkv))
560 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
561 if (MLX5_CAP_GEN(mdev, qkv))
562 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
563 if (MLX5_CAP_GEN(mdev, apm))
564 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
565 if (MLX5_CAP_GEN(mdev, xrc))
566 props->device_cap_flags |= IB_DEVICE_XRC;
567 if (MLX5_CAP_GEN(mdev, imaicl)) {
568 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
569 IB_DEVICE_MEM_WINDOW_TYPE_2B;
570 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
571 /* We support 'Gappy' memory registration too */
572 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
573 }
574 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
575 if (MLX5_CAP_GEN(mdev, sho)) {
576 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
577 /* At this stage no support for signature handover */
578 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
579 IB_PROT_T10DIF_TYPE_2 |
580 IB_PROT_T10DIF_TYPE_3;
581 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
582 IB_GUARD_T10DIF_CSUM;
583 }
584 if (MLX5_CAP_GEN(mdev, block_lb_mc))
585 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
586
587 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
588 if (MLX5_CAP_ETH(mdev, csum_cap))
589 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
590
591 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
592 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
593 if (max_tso) {
594 resp.tso_caps.max_tso = 1 << max_tso;
595 resp.tso_caps.supported_qpts |=
596 1 << IB_QPT_RAW_PACKET;
597 resp.response_length += sizeof(resp.tso_caps);
598 }
599 }
600
601 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
602 resp.rss_caps.rx_hash_function =
603 MLX5_RX_HASH_FUNC_TOEPLITZ;
604 resp.rss_caps.rx_hash_fields_mask =
605 MLX5_RX_HASH_SRC_IPV4 |
606 MLX5_RX_HASH_DST_IPV4 |
607 MLX5_RX_HASH_SRC_IPV6 |
608 MLX5_RX_HASH_DST_IPV6 |
609 MLX5_RX_HASH_SRC_PORT_TCP |
610 MLX5_RX_HASH_DST_PORT_TCP |
611 MLX5_RX_HASH_SRC_PORT_UDP |
612 MLX5_RX_HASH_DST_PORT_UDP;
613 resp.response_length += sizeof(resp.rss_caps);
614 }
615 } else {
616 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
617 resp.response_length += sizeof(resp.tso_caps);
618 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
619 resp.response_length += sizeof(resp.rss_caps);
620 }
621
622 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
623 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
624 props->device_cap_flags |= IB_DEVICE_UD_TSO;
625 }
626
627 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
628 MLX5_CAP_ETH(dev->mdev, scatter_fcs))
629 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
630
631 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
632 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
633
634 props->vendor_part_id = mdev->pdev->device;
635 props->hw_ver = mdev->pdev->revision;
636
637 props->max_mr_size = ~0ull;
638 props->page_size_cap = ~(min_page_size - 1);
639 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
640 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
641 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
642 sizeof(struct mlx5_wqe_data_seg);
643 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
644 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
645 sizeof(struct mlx5_wqe_raddr_seg)) /
646 sizeof(struct mlx5_wqe_data_seg);
647 props->max_sge = min(max_rq_sg, max_sq_sg);
648 props->max_sge_rd = MLX5_MAX_SGE_RD;
649 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
650 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
651 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
652 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
653 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
654 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
655 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
656 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
657 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
658 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
659 props->max_srq_sge = max_rq_sg - 1;
660 props->max_fast_reg_page_list_len =
661 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
662 get_atomic_caps(dev, props);
663 props->masked_atomic_cap = IB_ATOMIC_NONE;
664 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
665 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
666 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
667 props->max_mcast_grp;
668 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
669 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
670 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
671
672 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
673 if (MLX5_CAP_GEN(mdev, pg))
674 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
675 props->odp_caps = dev->odp_caps;
676 #endif
677
678 if (MLX5_CAP_GEN(mdev, cd))
679 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
680
681 if (!mlx5_core_is_pf(mdev))
682 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
683
684 if (mlx5_ib_port_link_layer(ibdev, 1) ==
685 IB_LINK_LAYER_ETHERNET) {
686 props->rss_caps.max_rwq_indirection_tables =
687 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
688 props->rss_caps.max_rwq_indirection_table_size =
689 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
690 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
691 props->max_wq_type_rq =
692 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
693 }
694
695 if (uhw->outlen) {
696 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
697
698 if (err)
699 return err;
700 }
701
702 return 0;
703 }
704
705 enum mlx5_ib_width {
706 MLX5_IB_WIDTH_1X = 1 << 0,
707 MLX5_IB_WIDTH_2X = 1 << 1,
708 MLX5_IB_WIDTH_4X = 1 << 2,
709 MLX5_IB_WIDTH_8X = 1 << 3,
710 MLX5_IB_WIDTH_12X = 1 << 4
711 };
712
translate_active_width(struct ib_device * ibdev,u8 active_width,u8 * ib_width)713 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
714 u8 *ib_width)
715 {
716 struct mlx5_ib_dev *dev = to_mdev(ibdev);
717 int err = 0;
718
719 if (active_width & MLX5_IB_WIDTH_1X) {
720 *ib_width = IB_WIDTH_1X;
721 } else if (active_width & MLX5_IB_WIDTH_2X) {
722 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
723 (int)active_width);
724 err = -EINVAL;
725 } else if (active_width & MLX5_IB_WIDTH_4X) {
726 *ib_width = IB_WIDTH_4X;
727 } else if (active_width & MLX5_IB_WIDTH_8X) {
728 *ib_width = IB_WIDTH_8X;
729 } else if (active_width & MLX5_IB_WIDTH_12X) {
730 *ib_width = IB_WIDTH_12X;
731 } else {
732 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
733 (int)active_width);
734 err = -EINVAL;
735 }
736
737 return err;
738 }
739
mlx5_mtu_to_ib_mtu(int mtu)740 static int mlx5_mtu_to_ib_mtu(int mtu)
741 {
742 switch (mtu) {
743 case 256: return 1;
744 case 512: return 2;
745 case 1024: return 3;
746 case 2048: return 4;
747 case 4096: return 5;
748 default:
749 pr_warn("invalid mtu\n");
750 return -1;
751 }
752 }
753
754 enum ib_max_vl_num {
755 __IB_MAX_VL_0 = 1,
756 __IB_MAX_VL_0_1 = 2,
757 __IB_MAX_VL_0_3 = 3,
758 __IB_MAX_VL_0_7 = 4,
759 __IB_MAX_VL_0_14 = 5,
760 };
761
762 enum mlx5_vl_hw_cap {
763 MLX5_VL_HW_0 = 1,
764 MLX5_VL_HW_0_1 = 2,
765 MLX5_VL_HW_0_2 = 3,
766 MLX5_VL_HW_0_3 = 4,
767 MLX5_VL_HW_0_4 = 5,
768 MLX5_VL_HW_0_5 = 6,
769 MLX5_VL_HW_0_6 = 7,
770 MLX5_VL_HW_0_7 = 8,
771 MLX5_VL_HW_0_14 = 15
772 };
773
translate_max_vl_num(struct ib_device * ibdev,u8 vl_hw_cap,u8 * max_vl_num)774 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
775 u8 *max_vl_num)
776 {
777 switch (vl_hw_cap) {
778 case MLX5_VL_HW_0:
779 *max_vl_num = __IB_MAX_VL_0;
780 break;
781 case MLX5_VL_HW_0_1:
782 *max_vl_num = __IB_MAX_VL_0_1;
783 break;
784 case MLX5_VL_HW_0_3:
785 *max_vl_num = __IB_MAX_VL_0_3;
786 break;
787 case MLX5_VL_HW_0_7:
788 *max_vl_num = __IB_MAX_VL_0_7;
789 break;
790 case MLX5_VL_HW_0_14:
791 *max_vl_num = __IB_MAX_VL_0_14;
792 break;
793
794 default:
795 return -EINVAL;
796 }
797
798 return 0;
799 }
800
mlx5_query_hca_port(struct ib_device * ibdev,u8 port,struct ib_port_attr * props)801 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
802 struct ib_port_attr *props)
803 {
804 struct mlx5_ib_dev *dev = to_mdev(ibdev);
805 struct mlx5_core_dev *mdev = dev->mdev;
806 struct mlx5_hca_vport_context *rep;
807 u16 max_mtu;
808 u16 oper_mtu;
809 int err;
810 u8 ib_link_width_oper;
811 u8 vl_hw_cap;
812
813 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
814 if (!rep) {
815 err = -ENOMEM;
816 goto out;
817 }
818
819 memset(props, 0, sizeof(*props));
820
821 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
822 if (err)
823 goto out;
824
825 props->lid = rep->lid;
826 props->lmc = rep->lmc;
827 props->sm_lid = rep->sm_lid;
828 props->sm_sl = rep->sm_sl;
829 props->state = rep->vport_state;
830 props->phys_state = rep->port_physical_state;
831 props->port_cap_flags = rep->cap_mask1;
832 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
833 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
834 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
835 props->bad_pkey_cntr = rep->pkey_violation_counter;
836 props->qkey_viol_cntr = rep->qkey_violation_counter;
837 props->subnet_timeout = rep->subnet_timeout;
838 props->init_type_reply = rep->init_type_reply;
839 props->grh_required = rep->grh_required;
840
841 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
842 if (err)
843 goto out;
844
845 err = translate_active_width(ibdev, ib_link_width_oper,
846 &props->active_width);
847 if (err)
848 goto out;
849 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
850 if (err)
851 goto out;
852
853 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
854
855 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
856
857 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
858
859 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
860
861 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
862 if (err)
863 goto out;
864
865 err = translate_max_vl_num(ibdev, vl_hw_cap,
866 &props->max_vl_num);
867 out:
868 kfree(rep);
869 return err;
870 }
871
mlx5_ib_query_port(struct ib_device * ibdev,u8 port,struct ib_port_attr * props)872 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
873 struct ib_port_attr *props)
874 {
875 switch (mlx5_get_vport_access_method(ibdev)) {
876 case MLX5_VPORT_ACCESS_METHOD_MAD:
877 return mlx5_query_mad_ifc_port(ibdev, port, props);
878
879 case MLX5_VPORT_ACCESS_METHOD_HCA:
880 return mlx5_query_hca_port(ibdev, port, props);
881
882 case MLX5_VPORT_ACCESS_METHOD_NIC:
883 return mlx5_query_port_roce(ibdev, port, props);
884
885 default:
886 return -EINVAL;
887 }
888 }
889
mlx5_ib_query_gid(struct ib_device * ibdev,u8 port,int index,union ib_gid * gid)890 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
891 union ib_gid *gid)
892 {
893 struct mlx5_ib_dev *dev = to_mdev(ibdev);
894 struct mlx5_core_dev *mdev = dev->mdev;
895
896 switch (mlx5_get_vport_access_method(ibdev)) {
897 case MLX5_VPORT_ACCESS_METHOD_MAD:
898 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
899
900 case MLX5_VPORT_ACCESS_METHOD_HCA:
901 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
902
903 default:
904 return -EINVAL;
905 }
906
907 }
908
mlx5_ib_query_pkey(struct ib_device * ibdev,u8 port,u16 index,u16 * pkey)909 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
910 u16 *pkey)
911 {
912 struct mlx5_ib_dev *dev = to_mdev(ibdev);
913 struct mlx5_core_dev *mdev = dev->mdev;
914
915 switch (mlx5_get_vport_access_method(ibdev)) {
916 case MLX5_VPORT_ACCESS_METHOD_MAD:
917 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
918
919 case MLX5_VPORT_ACCESS_METHOD_HCA:
920 case MLX5_VPORT_ACCESS_METHOD_NIC:
921 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
922 pkey);
923 default:
924 return -EINVAL;
925 }
926 }
927
mlx5_ib_modify_device(struct ib_device * ibdev,int mask,struct ib_device_modify * props)928 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
929 struct ib_device_modify *props)
930 {
931 struct mlx5_ib_dev *dev = to_mdev(ibdev);
932 struct mlx5_reg_node_desc in;
933 struct mlx5_reg_node_desc out;
934 int err;
935
936 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
937 return -EOPNOTSUPP;
938
939 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
940 return 0;
941
942 /*
943 * If possible, pass node desc to FW, so it can generate
944 * a 144 trap. If cmd fails, just ignore.
945 */
946 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
947 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
948 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
949 if (err)
950 return err;
951
952 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
953
954 return err;
955 }
956
mlx5_ib_modify_port(struct ib_device * ibdev,u8 port,int mask,struct ib_port_modify * props)957 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
958 struct ib_port_modify *props)
959 {
960 struct mlx5_ib_dev *dev = to_mdev(ibdev);
961 struct ib_port_attr attr;
962 u32 tmp;
963 int err;
964
965 mutex_lock(&dev->cap_mask_mutex);
966
967 err = mlx5_ib_query_port(ibdev, port, &attr);
968 if (err)
969 goto out;
970
971 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
972 ~props->clr_port_cap_mask;
973
974 err = mlx5_set_port_caps(dev->mdev, port, tmp);
975
976 out:
977 mutex_unlock(&dev->cap_mask_mutex);
978 return err;
979 }
980
mlx5_ib_alloc_ucontext(struct ib_device * ibdev,struct ib_udata * udata)981 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
982 struct ib_udata *udata)
983 {
984 struct mlx5_ib_dev *dev = to_mdev(ibdev);
985 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
986 struct mlx5_ib_alloc_ucontext_resp resp = {};
987 struct mlx5_ib_ucontext *context;
988 struct mlx5_uuar_info *uuari;
989 struct mlx5_uar *uars;
990 int gross_uuars;
991 int num_uars;
992 int ver;
993 int uuarn;
994 int err;
995 int i;
996 size_t reqlen;
997 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
998 max_cqe_version);
999
1000 if (!dev->ib_active)
1001 return ERR_PTR(-EAGAIN);
1002
1003 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
1004 return ERR_PTR(-EINVAL);
1005
1006 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
1007 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1008 ver = 0;
1009 else if (reqlen >= min_req_v2)
1010 ver = 2;
1011 else
1012 return ERR_PTR(-EINVAL);
1013
1014 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
1015 if (err)
1016 return ERR_PTR(err);
1017
1018 if (req.flags)
1019 return ERR_PTR(-EINVAL);
1020
1021 if (req.total_num_uuars > MLX5_MAX_UUARS)
1022 return ERR_PTR(-ENOMEM);
1023
1024 if (req.total_num_uuars == 0)
1025 return ERR_PTR(-EINVAL);
1026
1027 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1028 return ERR_PTR(-EOPNOTSUPP);
1029
1030 if (reqlen > sizeof(req) &&
1031 !ib_is_udata_cleared(udata, sizeof(req),
1032 reqlen - sizeof(req)))
1033 return ERR_PTR(-EOPNOTSUPP);
1034
1035 req.total_num_uuars = ALIGN(req.total_num_uuars,
1036 MLX5_NON_FP_BF_REGS_PER_PAGE);
1037 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
1038 return ERR_PTR(-EINVAL);
1039
1040 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
1041 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
1042 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1043 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1044 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1045 resp.cache_line_size = cache_line_size();
1046 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1047 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1048 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1049 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1050 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1051 resp.cqe_version = min_t(__u8,
1052 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1053 req.max_cqe_version);
1054 resp.response_length = min(offsetof(typeof(resp), response_length) +
1055 sizeof(resp.response_length), udata->outlen);
1056
1057 context = kzalloc(sizeof(*context), GFP_KERNEL);
1058 if (!context)
1059 return ERR_PTR(-ENOMEM);
1060
1061 uuari = &context->uuari;
1062 mutex_init(&uuari->lock);
1063 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
1064 if (!uars) {
1065 err = -ENOMEM;
1066 goto out_ctx;
1067 }
1068
1069 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
1070 sizeof(*uuari->bitmap),
1071 GFP_KERNEL);
1072 if (!uuari->bitmap) {
1073 err = -ENOMEM;
1074 goto out_uar_ctx;
1075 }
1076 /*
1077 * clear all fast path uuars
1078 */
1079 for (i = 0; i < gross_uuars; i++) {
1080 uuarn = i & 3;
1081 if (uuarn == 2 || uuarn == 3)
1082 set_bit(i, uuari->bitmap);
1083 }
1084
1085 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
1086 if (!uuari->count) {
1087 err = -ENOMEM;
1088 goto out_bitmap;
1089 }
1090
1091 for (i = 0; i < num_uars; i++) {
1092 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
1093 if (err)
1094 goto out_count;
1095 }
1096
1097 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1098 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1099 #endif
1100
1101 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1102 err = mlx5_core_alloc_transport_domain(dev->mdev,
1103 &context->tdn);
1104 if (err)
1105 goto out_uars;
1106 }
1107
1108 INIT_LIST_HEAD(&context->vma_private_list);
1109 INIT_LIST_HEAD(&context->db_page_list);
1110 mutex_init(&context->db_page_mutex);
1111
1112 resp.tot_uuars = req.total_num_uuars;
1113 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1114
1115 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1116 resp.response_length += sizeof(resp.cqe_version);
1117
1118 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1119 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE;
1120 resp.response_length += sizeof(resp.cmds_supp_uhw);
1121 }
1122
1123 /*
1124 * We don't want to expose information from the PCI bar that is located
1125 * after 4096 bytes, so if the arch only supports larger pages, let's
1126 * pretend we don't support reading the HCA's core clock. This is also
1127 * forced by mmap function.
1128 */
1129 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1130 if (PAGE_SIZE <= 4096) {
1131 resp.comp_mask |=
1132 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1133 resp.hca_core_clock_offset =
1134 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1135 }
1136 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1137 sizeof(resp.reserved2);
1138 }
1139
1140 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1141 if (err)
1142 goto out_td;
1143
1144 uuari->ver = ver;
1145 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1146 uuari->uars = uars;
1147 uuari->num_uars = num_uars;
1148 context->cqe_version = resp.cqe_version;
1149
1150 return &context->ibucontext;
1151
1152 out_td:
1153 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1154 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1155
1156 out_uars:
1157 for (i--; i >= 0; i--)
1158 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
1159 out_count:
1160 kfree(uuari->count);
1161
1162 out_bitmap:
1163 kfree(uuari->bitmap);
1164
1165 out_uar_ctx:
1166 kfree(uars);
1167
1168 out_ctx:
1169 kfree(context);
1170 return ERR_PTR(err);
1171 }
1172
mlx5_ib_dealloc_ucontext(struct ib_ucontext * ibcontext)1173 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1174 {
1175 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1176 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1177 struct mlx5_uuar_info *uuari = &context->uuari;
1178 int i;
1179
1180 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1181 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1182
1183 for (i = 0; i < uuari->num_uars; i++) {
1184 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
1185 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1186 }
1187
1188 kfree(uuari->count);
1189 kfree(uuari->bitmap);
1190 kfree(uuari->uars);
1191 kfree(context);
1192
1193 return 0;
1194 }
1195
uar_index2pfn(struct mlx5_ib_dev * dev,int index)1196 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1197 {
1198 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
1199 }
1200
get_command(unsigned long offset)1201 static int get_command(unsigned long offset)
1202 {
1203 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1204 }
1205
get_arg(unsigned long offset)1206 static int get_arg(unsigned long offset)
1207 {
1208 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1209 }
1210
get_index(unsigned long offset)1211 static int get_index(unsigned long offset)
1212 {
1213 return get_arg(offset);
1214 }
1215
mlx5_ib_vma_open(struct vm_area_struct * area)1216 static void mlx5_ib_vma_open(struct vm_area_struct *area)
1217 {
1218 /* vma_open is called when a new VMA is created on top of our VMA. This
1219 * is done through either mremap flow or split_vma (usually due to
1220 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1221 * as this VMA is strongly hardware related. Therefore we set the
1222 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1223 * calling us again and trying to do incorrect actions. We assume that
1224 * the original VMA size is exactly a single page, and therefore all
1225 * "splitting" operation will not happen to it.
1226 */
1227 area->vm_ops = NULL;
1228 }
1229
mlx5_ib_vma_close(struct vm_area_struct * area)1230 static void mlx5_ib_vma_close(struct vm_area_struct *area)
1231 {
1232 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1233
1234 /* It's guaranteed that all VMAs opened on a FD are closed before the
1235 * file itself is closed, therefore no sync is needed with the regular
1236 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1237 * However need a sync with accessing the vma as part of
1238 * mlx5_ib_disassociate_ucontext.
1239 * The close operation is usually called under mm->mmap_sem except when
1240 * process is exiting.
1241 * The exiting case is handled explicitly as part of
1242 * mlx5_ib_disassociate_ucontext.
1243 */
1244 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1245
1246 /* setting the vma context pointer to null in the mlx5_ib driver's
1247 * private data, to protect a race condition in
1248 * mlx5_ib_disassociate_ucontext().
1249 */
1250 mlx5_ib_vma_priv_data->vma = NULL;
1251 list_del(&mlx5_ib_vma_priv_data->list);
1252 kfree(mlx5_ib_vma_priv_data);
1253 }
1254
1255 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1256 .open = mlx5_ib_vma_open,
1257 .close = mlx5_ib_vma_close
1258 };
1259
mlx5_ib_set_vma_data(struct vm_area_struct * vma,struct mlx5_ib_ucontext * ctx)1260 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1261 struct mlx5_ib_ucontext *ctx)
1262 {
1263 struct mlx5_ib_vma_private_data *vma_prv;
1264 struct list_head *vma_head = &ctx->vma_private_list;
1265
1266 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1267 if (!vma_prv)
1268 return -ENOMEM;
1269
1270 vma_prv->vma = vma;
1271 vma->vm_private_data = vma_prv;
1272 vma->vm_ops = &mlx5_ib_vm_ops;
1273
1274 list_add(&vma_prv->list, vma_head);
1275
1276 return 0;
1277 }
1278
mlx5_ib_disassociate_ucontext(struct ib_ucontext * ibcontext)1279 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1280 {
1281 int ret;
1282 struct vm_area_struct *vma;
1283 struct mlx5_ib_vma_private_data *vma_private, *n;
1284 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1285 struct task_struct *owning_process = NULL;
1286 struct mm_struct *owning_mm = NULL;
1287
1288 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1289 if (!owning_process)
1290 return;
1291
1292 owning_mm = get_task_mm(owning_process);
1293 if (!owning_mm) {
1294 pr_info("no mm, disassociate ucontext is pending task termination\n");
1295 while (1) {
1296 put_task_struct(owning_process);
1297 usleep_range(1000, 2000);
1298 owning_process = get_pid_task(ibcontext->tgid,
1299 PIDTYPE_PID);
1300 if (!owning_process ||
1301 owning_process->state == TASK_DEAD) {
1302 pr_info("disassociate ucontext done, task was terminated\n");
1303 /* in case task was dead need to release the
1304 * task struct.
1305 */
1306 if (owning_process)
1307 put_task_struct(owning_process);
1308 return;
1309 }
1310 }
1311 }
1312
1313 /* need to protect from a race on closing the vma as part of
1314 * mlx5_ib_vma_close.
1315 */
1316 down_write(&owning_mm->mmap_sem);
1317 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1318 list) {
1319 vma = vma_private->vma;
1320 ret = zap_vma_ptes(vma, vma->vm_start,
1321 PAGE_SIZE);
1322 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1323 /* context going to be destroyed, should
1324 * not access ops any more.
1325 */
1326 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
1327 vma->vm_ops = NULL;
1328 list_del(&vma_private->list);
1329 kfree(vma_private);
1330 }
1331 up_write(&owning_mm->mmap_sem);
1332 mmput(owning_mm);
1333 put_task_struct(owning_process);
1334 }
1335
mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)1336 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1337 {
1338 switch (cmd) {
1339 case MLX5_IB_MMAP_WC_PAGE:
1340 return "WC";
1341 case MLX5_IB_MMAP_REGULAR_PAGE:
1342 return "best effort WC";
1343 case MLX5_IB_MMAP_NC_PAGE:
1344 return "NC";
1345 default:
1346 return NULL;
1347 }
1348 }
1349
uar_mmap(struct mlx5_ib_dev * dev,enum mlx5_ib_mmap_cmd cmd,struct vm_area_struct * vma,struct mlx5_ib_ucontext * context)1350 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1351 struct vm_area_struct *vma,
1352 struct mlx5_ib_ucontext *context)
1353 {
1354 struct mlx5_uuar_info *uuari = &context->uuari;
1355 int err;
1356 unsigned long idx;
1357 phys_addr_t pfn, pa;
1358 pgprot_t prot;
1359
1360 switch (cmd) {
1361 case MLX5_IB_MMAP_WC_PAGE:
1362 /* Some architectures don't support WC memory */
1363 #if defined(CONFIG_X86)
1364 if (!pat_enabled())
1365 return -EPERM;
1366 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1367 return -EPERM;
1368 #endif
1369 /* fall through */
1370 case MLX5_IB_MMAP_REGULAR_PAGE:
1371 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1372 prot = pgprot_writecombine(vma->vm_page_prot);
1373 break;
1374 case MLX5_IB_MMAP_NC_PAGE:
1375 prot = pgprot_noncached(vma->vm_page_prot);
1376 break;
1377 default:
1378 return -EINVAL;
1379 }
1380
1381 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1382 return -EINVAL;
1383
1384 idx = get_index(vma->vm_pgoff);
1385 if (idx >= uuari->num_uars)
1386 return -EINVAL;
1387
1388 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1389 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1390
1391 vma->vm_page_prot = prot;
1392 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1393 PAGE_SIZE, vma->vm_page_prot);
1394 if (err) {
1395 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1396 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1397 return -EAGAIN;
1398 }
1399
1400 pa = pfn << PAGE_SHIFT;
1401 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1402 vma->vm_start, &pa);
1403
1404 return mlx5_ib_set_vma_data(vma, context);
1405 }
1406
mlx5_ib_mmap(struct ib_ucontext * ibcontext,struct vm_area_struct * vma)1407 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1408 {
1409 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1410 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1411 unsigned long command;
1412 phys_addr_t pfn;
1413
1414 command = get_command(vma->vm_pgoff);
1415 switch (command) {
1416 case MLX5_IB_MMAP_WC_PAGE:
1417 case MLX5_IB_MMAP_NC_PAGE:
1418 case MLX5_IB_MMAP_REGULAR_PAGE:
1419 return uar_mmap(dev, command, vma, context);
1420
1421 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1422 return -ENOSYS;
1423
1424 case MLX5_IB_MMAP_CORE_CLOCK:
1425 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1426 return -EINVAL;
1427
1428 if (vma->vm_flags & VM_WRITE)
1429 return -EPERM;
1430
1431 /* Don't expose to user-space information it shouldn't have */
1432 if (PAGE_SIZE > 4096)
1433 return -EOPNOTSUPP;
1434
1435 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1436 pfn = (dev->mdev->iseg_base +
1437 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1438 PAGE_SHIFT;
1439 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1440 PAGE_SIZE, vma->vm_page_prot))
1441 return -EAGAIN;
1442
1443 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1444 vma->vm_start,
1445 (unsigned long long)pfn << PAGE_SHIFT);
1446 break;
1447
1448 default:
1449 return -EINVAL;
1450 }
1451
1452 return 0;
1453 }
1454
mlx5_ib_alloc_pd(struct ib_device * ibdev,struct ib_ucontext * context,struct ib_udata * udata)1455 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1456 struct ib_ucontext *context,
1457 struct ib_udata *udata)
1458 {
1459 struct mlx5_ib_alloc_pd_resp resp;
1460 struct mlx5_ib_pd *pd;
1461 int err;
1462
1463 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1464 if (!pd)
1465 return ERR_PTR(-ENOMEM);
1466
1467 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1468 if (err) {
1469 kfree(pd);
1470 return ERR_PTR(err);
1471 }
1472
1473 if (context) {
1474 resp.pdn = pd->pdn;
1475 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1476 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1477 kfree(pd);
1478 return ERR_PTR(-EFAULT);
1479 }
1480 }
1481
1482 return &pd->ibpd;
1483 }
1484
mlx5_ib_dealloc_pd(struct ib_pd * pd)1485 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1486 {
1487 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1488 struct mlx5_ib_pd *mpd = to_mpd(pd);
1489
1490 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1491 kfree(mpd);
1492
1493 return 0;
1494 }
1495
1496 enum {
1497 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1498 MATCH_CRITERIA_ENABLE_MISC_BIT,
1499 MATCH_CRITERIA_ENABLE_INNER_BIT
1500 };
1501
1502 #define HEADER_IS_ZERO(match_criteria, headers) \
1503 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1504 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
1505
get_match_criteria_enable(u32 * match_criteria)1506 static u8 get_match_criteria_enable(u32 *match_criteria)
1507 {
1508 u8 match_criteria_enable;
1509
1510 match_criteria_enable =
1511 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1512 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1513 match_criteria_enable |=
1514 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1515 MATCH_CRITERIA_ENABLE_MISC_BIT;
1516 match_criteria_enable |=
1517 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1518 MATCH_CRITERIA_ENABLE_INNER_BIT;
1519
1520 return match_criteria_enable;
1521 }
1522
set_proto(void * outer_c,void * outer_v,u8 mask,u8 val)1523 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1524 {
1525 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1526 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1527 }
1528
set_tos(void * outer_c,void * outer_v,u8 mask,u8 val)1529 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1530 {
1531 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1532 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1533 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1534 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1535 }
1536
1537 #define LAST_ETH_FIELD vlan_tag
1538 #define LAST_IB_FIELD sl
1539 #define LAST_IPV4_FIELD tos
1540 #define LAST_IPV6_FIELD traffic_class
1541 #define LAST_TCP_UDP_FIELD src_port
1542
1543 /* Field is the last supported field */
1544 #define FIELDS_NOT_SUPPORTED(filter, field)\
1545 memchr_inv((void *)&filter.field +\
1546 sizeof(filter.field), 0,\
1547 sizeof(filter) -\
1548 offsetof(typeof(filter), field) -\
1549 sizeof(filter.field))
1550
parse_flow_attr(u32 * match_c,u32 * match_v,const union ib_flow_spec * ib_spec)1551 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1552 const union ib_flow_spec *ib_spec)
1553 {
1554 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1555 outer_headers);
1556 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1557 outer_headers);
1558 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1559 misc_parameters);
1560 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1561 misc_parameters);
1562
1563 switch (ib_spec->type) {
1564 case IB_FLOW_SPEC_ETH:
1565 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1566 return -ENOTSUPP;
1567
1568 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1569 dmac_47_16),
1570 ib_spec->eth.mask.dst_mac);
1571 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1572 dmac_47_16),
1573 ib_spec->eth.val.dst_mac);
1574
1575 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1576 smac_47_16),
1577 ib_spec->eth.mask.src_mac);
1578 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1579 smac_47_16),
1580 ib_spec->eth.val.src_mac);
1581
1582 if (ib_spec->eth.mask.vlan_tag) {
1583 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1584 vlan_tag, 1);
1585 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1586 vlan_tag, 1);
1587
1588 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1589 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1590 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1591 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1592
1593 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1594 first_cfi,
1595 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1596 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1597 first_cfi,
1598 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1599
1600 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1601 first_prio,
1602 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1603 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1604 first_prio,
1605 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1606 }
1607 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1608 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1609 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1610 ethertype, ntohs(ib_spec->eth.val.ether_type));
1611 break;
1612 case IB_FLOW_SPEC_IPV4:
1613 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1614 return -ENOTSUPP;
1615
1616 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1617 ethertype, 0xffff);
1618 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1619 ethertype, ETH_P_IP);
1620
1621 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1622 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1623 &ib_spec->ipv4.mask.src_ip,
1624 sizeof(ib_spec->ipv4.mask.src_ip));
1625 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1626 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1627 &ib_spec->ipv4.val.src_ip,
1628 sizeof(ib_spec->ipv4.val.src_ip));
1629 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1630 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1631 &ib_spec->ipv4.mask.dst_ip,
1632 sizeof(ib_spec->ipv4.mask.dst_ip));
1633 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1634 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1635 &ib_spec->ipv4.val.dst_ip,
1636 sizeof(ib_spec->ipv4.val.dst_ip));
1637
1638 set_tos(outer_headers_c, outer_headers_v,
1639 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1640
1641 set_proto(outer_headers_c, outer_headers_v,
1642 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1643 break;
1644 case IB_FLOW_SPEC_IPV6:
1645 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1646 return -ENOTSUPP;
1647
1648 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1649 ethertype, 0xffff);
1650 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1651 ethertype, ETH_P_IPV6);
1652
1653 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1654 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1655 &ib_spec->ipv6.mask.src_ip,
1656 sizeof(ib_spec->ipv6.mask.src_ip));
1657 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1658 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1659 &ib_spec->ipv6.val.src_ip,
1660 sizeof(ib_spec->ipv6.val.src_ip));
1661 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1662 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1663 &ib_spec->ipv6.mask.dst_ip,
1664 sizeof(ib_spec->ipv6.mask.dst_ip));
1665 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1666 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1667 &ib_spec->ipv6.val.dst_ip,
1668 sizeof(ib_spec->ipv6.val.dst_ip));
1669
1670 set_tos(outer_headers_c, outer_headers_v,
1671 ib_spec->ipv6.mask.traffic_class,
1672 ib_spec->ipv6.val.traffic_class);
1673
1674 set_proto(outer_headers_c, outer_headers_v,
1675 ib_spec->ipv6.mask.next_hdr,
1676 ib_spec->ipv6.val.next_hdr);
1677
1678 MLX5_SET(fte_match_set_misc, misc_params_c,
1679 outer_ipv6_flow_label,
1680 ntohl(ib_spec->ipv6.mask.flow_label));
1681 MLX5_SET(fte_match_set_misc, misc_params_v,
1682 outer_ipv6_flow_label,
1683 ntohl(ib_spec->ipv6.val.flow_label));
1684 break;
1685 case IB_FLOW_SPEC_TCP:
1686 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1687 LAST_TCP_UDP_FIELD))
1688 return -ENOTSUPP;
1689
1690 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1691 0xff);
1692 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1693 IPPROTO_TCP);
1694
1695 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1696 ntohs(ib_spec->tcp_udp.mask.src_port));
1697 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1698 ntohs(ib_spec->tcp_udp.val.src_port));
1699
1700 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1701 ntohs(ib_spec->tcp_udp.mask.dst_port));
1702 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1703 ntohs(ib_spec->tcp_udp.val.dst_port));
1704 break;
1705 case IB_FLOW_SPEC_UDP:
1706 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1707 LAST_TCP_UDP_FIELD))
1708 return -ENOTSUPP;
1709
1710 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1711 0xff);
1712 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1713 IPPROTO_UDP);
1714
1715 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1716 ntohs(ib_spec->tcp_udp.mask.src_port));
1717 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1718 ntohs(ib_spec->tcp_udp.val.src_port));
1719
1720 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1721 ntohs(ib_spec->tcp_udp.mask.dst_port));
1722 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1723 ntohs(ib_spec->tcp_udp.val.dst_port));
1724 break;
1725 default:
1726 return -EINVAL;
1727 }
1728
1729 return 0;
1730 }
1731
1732 /* If a flow could catch both multicast and unicast packets,
1733 * it won't fall into the multicast flow steering table and this rule
1734 * could steal other multicast packets.
1735 */
flow_is_multicast_only(struct ib_flow_attr * ib_attr)1736 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1737 {
1738 struct ib_flow_spec_eth *eth_spec;
1739
1740 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1741 ib_attr->size < sizeof(struct ib_flow_attr) +
1742 sizeof(struct ib_flow_spec_eth) ||
1743 ib_attr->num_of_specs < 1)
1744 return false;
1745
1746 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1747 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1748 eth_spec->size != sizeof(*eth_spec))
1749 return false;
1750
1751 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1752 is_multicast_ether_addr(eth_spec->val.dst_mac);
1753 }
1754
is_valid_attr(const struct ib_flow_attr * flow_attr)1755 static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
1756 {
1757 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1758 bool has_ipv4_spec = false;
1759 bool eth_type_ipv4 = true;
1760 unsigned int spec_index;
1761
1762 /* Validate that ethertype is correct */
1763 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1764 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1765 ib_spec->eth.mask.ether_type) {
1766 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1767 ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1768 eth_type_ipv4 = false;
1769 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1770 has_ipv4_spec = true;
1771 }
1772 ib_spec = (void *)ib_spec + ib_spec->size;
1773 }
1774 return !has_ipv4_spec || eth_type_ipv4;
1775 }
1776
put_flow_table(struct mlx5_ib_dev * dev,struct mlx5_ib_flow_prio * prio,bool ft_added)1777 static void put_flow_table(struct mlx5_ib_dev *dev,
1778 struct mlx5_ib_flow_prio *prio, bool ft_added)
1779 {
1780 prio->refcount -= !!ft_added;
1781 if (!prio->refcount) {
1782 mlx5_destroy_flow_table(prio->flow_table);
1783 prio->flow_table = NULL;
1784 }
1785 }
1786
mlx5_ib_destroy_flow(struct ib_flow * flow_id)1787 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1788 {
1789 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1790 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1791 struct mlx5_ib_flow_handler,
1792 ibflow);
1793 struct mlx5_ib_flow_handler *iter, *tmp;
1794
1795 mutex_lock(&dev->flow_db.lock);
1796
1797 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1798 mlx5_del_flow_rule(iter->rule);
1799 put_flow_table(dev, iter->prio, true);
1800 list_del(&iter->list);
1801 kfree(iter);
1802 }
1803
1804 mlx5_del_flow_rule(handler->rule);
1805 put_flow_table(dev, handler->prio, true);
1806 mutex_unlock(&dev->flow_db.lock);
1807
1808 kfree(handler);
1809
1810 return 0;
1811 }
1812
ib_prio_to_core_prio(unsigned int priority,bool dont_trap)1813 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1814 {
1815 priority *= 2;
1816 if (!dont_trap)
1817 priority++;
1818 return priority;
1819 }
1820
1821 enum flow_table_type {
1822 MLX5_IB_FT_RX,
1823 MLX5_IB_FT_TX
1824 };
1825
1826 #define MLX5_FS_MAX_TYPES 10
1827 #define MLX5_FS_MAX_ENTRIES 32000UL
get_flow_table(struct mlx5_ib_dev * dev,struct ib_flow_attr * flow_attr,enum flow_table_type ft_type)1828 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1829 struct ib_flow_attr *flow_attr,
1830 enum flow_table_type ft_type)
1831 {
1832 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
1833 struct mlx5_flow_namespace *ns = NULL;
1834 struct mlx5_ib_flow_prio *prio;
1835 struct mlx5_flow_table *ft;
1836 int num_entries;
1837 int num_groups;
1838 int priority;
1839 int err = 0;
1840
1841 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1842 if (flow_is_multicast_only(flow_attr) &&
1843 !dont_trap)
1844 priority = MLX5_IB_FLOW_MCAST_PRIO;
1845 else
1846 priority = ib_prio_to_core_prio(flow_attr->priority,
1847 dont_trap);
1848 ns = mlx5_get_flow_namespace(dev->mdev,
1849 MLX5_FLOW_NAMESPACE_BYPASS);
1850 num_entries = MLX5_FS_MAX_ENTRIES;
1851 num_groups = MLX5_FS_MAX_TYPES;
1852 prio = &dev->flow_db.prios[priority];
1853 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1854 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1855 ns = mlx5_get_flow_namespace(dev->mdev,
1856 MLX5_FLOW_NAMESPACE_LEFTOVERS);
1857 build_leftovers_ft_param(&priority,
1858 &num_entries,
1859 &num_groups);
1860 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1861 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
1862 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
1863 allow_sniffer_and_nic_rx_shared_tir))
1864 return ERR_PTR(-ENOTSUPP);
1865
1866 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
1867 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
1868 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
1869
1870 prio = &dev->flow_db.sniffer[ft_type];
1871 priority = 0;
1872 num_entries = 1;
1873 num_groups = 1;
1874 }
1875
1876 if (!ns)
1877 return ERR_PTR(-ENOTSUPP);
1878
1879 ft = prio->flow_table;
1880 if (!ft) {
1881 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1882 num_entries,
1883 num_groups,
1884 0);
1885
1886 if (!IS_ERR(ft)) {
1887 prio->refcount = 0;
1888 prio->flow_table = ft;
1889 } else {
1890 err = PTR_ERR(ft);
1891 }
1892 }
1893
1894 return err ? ERR_PTR(err) : prio;
1895 }
1896
create_flow_rule(struct mlx5_ib_dev * dev,struct mlx5_ib_flow_prio * ft_prio,const struct ib_flow_attr * flow_attr,struct mlx5_flow_destination * dst)1897 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1898 struct mlx5_ib_flow_prio *ft_prio,
1899 const struct ib_flow_attr *flow_attr,
1900 struct mlx5_flow_destination *dst)
1901 {
1902 struct mlx5_flow_table *ft = ft_prio->flow_table;
1903 struct mlx5_ib_flow_handler *handler;
1904 struct mlx5_flow_spec *spec;
1905 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
1906 unsigned int spec_index;
1907 u32 action;
1908 int err = 0;
1909
1910 if (!is_valid_attr(flow_attr))
1911 return ERR_PTR(-EINVAL);
1912
1913 spec = mlx5_vzalloc(sizeof(*spec));
1914 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1915 if (!handler || !spec) {
1916 err = -ENOMEM;
1917 goto free;
1918 }
1919
1920 INIT_LIST_HEAD(&handler->list);
1921
1922 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1923 err = parse_flow_attr(spec->match_criteria,
1924 spec->match_value, ib_flow);
1925 if (err < 0)
1926 goto free;
1927
1928 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1929 }
1930
1931 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
1932 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1933 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
1934 handler->rule = mlx5_add_flow_rule(ft, spec,
1935 action,
1936 MLX5_FS_DEFAULT_FLOW_TAG,
1937 dst);
1938
1939 if (IS_ERR(handler->rule)) {
1940 err = PTR_ERR(handler->rule);
1941 goto free;
1942 }
1943
1944 ft_prio->refcount++;
1945 handler->prio = ft_prio;
1946
1947 ft_prio->flow_table = ft;
1948 free:
1949 if (err)
1950 kfree(handler);
1951 kvfree(spec);
1952 return err ? ERR_PTR(err) : handler;
1953 }
1954
create_dont_trap_rule(struct mlx5_ib_dev * dev,struct mlx5_ib_flow_prio * ft_prio,struct ib_flow_attr * flow_attr,struct mlx5_flow_destination * dst)1955 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1956 struct mlx5_ib_flow_prio *ft_prio,
1957 struct ib_flow_attr *flow_attr,
1958 struct mlx5_flow_destination *dst)
1959 {
1960 struct mlx5_ib_flow_handler *handler_dst = NULL;
1961 struct mlx5_ib_flow_handler *handler = NULL;
1962
1963 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1964 if (!IS_ERR(handler)) {
1965 handler_dst = create_flow_rule(dev, ft_prio,
1966 flow_attr, dst);
1967 if (IS_ERR(handler_dst)) {
1968 mlx5_del_flow_rule(handler->rule);
1969 ft_prio->refcount--;
1970 kfree(handler);
1971 handler = handler_dst;
1972 } else {
1973 list_add(&handler_dst->list, &handler->list);
1974 }
1975 }
1976
1977 return handler;
1978 }
1979 enum {
1980 LEFTOVERS_MC,
1981 LEFTOVERS_UC,
1982 };
1983
create_leftovers_rule(struct mlx5_ib_dev * dev,struct mlx5_ib_flow_prio * ft_prio,struct ib_flow_attr * flow_attr,struct mlx5_flow_destination * dst)1984 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1985 struct mlx5_ib_flow_prio *ft_prio,
1986 struct ib_flow_attr *flow_attr,
1987 struct mlx5_flow_destination *dst)
1988 {
1989 struct mlx5_ib_flow_handler *handler_ucast = NULL;
1990 struct mlx5_ib_flow_handler *handler = NULL;
1991
1992 static struct {
1993 struct ib_flow_attr flow_attr;
1994 struct ib_flow_spec_eth eth_flow;
1995 } leftovers_specs[] = {
1996 [LEFTOVERS_MC] = {
1997 .flow_attr = {
1998 .num_of_specs = 1,
1999 .size = sizeof(leftovers_specs[0])
2000 },
2001 .eth_flow = {
2002 .type = IB_FLOW_SPEC_ETH,
2003 .size = sizeof(struct ib_flow_spec_eth),
2004 .mask = {.dst_mac = {0x1} },
2005 .val = {.dst_mac = {0x1} }
2006 }
2007 },
2008 [LEFTOVERS_UC] = {
2009 .flow_attr = {
2010 .num_of_specs = 1,
2011 .size = sizeof(leftovers_specs[0])
2012 },
2013 .eth_flow = {
2014 .type = IB_FLOW_SPEC_ETH,
2015 .size = sizeof(struct ib_flow_spec_eth),
2016 .mask = {.dst_mac = {0x1} },
2017 .val = {.dst_mac = {} }
2018 }
2019 }
2020 };
2021
2022 handler = create_flow_rule(dev, ft_prio,
2023 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2024 dst);
2025 if (!IS_ERR(handler) &&
2026 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2027 handler_ucast = create_flow_rule(dev, ft_prio,
2028 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2029 dst);
2030 if (IS_ERR(handler_ucast)) {
2031 mlx5_del_flow_rule(handler->rule);
2032 ft_prio->refcount--;
2033 kfree(handler);
2034 handler = handler_ucast;
2035 } else {
2036 list_add(&handler_ucast->list, &handler->list);
2037 }
2038 }
2039
2040 return handler;
2041 }
2042
create_sniffer_rule(struct mlx5_ib_dev * dev,struct mlx5_ib_flow_prio * ft_rx,struct mlx5_ib_flow_prio * ft_tx,struct mlx5_flow_destination * dst)2043 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2044 struct mlx5_ib_flow_prio *ft_rx,
2045 struct mlx5_ib_flow_prio *ft_tx,
2046 struct mlx5_flow_destination *dst)
2047 {
2048 struct mlx5_ib_flow_handler *handler_rx;
2049 struct mlx5_ib_flow_handler *handler_tx;
2050 int err;
2051 static const struct ib_flow_attr flow_attr = {
2052 .num_of_specs = 0,
2053 .size = sizeof(flow_attr)
2054 };
2055
2056 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2057 if (IS_ERR(handler_rx)) {
2058 err = PTR_ERR(handler_rx);
2059 goto err;
2060 }
2061
2062 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2063 if (IS_ERR(handler_tx)) {
2064 err = PTR_ERR(handler_tx);
2065 goto err_tx;
2066 }
2067
2068 list_add(&handler_tx->list, &handler_rx->list);
2069
2070 return handler_rx;
2071
2072 err_tx:
2073 mlx5_del_flow_rule(handler_rx->rule);
2074 ft_rx->refcount--;
2075 kfree(handler_rx);
2076 err:
2077 return ERR_PTR(err);
2078 }
2079
mlx5_ib_create_flow(struct ib_qp * qp,struct ib_flow_attr * flow_attr,int domain)2080 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2081 struct ib_flow_attr *flow_attr,
2082 int domain)
2083 {
2084 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2085 struct mlx5_ib_qp *mqp = to_mqp(qp);
2086 struct mlx5_ib_flow_handler *handler = NULL;
2087 struct mlx5_flow_destination *dst = NULL;
2088 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2089 struct mlx5_ib_flow_prio *ft_prio;
2090 int err;
2091
2092 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2093 return ERR_PTR(-ENOSPC);
2094
2095 if (domain != IB_FLOW_DOMAIN_USER ||
2096 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2097 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2098 return ERR_PTR(-EINVAL);
2099
2100 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2101 if (!dst)
2102 return ERR_PTR(-ENOMEM);
2103
2104 mutex_lock(&dev->flow_db.lock);
2105
2106 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2107 if (IS_ERR(ft_prio)) {
2108 err = PTR_ERR(ft_prio);
2109 goto unlock;
2110 }
2111 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2112 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2113 if (IS_ERR(ft_prio_tx)) {
2114 err = PTR_ERR(ft_prio_tx);
2115 ft_prio_tx = NULL;
2116 goto destroy_ft;
2117 }
2118 }
2119
2120 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2121 if (mqp->flags & MLX5_IB_QP_RSS)
2122 dst->tir_num = mqp->rss_qp.tirn;
2123 else
2124 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2125
2126 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2127 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2128 handler = create_dont_trap_rule(dev, ft_prio,
2129 flow_attr, dst);
2130 } else {
2131 handler = create_flow_rule(dev, ft_prio, flow_attr,
2132 dst);
2133 }
2134 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2135 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2136 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2137 dst);
2138 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2139 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2140 } else {
2141 err = -EINVAL;
2142 goto destroy_ft;
2143 }
2144
2145 if (IS_ERR(handler)) {
2146 err = PTR_ERR(handler);
2147 handler = NULL;
2148 goto destroy_ft;
2149 }
2150
2151 mutex_unlock(&dev->flow_db.lock);
2152 kfree(dst);
2153
2154 return &handler->ibflow;
2155
2156 destroy_ft:
2157 put_flow_table(dev, ft_prio, false);
2158 if (ft_prio_tx)
2159 put_flow_table(dev, ft_prio_tx, false);
2160 unlock:
2161 mutex_unlock(&dev->flow_db.lock);
2162 kfree(dst);
2163 kfree(handler);
2164 return ERR_PTR(err);
2165 }
2166
mlx5_ib_mcg_attach(struct ib_qp * ibqp,union ib_gid * gid,u16 lid)2167 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2168 {
2169 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2170 int err;
2171
2172 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2173 if (err)
2174 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2175 ibqp->qp_num, gid->raw);
2176
2177 return err;
2178 }
2179
mlx5_ib_mcg_detach(struct ib_qp * ibqp,union ib_gid * gid,u16 lid)2180 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2181 {
2182 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2183 int err;
2184
2185 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2186 if (err)
2187 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2188 ibqp->qp_num, gid->raw);
2189
2190 return err;
2191 }
2192
init_node_data(struct mlx5_ib_dev * dev)2193 static int init_node_data(struct mlx5_ib_dev *dev)
2194 {
2195 int err;
2196
2197 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2198 if (err)
2199 return err;
2200
2201 dev->mdev->rev_id = dev->mdev->pdev->revision;
2202
2203 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2204 }
2205
show_fw_pages(struct device * device,struct device_attribute * attr,char * buf)2206 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2207 char *buf)
2208 {
2209 struct mlx5_ib_dev *dev =
2210 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2211
2212 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2213 }
2214
show_reg_pages(struct device * device,struct device_attribute * attr,char * buf)2215 static ssize_t show_reg_pages(struct device *device,
2216 struct device_attribute *attr, char *buf)
2217 {
2218 struct mlx5_ib_dev *dev =
2219 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2220
2221 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2222 }
2223
show_hca(struct device * device,struct device_attribute * attr,char * buf)2224 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2225 char *buf)
2226 {
2227 struct mlx5_ib_dev *dev =
2228 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2229 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2230 }
2231
show_rev(struct device * device,struct device_attribute * attr,char * buf)2232 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2233 char *buf)
2234 {
2235 struct mlx5_ib_dev *dev =
2236 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2237 return sprintf(buf, "%x\n", dev->mdev->rev_id);
2238 }
2239
show_board(struct device * device,struct device_attribute * attr,char * buf)2240 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2241 char *buf)
2242 {
2243 struct mlx5_ib_dev *dev =
2244 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2245 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2246 dev->mdev->board_id);
2247 }
2248
2249 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
2250 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2251 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2252 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2253 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2254
2255 static struct device_attribute *mlx5_class_attributes[] = {
2256 &dev_attr_hw_rev,
2257 &dev_attr_hca_type,
2258 &dev_attr_board_id,
2259 &dev_attr_fw_pages,
2260 &dev_attr_reg_pages,
2261 };
2262
pkey_change_handler(struct work_struct * work)2263 static void pkey_change_handler(struct work_struct *work)
2264 {
2265 struct mlx5_ib_port_resources *ports =
2266 container_of(work, struct mlx5_ib_port_resources,
2267 pkey_change_work);
2268
2269 mutex_lock(&ports->devr->mutex);
2270 mlx5_ib_gsi_pkey_change(ports->gsi);
2271 mutex_unlock(&ports->devr->mutex);
2272 }
2273
mlx5_ib_handle_internal_error(struct mlx5_ib_dev * ibdev)2274 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2275 {
2276 struct mlx5_ib_qp *mqp;
2277 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2278 struct mlx5_core_cq *mcq;
2279 struct list_head cq_armed_list;
2280 unsigned long flags_qp;
2281 unsigned long flags_cq;
2282 unsigned long flags;
2283
2284 INIT_LIST_HEAD(&cq_armed_list);
2285
2286 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2287 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2288 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2289 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2290 if (mqp->sq.tail != mqp->sq.head) {
2291 send_mcq = to_mcq(mqp->ibqp.send_cq);
2292 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2293 if (send_mcq->mcq.comp &&
2294 mqp->ibqp.send_cq->comp_handler) {
2295 if (!send_mcq->mcq.reset_notify_added) {
2296 send_mcq->mcq.reset_notify_added = 1;
2297 list_add_tail(&send_mcq->mcq.reset_notify,
2298 &cq_armed_list);
2299 }
2300 }
2301 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2302 }
2303 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2304 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2305 /* no handling is needed for SRQ */
2306 if (!mqp->ibqp.srq) {
2307 if (mqp->rq.tail != mqp->rq.head) {
2308 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2309 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2310 if (recv_mcq->mcq.comp &&
2311 mqp->ibqp.recv_cq->comp_handler) {
2312 if (!recv_mcq->mcq.reset_notify_added) {
2313 recv_mcq->mcq.reset_notify_added = 1;
2314 list_add_tail(&recv_mcq->mcq.reset_notify,
2315 &cq_armed_list);
2316 }
2317 }
2318 spin_unlock_irqrestore(&recv_mcq->lock,
2319 flags_cq);
2320 }
2321 }
2322 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2323 }
2324 /*At that point all inflight post send were put to be executed as of we
2325 * lock/unlock above locks Now need to arm all involved CQs.
2326 */
2327 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2328 mcq->comp(mcq);
2329 }
2330 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2331 }
2332
mlx5_ib_event(struct mlx5_core_dev * dev,void * context,enum mlx5_dev_event event,unsigned long param)2333 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2334 enum mlx5_dev_event event, unsigned long param)
2335 {
2336 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2337 struct ib_event ibev;
2338 bool fatal = false;
2339 u8 port = 0;
2340
2341 switch (event) {
2342 case MLX5_DEV_EVENT_SYS_ERROR:
2343 ibev.event = IB_EVENT_DEVICE_FATAL;
2344 mlx5_ib_handle_internal_error(ibdev);
2345 fatal = true;
2346 break;
2347
2348 case MLX5_DEV_EVENT_PORT_UP:
2349 case MLX5_DEV_EVENT_PORT_DOWN:
2350 case MLX5_DEV_EVENT_PORT_INITIALIZED:
2351 port = (u8)param;
2352
2353 /* In RoCE, port up/down events are handled in
2354 * mlx5_netdev_event().
2355 */
2356 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2357 IB_LINK_LAYER_ETHERNET)
2358 return;
2359
2360 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2361 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2362 break;
2363
2364 case MLX5_DEV_EVENT_LID_CHANGE:
2365 ibev.event = IB_EVENT_LID_CHANGE;
2366 port = (u8)param;
2367 break;
2368
2369 case MLX5_DEV_EVENT_PKEY_CHANGE:
2370 ibev.event = IB_EVENT_PKEY_CHANGE;
2371 port = (u8)param;
2372
2373 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2374 break;
2375
2376 case MLX5_DEV_EVENT_GUID_CHANGE:
2377 ibev.event = IB_EVENT_GID_CHANGE;
2378 port = (u8)param;
2379 break;
2380
2381 case MLX5_DEV_EVENT_CLIENT_REREG:
2382 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2383 port = (u8)param;
2384 break;
2385 }
2386
2387 ibev.device = &ibdev->ib_dev;
2388 ibev.element.port_num = port;
2389
2390 if (port < 1 || port > ibdev->num_ports) {
2391 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2392 return;
2393 }
2394
2395 if (ibdev->ib_active)
2396 ib_dispatch_event(&ibev);
2397
2398 if (fatal)
2399 ibdev->ib_active = false;
2400 }
2401
get_ext_port_caps(struct mlx5_ib_dev * dev)2402 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2403 {
2404 int port;
2405
2406 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2407 mlx5_query_ext_port_caps(dev, port);
2408 }
2409
get_port_caps(struct mlx5_ib_dev * dev)2410 static int get_port_caps(struct mlx5_ib_dev *dev)
2411 {
2412 struct ib_device_attr *dprops = NULL;
2413 struct ib_port_attr *pprops = NULL;
2414 int err = -ENOMEM;
2415 int port;
2416 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2417
2418 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2419 if (!pprops)
2420 goto out;
2421
2422 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2423 if (!dprops)
2424 goto out;
2425
2426 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2427 if (err) {
2428 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2429 goto out;
2430 }
2431
2432 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2433 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2434 if (err) {
2435 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2436 port, err);
2437 break;
2438 }
2439 dev->mdev->port_caps[port - 1].pkey_table_len =
2440 dprops->max_pkeys;
2441 dev->mdev->port_caps[port - 1].gid_table_len =
2442 pprops->gid_tbl_len;
2443 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2444 dprops->max_pkeys, pprops->gid_tbl_len);
2445 }
2446
2447 out:
2448 kfree(pprops);
2449 kfree(dprops);
2450
2451 return err;
2452 }
2453
destroy_umrc_res(struct mlx5_ib_dev * dev)2454 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2455 {
2456 int err;
2457
2458 err = mlx5_mr_cache_cleanup(dev);
2459 if (err)
2460 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2461
2462 mlx5_ib_destroy_qp(dev->umrc.qp);
2463 ib_free_cq(dev->umrc.cq);
2464 ib_dealloc_pd(dev->umrc.pd);
2465 }
2466
2467 enum {
2468 MAX_UMR_WR = 128,
2469 };
2470
create_umr_res(struct mlx5_ib_dev * dev)2471 static int create_umr_res(struct mlx5_ib_dev *dev)
2472 {
2473 struct ib_qp_init_attr *init_attr = NULL;
2474 struct ib_qp_attr *attr = NULL;
2475 struct ib_pd *pd;
2476 struct ib_cq *cq;
2477 struct ib_qp *qp;
2478 int ret;
2479
2480 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2481 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2482 if (!attr || !init_attr) {
2483 ret = -ENOMEM;
2484 goto error_0;
2485 }
2486
2487 pd = ib_alloc_pd(&dev->ib_dev, 0);
2488 if (IS_ERR(pd)) {
2489 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2490 ret = PTR_ERR(pd);
2491 goto error_0;
2492 }
2493
2494 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2495 if (IS_ERR(cq)) {
2496 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2497 ret = PTR_ERR(cq);
2498 goto error_2;
2499 }
2500
2501 init_attr->send_cq = cq;
2502 init_attr->recv_cq = cq;
2503 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2504 init_attr->cap.max_send_wr = MAX_UMR_WR;
2505 init_attr->cap.max_send_sge = 1;
2506 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2507 init_attr->port_num = 1;
2508 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2509 if (IS_ERR(qp)) {
2510 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2511 ret = PTR_ERR(qp);
2512 goto error_3;
2513 }
2514 qp->device = &dev->ib_dev;
2515 qp->real_qp = qp;
2516 qp->uobject = NULL;
2517 qp->qp_type = MLX5_IB_QPT_REG_UMR;
2518 qp->send_cq = init_attr->send_cq;
2519 qp->recv_cq = init_attr->recv_cq;
2520
2521 attr->qp_state = IB_QPS_INIT;
2522 attr->port_num = 1;
2523 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2524 IB_QP_PORT, NULL);
2525 if (ret) {
2526 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2527 goto error_4;
2528 }
2529
2530 memset(attr, 0, sizeof(*attr));
2531 attr->qp_state = IB_QPS_RTR;
2532 attr->path_mtu = IB_MTU_256;
2533
2534 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2535 if (ret) {
2536 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2537 goto error_4;
2538 }
2539
2540 memset(attr, 0, sizeof(*attr));
2541 attr->qp_state = IB_QPS_RTS;
2542 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2543 if (ret) {
2544 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2545 goto error_4;
2546 }
2547
2548 dev->umrc.qp = qp;
2549 dev->umrc.cq = cq;
2550 dev->umrc.pd = pd;
2551
2552 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2553 ret = mlx5_mr_cache_init(dev);
2554 if (ret) {
2555 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2556 goto error_4;
2557 }
2558
2559 kfree(attr);
2560 kfree(init_attr);
2561
2562 return 0;
2563
2564 error_4:
2565 mlx5_ib_destroy_qp(qp);
2566
2567 error_3:
2568 ib_free_cq(cq);
2569
2570 error_2:
2571 ib_dealloc_pd(pd);
2572
2573 error_0:
2574 kfree(attr);
2575 kfree(init_attr);
2576 return ret;
2577 }
2578
mlx5_get_umr_fence(u8 umr_fence_cap)2579 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
2580 {
2581 switch (umr_fence_cap) {
2582 case MLX5_CAP_UMR_FENCE_NONE:
2583 return MLX5_FENCE_MODE_NONE;
2584 case MLX5_CAP_UMR_FENCE_SMALL:
2585 return MLX5_FENCE_MODE_INITIATOR_SMALL;
2586 default:
2587 return MLX5_FENCE_MODE_STRONG_ORDERING;
2588 }
2589 }
2590
create_dev_resources(struct mlx5_ib_resources * devr)2591 static int create_dev_resources(struct mlx5_ib_resources *devr)
2592 {
2593 struct ib_srq_init_attr attr;
2594 struct mlx5_ib_dev *dev;
2595 struct ib_cq_init_attr cq_attr = {.cqe = 1};
2596 int port;
2597 int ret = 0;
2598
2599 dev = container_of(devr, struct mlx5_ib_dev, devr);
2600
2601 mutex_init(&devr->mutex);
2602
2603 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2604 if (IS_ERR(devr->p0)) {
2605 ret = PTR_ERR(devr->p0);
2606 goto error0;
2607 }
2608 devr->p0->device = &dev->ib_dev;
2609 devr->p0->uobject = NULL;
2610 atomic_set(&devr->p0->usecnt, 0);
2611
2612 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2613 if (IS_ERR(devr->c0)) {
2614 ret = PTR_ERR(devr->c0);
2615 goto error1;
2616 }
2617 devr->c0->device = &dev->ib_dev;
2618 devr->c0->uobject = NULL;
2619 devr->c0->comp_handler = NULL;
2620 devr->c0->event_handler = NULL;
2621 devr->c0->cq_context = NULL;
2622 atomic_set(&devr->c0->usecnt, 0);
2623
2624 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2625 if (IS_ERR(devr->x0)) {
2626 ret = PTR_ERR(devr->x0);
2627 goto error2;
2628 }
2629 devr->x0->device = &dev->ib_dev;
2630 devr->x0->inode = NULL;
2631 atomic_set(&devr->x0->usecnt, 0);
2632 mutex_init(&devr->x0->tgt_qp_mutex);
2633 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2634
2635 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2636 if (IS_ERR(devr->x1)) {
2637 ret = PTR_ERR(devr->x1);
2638 goto error3;
2639 }
2640 devr->x1->device = &dev->ib_dev;
2641 devr->x1->inode = NULL;
2642 atomic_set(&devr->x1->usecnt, 0);
2643 mutex_init(&devr->x1->tgt_qp_mutex);
2644 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2645
2646 memset(&attr, 0, sizeof(attr));
2647 attr.attr.max_sge = 1;
2648 attr.attr.max_wr = 1;
2649 attr.srq_type = IB_SRQT_XRC;
2650 attr.ext.xrc.cq = devr->c0;
2651 attr.ext.xrc.xrcd = devr->x0;
2652
2653 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2654 if (IS_ERR(devr->s0)) {
2655 ret = PTR_ERR(devr->s0);
2656 goto error4;
2657 }
2658 devr->s0->device = &dev->ib_dev;
2659 devr->s0->pd = devr->p0;
2660 devr->s0->uobject = NULL;
2661 devr->s0->event_handler = NULL;
2662 devr->s0->srq_context = NULL;
2663 devr->s0->srq_type = IB_SRQT_XRC;
2664 devr->s0->ext.xrc.xrcd = devr->x0;
2665 devr->s0->ext.xrc.cq = devr->c0;
2666 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2667 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2668 atomic_inc(&devr->p0->usecnt);
2669 atomic_set(&devr->s0->usecnt, 0);
2670
2671 memset(&attr, 0, sizeof(attr));
2672 attr.attr.max_sge = 1;
2673 attr.attr.max_wr = 1;
2674 attr.srq_type = IB_SRQT_BASIC;
2675 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2676 if (IS_ERR(devr->s1)) {
2677 ret = PTR_ERR(devr->s1);
2678 goto error5;
2679 }
2680 devr->s1->device = &dev->ib_dev;
2681 devr->s1->pd = devr->p0;
2682 devr->s1->uobject = NULL;
2683 devr->s1->event_handler = NULL;
2684 devr->s1->srq_context = NULL;
2685 devr->s1->srq_type = IB_SRQT_BASIC;
2686 devr->s1->ext.xrc.cq = devr->c0;
2687 atomic_inc(&devr->p0->usecnt);
2688 atomic_set(&devr->s0->usecnt, 0);
2689
2690 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2691 INIT_WORK(&devr->ports[port].pkey_change_work,
2692 pkey_change_handler);
2693 devr->ports[port].devr = devr;
2694 }
2695
2696 return 0;
2697
2698 error5:
2699 mlx5_ib_destroy_srq(devr->s0);
2700 error4:
2701 mlx5_ib_dealloc_xrcd(devr->x1);
2702 error3:
2703 mlx5_ib_dealloc_xrcd(devr->x0);
2704 error2:
2705 mlx5_ib_destroy_cq(devr->c0);
2706 error1:
2707 mlx5_ib_dealloc_pd(devr->p0);
2708 error0:
2709 return ret;
2710 }
2711
destroy_dev_resources(struct mlx5_ib_resources * devr)2712 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2713 {
2714 struct mlx5_ib_dev *dev =
2715 container_of(devr, struct mlx5_ib_dev, devr);
2716 int port;
2717
2718 mlx5_ib_destroy_srq(devr->s1);
2719 mlx5_ib_destroy_srq(devr->s0);
2720 mlx5_ib_dealloc_xrcd(devr->x0);
2721 mlx5_ib_dealloc_xrcd(devr->x1);
2722 mlx5_ib_destroy_cq(devr->c0);
2723 mlx5_ib_dealloc_pd(devr->p0);
2724
2725 /* Make sure no change P_Key work items are still executing */
2726 for (port = 0; port < dev->num_ports; ++port)
2727 cancel_work_sync(&devr->ports[port].pkey_change_work);
2728 }
2729
get_core_cap_flags(struct ib_device * ibdev)2730 static u32 get_core_cap_flags(struct ib_device *ibdev)
2731 {
2732 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2733 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2734 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2735 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2736 u32 ret = 0;
2737
2738 if (ll == IB_LINK_LAYER_INFINIBAND)
2739 return RDMA_CORE_PORT_IBA_IB;
2740
2741 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2742 return 0;
2743
2744 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2745 return 0;
2746
2747 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2748 ret |= RDMA_CORE_PORT_IBA_ROCE;
2749
2750 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2751 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2752
2753 return ret;
2754 }
2755
mlx5_port_immutable(struct ib_device * ibdev,u8 port_num,struct ib_port_immutable * immutable)2756 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2757 struct ib_port_immutable *immutable)
2758 {
2759 struct ib_port_attr attr;
2760 int err;
2761
2762 err = mlx5_ib_query_port(ibdev, port_num, &attr);
2763 if (err)
2764 return err;
2765
2766 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2767 immutable->gid_tbl_len = attr.gid_tbl_len;
2768 immutable->core_cap_flags = get_core_cap_flags(ibdev);
2769 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2770
2771 return 0;
2772 }
2773
get_dev_fw_str(struct ib_device * ibdev,char * str,size_t str_len)2774 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2775 size_t str_len)
2776 {
2777 struct mlx5_ib_dev *dev =
2778 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2779 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2780 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2781 }
2782
mlx5_roce_lag_init(struct mlx5_ib_dev * dev)2783 static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev)
2784 {
2785 struct mlx5_core_dev *mdev = dev->mdev;
2786 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
2787 MLX5_FLOW_NAMESPACE_LAG);
2788 struct mlx5_flow_table *ft;
2789 int err;
2790
2791 if (!ns || !mlx5_lag_is_active(mdev))
2792 return 0;
2793
2794 err = mlx5_cmd_create_vport_lag(mdev);
2795 if (err)
2796 return err;
2797
2798 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
2799 if (IS_ERR(ft)) {
2800 err = PTR_ERR(ft);
2801 goto err_destroy_vport_lag;
2802 }
2803
2804 dev->flow_db.lag_demux_ft = ft;
2805 return 0;
2806
2807 err_destroy_vport_lag:
2808 mlx5_cmd_destroy_vport_lag(mdev);
2809 return err;
2810 }
2811
mlx5_roce_lag_cleanup(struct mlx5_ib_dev * dev)2812 static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev)
2813 {
2814 struct mlx5_core_dev *mdev = dev->mdev;
2815
2816 if (dev->flow_db.lag_demux_ft) {
2817 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
2818 dev->flow_db.lag_demux_ft = NULL;
2819
2820 mlx5_cmd_destroy_vport_lag(mdev);
2821 }
2822 }
2823
mlx5_remove_roce_notifier(struct mlx5_ib_dev * dev)2824 static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev)
2825 {
2826 if (dev->roce.nb.notifier_call) {
2827 unregister_netdevice_notifier(&dev->roce.nb);
2828 dev->roce.nb.notifier_call = NULL;
2829 }
2830 }
2831
mlx5_enable_roce(struct mlx5_ib_dev * dev)2832 static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2833 {
2834 int err;
2835
2836 dev->roce.nb.notifier_call = mlx5_netdev_event;
2837 err = register_netdevice_notifier(&dev->roce.nb);
2838 if (err) {
2839 dev->roce.nb.notifier_call = NULL;
2840 return err;
2841 }
2842
2843 err = mlx5_nic_vport_enable_roce(dev->mdev);
2844 if (err)
2845 goto err_unregister_netdevice_notifier;
2846
2847 err = mlx5_roce_lag_init(dev);
2848 if (err)
2849 goto err_disable_roce;
2850
2851 return 0;
2852
2853 err_disable_roce:
2854 mlx5_nic_vport_disable_roce(dev->mdev);
2855
2856 err_unregister_netdevice_notifier:
2857 mlx5_remove_roce_notifier(dev);
2858 return err;
2859 }
2860
mlx5_disable_roce(struct mlx5_ib_dev * dev)2861 static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2862 {
2863 mlx5_roce_lag_cleanup(dev);
2864 mlx5_nic_vport_disable_roce(dev->mdev);
2865 }
2866
mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev * dev)2867 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2868 {
2869 unsigned int i;
2870
2871 for (i = 0; i < dev->num_ports; i++)
2872 mlx5_core_dealloc_q_counter(dev->mdev,
2873 dev->port[i].q_cnt_id);
2874 }
2875
mlx5_ib_alloc_q_counters(struct mlx5_ib_dev * dev)2876 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2877 {
2878 int i;
2879 int ret;
2880
2881 for (i = 0; i < dev->num_ports; i++) {
2882 ret = mlx5_core_alloc_q_counter(dev->mdev,
2883 &dev->port[i].q_cnt_id);
2884 if (ret) {
2885 mlx5_ib_warn(dev,
2886 "couldn't allocate queue counter for port %d, err %d\n",
2887 i + 1, ret);
2888 goto dealloc_counters;
2889 }
2890 }
2891
2892 return 0;
2893
2894 dealloc_counters:
2895 while (--i >= 0)
2896 mlx5_core_dealloc_q_counter(dev->mdev,
2897 dev->port[i].q_cnt_id);
2898
2899 return ret;
2900 }
2901
2902 static const char * const names[] = {
2903 "rx_write_requests",
2904 "rx_read_requests",
2905 "rx_atomic_requests",
2906 "out_of_buffer",
2907 "out_of_sequence",
2908 "duplicate_request",
2909 "rnr_nak_retry_err",
2910 "packet_seq_err",
2911 "implied_nak_seq_err",
2912 "local_ack_timeout_err",
2913 };
2914
2915 static const size_t stats_offsets[] = {
2916 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
2917 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
2918 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
2919 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
2920 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
2921 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
2922 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
2923 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
2924 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
2925 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
2926 };
2927
mlx5_ib_alloc_hw_stats(struct ib_device * ibdev,u8 port_num)2928 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
2929 u8 port_num)
2930 {
2931 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
2932
2933 /* We support only per port stats */
2934 if (port_num == 0)
2935 return NULL;
2936
2937 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
2938 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2939 }
2940
mlx5_ib_get_hw_stats(struct ib_device * ibdev,struct rdma_hw_stats * stats,u8 port,int index)2941 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
2942 struct rdma_hw_stats *stats,
2943 u8 port, int index)
2944 {
2945 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2946 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
2947 void *out;
2948 __be32 val;
2949 int ret;
2950 int i;
2951
2952 if (!port || !stats)
2953 return -ENOSYS;
2954
2955 out = mlx5_vzalloc(outlen);
2956 if (!out)
2957 return -ENOMEM;
2958
2959 ret = mlx5_core_query_q_counter(dev->mdev,
2960 dev->port[port - 1].q_cnt_id, 0,
2961 out, outlen);
2962 if (ret)
2963 goto free;
2964
2965 for (i = 0; i < ARRAY_SIZE(names); i++) {
2966 val = *(__be32 *)(out + stats_offsets[i]);
2967 stats->value[i] = (u64)be32_to_cpu(val);
2968 }
2969 free:
2970 kvfree(out);
2971 return ARRAY_SIZE(names);
2972 }
2973
mlx5_ib_add(struct mlx5_core_dev * mdev)2974 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
2975 {
2976 struct mlx5_ib_dev *dev;
2977 enum rdma_link_layer ll;
2978 int port_type_cap;
2979 const char *name;
2980 int err;
2981 int i;
2982
2983 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2984 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2985
2986 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
2987 return NULL;
2988
2989 printk_once(KERN_INFO "%s", mlx5_version);
2990
2991 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2992 if (!dev)
2993 return NULL;
2994
2995 dev->mdev = mdev;
2996
2997 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
2998 GFP_KERNEL);
2999 if (!dev->port)
3000 goto err_dealloc;
3001
3002 rwlock_init(&dev->roce.netdev_lock);
3003 err = get_port_caps(dev);
3004 if (err)
3005 goto err_free_port;
3006
3007 if (mlx5_use_mad_ifc(dev))
3008 get_ext_port_caps(dev);
3009
3010 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
3011
3012 if (!mlx5_lag_is_active(mdev))
3013 name = "mlx5_%d";
3014 else
3015 name = "mlx5_bond_%d";
3016
3017 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
3018 dev->ib_dev.owner = THIS_MODULE;
3019 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
3020 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
3021 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
3022 dev->ib_dev.phys_port_cnt = dev->num_ports;
3023 dev->ib_dev.num_comp_vectors =
3024 dev->mdev->priv.eq_table.num_comp_vectors;
3025 dev->ib_dev.dma_device = &mdev->pdev->dev;
3026
3027 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
3028 dev->ib_dev.uverbs_cmd_mask =
3029 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
3030 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
3031 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
3032 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
3033 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
3034 (1ull << IB_USER_VERBS_CMD_REG_MR) |
3035 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
3036 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
3037 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3038 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
3039 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
3040 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
3041 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
3042 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
3043 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
3044 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
3045 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
3046 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
3047 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
3048 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
3049 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
3050 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
3051 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
3052 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
3053 dev->ib_dev.uverbs_ex_cmd_mask =
3054 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
3055 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
3056 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
3057
3058 dev->ib_dev.query_device = mlx5_ib_query_device;
3059 dev->ib_dev.query_port = mlx5_ib_query_port;
3060 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
3061 if (ll == IB_LINK_LAYER_ETHERNET)
3062 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
3063 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3064 dev->ib_dev.add_gid = mlx5_ib_add_gid;
3065 dev->ib_dev.del_gid = mlx5_ib_del_gid;
3066 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
3067 dev->ib_dev.modify_device = mlx5_ib_modify_device;
3068 dev->ib_dev.modify_port = mlx5_ib_modify_port;
3069 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
3070 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
3071 dev->ib_dev.mmap = mlx5_ib_mmap;
3072 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
3073 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
3074 dev->ib_dev.create_ah = mlx5_ib_create_ah;
3075 dev->ib_dev.query_ah = mlx5_ib_query_ah;
3076 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
3077 dev->ib_dev.create_srq = mlx5_ib_create_srq;
3078 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
3079 dev->ib_dev.query_srq = mlx5_ib_query_srq;
3080 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
3081 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
3082 dev->ib_dev.create_qp = mlx5_ib_create_qp;
3083 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
3084 dev->ib_dev.query_qp = mlx5_ib_query_qp;
3085 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
3086 dev->ib_dev.post_send = mlx5_ib_post_send;
3087 dev->ib_dev.post_recv = mlx5_ib_post_recv;
3088 dev->ib_dev.create_cq = mlx5_ib_create_cq;
3089 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
3090 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
3091 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
3092 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
3093 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
3094 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
3095 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
3096 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
3097 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
3098 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
3099 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
3100 dev->ib_dev.process_mad = mlx5_ib_process_mad;
3101 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
3102 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
3103 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
3104 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
3105 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
3106 if (mlx5_core_is_pf(mdev)) {
3107 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
3108 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
3109 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
3110 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
3111 }
3112
3113 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3114
3115 mlx5_ib_internal_fill_odp_caps(dev);
3116
3117 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
3118
3119 if (MLX5_CAP_GEN(mdev, imaicl)) {
3120 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
3121 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
3122 dev->ib_dev.uverbs_cmd_mask |=
3123 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
3124 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3125 }
3126
3127 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
3128 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3129 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
3130 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
3131 }
3132
3133 if (MLX5_CAP_GEN(mdev, xrc)) {
3134 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3135 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3136 dev->ib_dev.uverbs_cmd_mask |=
3137 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3138 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3139 }
3140
3141 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3142 IB_LINK_LAYER_ETHERNET) {
3143 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3144 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3145 dev->ib_dev.create_wq = mlx5_ib_create_wq;
3146 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
3147 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
3148 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3149 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3150 dev->ib_dev.uverbs_ex_cmd_mask |=
3151 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3152 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3153 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3154 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3155 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3156 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3157 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3158 }
3159 err = init_node_data(dev);
3160 if (err)
3161 goto err_free_port;
3162
3163 mutex_init(&dev->flow_db.lock);
3164 mutex_init(&dev->cap_mask_mutex);
3165 INIT_LIST_HEAD(&dev->qp_list);
3166 spin_lock_init(&dev->reset_flow_resource_lock);
3167
3168 if (ll == IB_LINK_LAYER_ETHERNET) {
3169 err = mlx5_enable_roce(dev);
3170 if (err)
3171 goto err_free_port;
3172 }
3173
3174 err = create_dev_resources(&dev->devr);
3175 if (err)
3176 goto err_disable_roce;
3177
3178 err = mlx5_ib_odp_init_one(dev);
3179 if (err)
3180 goto err_rsrc;
3181
3182 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
3183 err = mlx5_ib_alloc_q_counters(dev);
3184 if (err)
3185 goto err_odp;
3186 }
3187
3188 err = ib_register_device(&dev->ib_dev, NULL);
3189 if (err)
3190 goto err_q_cnt;
3191
3192 err = create_umr_res(dev);
3193 if (err)
3194 goto err_dev;
3195
3196 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3197 err = device_create_file(&dev->ib_dev.dev,
3198 mlx5_class_attributes[i]);
3199 if (err)
3200 goto err_umrc;
3201 }
3202
3203 dev->ib_active = true;
3204
3205 return dev;
3206
3207 err_umrc:
3208 destroy_umrc_res(dev);
3209
3210 err_dev:
3211 ib_unregister_device(&dev->ib_dev);
3212
3213 err_q_cnt:
3214 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3215 mlx5_ib_dealloc_q_counters(dev);
3216
3217 err_odp:
3218 mlx5_ib_odp_remove_one(dev);
3219
3220 err_rsrc:
3221 destroy_dev_resources(&dev->devr);
3222
3223 err_disable_roce:
3224 if (ll == IB_LINK_LAYER_ETHERNET) {
3225 mlx5_disable_roce(dev);
3226 mlx5_remove_roce_notifier(dev);
3227 }
3228
3229 err_free_port:
3230 kfree(dev->port);
3231
3232 err_dealloc:
3233 ib_dealloc_device((struct ib_device *)dev);
3234
3235 return NULL;
3236 }
3237
mlx5_ib_remove(struct mlx5_core_dev * mdev,void * context)3238 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3239 {
3240 struct mlx5_ib_dev *dev = context;
3241 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3242
3243 mlx5_remove_roce_notifier(dev);
3244 ib_unregister_device(&dev->ib_dev);
3245 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3246 mlx5_ib_dealloc_q_counters(dev);
3247 destroy_umrc_res(dev);
3248 mlx5_ib_odp_remove_one(dev);
3249 destroy_dev_resources(&dev->devr);
3250 if (ll == IB_LINK_LAYER_ETHERNET)
3251 mlx5_disable_roce(dev);
3252 kfree(dev->port);
3253 ib_dealloc_device(&dev->ib_dev);
3254 }
3255
3256 static struct mlx5_interface mlx5_ib_interface = {
3257 .add = mlx5_ib_add,
3258 .remove = mlx5_ib_remove,
3259 .event = mlx5_ib_event,
3260 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
3261 };
3262
mlx5_ib_init(void)3263 static int __init mlx5_ib_init(void)
3264 {
3265 int err;
3266
3267 if (deprecated_prof_sel != 2)
3268 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
3269
3270 err = mlx5_ib_odp_init();
3271 if (err)
3272 return err;
3273
3274 err = mlx5_register_interface(&mlx5_ib_interface);
3275 if (err)
3276 goto clean_odp;
3277
3278 return err;
3279
3280 clean_odp:
3281 mlx5_ib_odp_cleanup();
3282 return err;
3283 }
3284
mlx5_ib_cleanup(void)3285 static void __exit mlx5_ib_cleanup(void)
3286 {
3287 mlx5_unregister_interface(&mlx5_ib_interface);
3288 mlx5_ib_odp_cleanup();
3289 }
3290
3291 module_init(mlx5_ib_init);
3292 module_exit(mlx5_ib_cleanup);
3293