| /drivers/media/platform/exynos-gsc/ |
| D | gsc-regs.c | 26 u32 cfg; in gsc_wait_reset() local
29 cfg = readl(dev->regs + GSC_SW_RESET); in gsc_wait_reset()
30 if (!cfg) in gsc_wait_reset()
40 u32 cfg; in gsc_hw_set_frm_done_irq_mask() local
42 cfg = readl(dev->regs + GSC_IRQ); in gsc_hw_set_frm_done_irq_mask()
44 cfg |= GSC_IRQ_FRMDONE_MASK; in gsc_hw_set_frm_done_irq_mask()
46 cfg &= ~GSC_IRQ_FRMDONE_MASK; in gsc_hw_set_frm_done_irq_mask()
47 writel(cfg, dev->regs + GSC_IRQ); in gsc_hw_set_frm_done_irq_mask()
52 u32 cfg; in gsc_hw_set_gsc_irq_enable() local
54 cfg = readl(dev->regs + GSC_IRQ); in gsc_hw_set_gsc_irq_enable()
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| /drivers/media/platform/exynos4-is/ |
| D | fimc-reg.c | 24 u32 cfg; in fimc_hw_reset() local
26 cfg = readl(dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
27 cfg |= FIMC_REG_CISRCFMT_ITU601_8BIT; in fimc_hw_reset()
28 writel(cfg, dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset()
31 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
32 cfg |= (FIMC_REG_CIGCTRL_SWRST | FIMC_REG_CIGCTRL_IRQ_LEVEL); in fimc_hw_reset()
33 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
36 cfg = readl(dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
37 cfg &= ~FIMC_REG_CIGCTRL_SWRST; in fimc_hw_reset()
38 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset()
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| D | fimc-lite-reg.c | 26 u32 cfg; in flite_hw_reset() local
28 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
29 cfg |= FLITE_REG_CIGCTRL_SWRST_REQ; in flite_hw_reset()
30 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
33 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
34 if (cfg & FLITE_REG_CIGCTRL_SWRST_RDY) in flite_hw_reset()
39 cfg |= FLITE_REG_CIGCTRL_SWRST; in flite_hw_reset()
40 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset()
45 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS); in flite_hw_clear_pending_irq() local
46 cfg &= ~FLITE_REG_CISTATUS_IRQ_CAM; in flite_hw_clear_pending_irq()
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| /drivers/media/platform/s3c-camif/ |
| D | camif-regs.c | 21 u32 cfg; in camif_hw_reset() local
23 cfg = camif_read(camif, S3C_CAMIF_REG_CISRCFMT); in camif_hw_reset()
24 cfg |= CISRCFMT_ITU601_8BIT; in camif_hw_reset()
25 camif_write(camif, S3C_CAMIF_REG_CISRCFMT, cfg); in camif_hw_reset()
28 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL); in camif_hw_reset()
29 cfg |= CIGCTRL_SWRST; in camif_hw_reset()
31 cfg |= CIGCTRL_IRQ_LEVEL; in camif_hw_reset()
32 camif_write(camif, S3C_CAMIF_REG_CIGCTRL, cfg); in camif_hw_reset()
35 cfg = camif_read(camif, S3C_CAMIF_REG_CIGCTRL); in camif_hw_reset()
36 cfg &= ~CIGCTRL_SWRST; in camif_hw_reset()
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| /drivers/net/ethernet/cavium/liquidio/ |
| D | octeon_config.h | 116 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq) argument
117 #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs) argument
118 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size) argument
119 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type) argument
120 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min) argument
121 #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout) argument
123 #define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt) argument
124 #define CFG_SET_IQ_INTR_PKT(cfg, val) (cfg)->iq.iq_intr_pkt = val argument
126 #define CFG_GET_OQ_MAX_Q(cfg) ((cfg)->oq.max_oqs) argument
127 #define CFG_GET_OQ_INFO_PTR(cfg) ((cfg)->oq.info_ptr) argument
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| /drivers/pci/ |
| D | ecam.c | 42 struct pci_config_window *cfg; in pci_ecam_create() local
50 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); in pci_ecam_create()
51 if (!cfg) in pci_ecam_create()
54 cfg->parent = dev; in pci_ecam_create()
55 cfg->ops = ops; in pci_ecam_create()
56 cfg->busr.start = busr->start; in pci_ecam_create()
57 cfg->busr.end = busr->end; in pci_ecam_create()
58 cfg->busr.flags = IORESOURCE_BUS; in pci_ecam_create()
59 bus_range = resource_size(&cfg->busr); in pci_ecam_create()
63 cfg->busr.end = busr->start + bus_range - 1; in pci_ecam_create()
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| D | htirq.c | 28 struct ht_irq_cfg *cfg = irq_get_handler_data(irq); in write_ht_irq_msg() local
32 if (cfg->msg.address_lo != msg->address_lo) { in write_ht_irq_msg()
33 pci_write_config_byte(cfg->dev, cfg->pos + 2, cfg->idx); in write_ht_irq_msg()
34 pci_write_config_dword(cfg->dev, cfg->pos + 4, msg->address_lo); in write_ht_irq_msg()
36 if (cfg->msg.address_hi != msg->address_hi) { in write_ht_irq_msg()
37 pci_write_config_byte(cfg->dev, cfg->pos + 2, cfg->idx + 1); in write_ht_irq_msg()
38 pci_write_config_dword(cfg->dev, cfg->pos + 4, msg->address_hi); in write_ht_irq_msg()
40 if (cfg->update) in write_ht_irq_msg()
41 cfg->update(cfg->dev, irq, msg); in write_ht_irq_msg()
43 cfg->msg = *msg; in write_ht_irq_msg()
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| /drivers/gpu/drm/exynos/ |
| D | exynos_drm_gsc.c | 85 #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset)) argument
403 u32 cfg; in gsc_sw_reset() local
407 cfg = (GSC_SW_RESET_SRESET); in gsc_sw_reset()
408 gsc_write(cfg, GSC_SW_RESET); in gsc_sw_reset()
412 cfg = gsc_read(GSC_SW_RESET); in gsc_sw_reset()
413 if (!cfg) in gsc_sw_reset()
418 if (cfg) { in gsc_sw_reset()
424 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK); in gsc_sw_reset()
425 cfg |= (GSC_IN_BASE_ADDR_MASK | in gsc_sw_reset()
427 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK); in gsc_sw_reset()
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| D | exynos_drm_fimc.c | 197 u32 cfg; in fimc_sw_reset() local
200 cfg = fimc_read(ctx, EXYNOS_CISTATUS); in fimc_sw_reset()
201 if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) in fimc_sw_reset()
229 u32 cfg; in fimc_set_type_ctrl() local
233 cfg = fimc_read(ctx, EXYNOS_CIGCTRL); in fimc_set_type_ctrl()
234 cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK | in fimc_set_type_ctrl()
243 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_A | in fimc_set_type_ctrl()
247 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_B | in fimc_set_type_ctrl()
252 cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A | in fimc_set_type_ctrl()
259 fimc_write(ctx, cfg, EXYNOS_CIGCTRL); in fimc_set_type_ctrl()
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| /drivers/gpu/drm/msm/hdmi/ |
| D | hdmi_phy_8996.c | 226 struct hdmi_8996_phy_pll_reg_cfg *cfg) in pll_calculate() argument
293 cfg->com_svs_mode_clk_sel = 1; in pll_calculate()
295 cfg->com_svs_mode_clk_sel = 2; in pll_calculate()
297 cfg->com_hsclk_sel = (0x20 | pd.hsclk_divsel); in pll_calculate()
298 cfg->com_pll_cctrl_mode0 = cctrl; in pll_calculate()
299 cfg->com_pll_rctrl_mode0 = rctrl; in pll_calculate()
300 cfg->com_cp_ctrl_mode0 = cpctrl; in pll_calculate()
301 cfg->com_dec_start_mode0 = dec_start; in pll_calculate()
302 cfg->com_div_frac_start1_mode0 = (frac_start & 0xff); in pll_calculate()
303 cfg->com_div_frac_start2_mode0 = ((frac_start & 0xff00) >> 8); in pll_calculate()
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| D | hdmi_phy.c | 20 struct hdmi_phy_cfg *cfg = phy->cfg; in msm_hdmi_phy_resource_init() local
24 phy->regs = devm_kzalloc(dev, sizeof(phy->regs[0]) * cfg->num_regs, in msm_hdmi_phy_resource_init()
29 phy->clks = devm_kzalloc(dev, sizeof(phy->clks[0]) * cfg->num_clks, in msm_hdmi_phy_resource_init()
34 for (i = 0; i < cfg->num_regs; i++) { in msm_hdmi_phy_resource_init()
37 reg = devm_regulator_get(dev, cfg->reg_names[i]); in msm_hdmi_phy_resource_init()
41 cfg->reg_names[i], ret); in msm_hdmi_phy_resource_init()
48 for (i = 0; i < cfg->num_clks; i++) { in msm_hdmi_phy_resource_init()
51 clk = devm_clk_get(dev, cfg->clk_names[i]); in msm_hdmi_phy_resource_init()
55 cfg->clk_names[i], ret); in msm_hdmi_phy_resource_init()
67 struct hdmi_phy_cfg *cfg = phy->cfg; in msm_hdmi_phy_resource_enable() local
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| /drivers/scsi/cxlflash/ |
| D | main.c | 222 struct cxlflash_cfg *cfg = afu->parent; in cmd_complete() local
247 spin_lock_irqsave(&cfg->tmf_slock, lock_flags); in cmd_complete()
248 cfg->tmf_active = false; in cmd_complete()
249 wake_up_all_locked(&cfg->tmf_waitq); in cmd_complete()
250 spin_unlock_irqrestore(&cfg->tmf_slock, lock_flags); in cmd_complete()
320 struct cxlflash_cfg *cfg = afu->parent; in send_cmd() local
321 struct device *dev = &cfg->dev->dev; in send_cmd()
371 kref_get(&cfg->afu->mapcount); in send_cmd()
372 schedule_work(&cfg->work_q); in send_cmd()
413 struct cxlflash_cfg *cfg = (struct cxlflash_cfg *)host->hostdata; in send_tmf() local
[all …]
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| /drivers/net/ethernet/cavium/thunder/ |
| D | thunder_xcv.c | 70 u64 cfg; in xcv_init_hw() local
73 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
74 cfg &= ~DLL_RESET; in xcv_init_hw()
75 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
78 cfg = readq_relaxed(xcv->reg_base + XCV_RESET); in xcv_init_hw()
79 cfg &= ~CLK_RESET; in xcv_init_hw()
80 writeq_relaxed(cfg, xcv->reg_base + XCV_RESET); in xcv_init_hw()
87 cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL); in xcv_init_hw()
88 cfg &= ~0xFF03; in xcv_init_hw()
89 cfg |= CLKRX_BYP; in xcv_init_hw()
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| /drivers/block/rsxx/ |
| D | config.c | 32 static void initialize_config(struct rsxx_card_cfg *cfg) in initialize_config() argument
34 cfg->hdr.version = RSXX_CFG_VERSION; in initialize_config()
36 cfg->data.block_size = RSXX_HW_BLK_SIZE; in initialize_config()
37 cfg->data.stripe_size = RSXX_HW_BLK_SIZE; in initialize_config()
38 cfg->data.vendor_id = RSXX_VENDOR_ID_IBM; in initialize_config()
39 cfg->data.cache_order = (-1); in initialize_config()
40 cfg->data.intr_coal.mode = RSXX_INTR_COAL_DISABLED; in initialize_config()
41 cfg->data.intr_coal.count = 0; in initialize_config()
42 cfg->data.intr_coal.latency = 0; in initialize_config()
45 static u32 config_data_crc32(struct rsxx_card_cfg *cfg) in config_data_crc32() argument
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| /drivers/media/platform/davinci/ |
| D | vpbe.c | 65 struct vpbe_config *cfg = vpbe_dev->cfg; in vpbe_current_encoder_info() local
68 return ((index == 0) ? &cfg->venc : in vpbe_current_encoder_info()
69 &cfg->ext_encoders[index-1]); in vpbe_current_encoder_info()
80 static int vpbe_find_encoder_sd_index(struct vpbe_config *cfg, in vpbe_find_encoder_sd_index() argument
83 char *encoder_name = cfg->outputs[index].subdev_name; in vpbe_find_encoder_sd_index()
87 if (!strcmp(encoder_name, cfg->venc.module_name)) in vpbe_find_encoder_sd_index()
90 for (i = 0; i < cfg->num_ext_encoders; i++) { in vpbe_find_encoder_sd_index()
92 cfg->ext_encoders[i].module_name)) in vpbe_find_encoder_sd_index()
132 struct vpbe_config *cfg = vpbe_dev->cfg; in vpbe_enum_outputs() local
135 if (temp_index >= cfg->num_outputs) in vpbe_enum_outputs()
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| /drivers/media/tuners/ |
| D | qm1d1c0042.c | 63 struct qm1d1c0042_config cfg; member
70 return container_of(c, struct qm1d1c0042_state, cfg); in cfg_to_state()
132 __func__, state->cfg.fe->dvb->num, state->cfg.fe->id); in qm1d1c0042_wakeup()
141 struct qm1d1c0042_config *cfg; in qm1d1c0042_set_config() local
144 cfg = priv_cfg; in qm1d1c0042_set_config()
146 if (cfg->fe) in qm1d1c0042_set_config()
147 state->cfg.fe = cfg->fe; in qm1d1c0042_set_config()
149 if (cfg->xtal_freq != QM1D1C0042_CFG_XTAL_DFLT) in qm1d1c0042_set_config()
152 state->cfg.xtal_freq = default_cfg.xtal_freq; in qm1d1c0042_set_config()
154 state->cfg.lpf = cfg->lpf; in qm1d1c0042_set_config()
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| /drivers/cpufreq/ |
| D | s3c2412-cpufreq.c | 43 static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) in s3c2412_cpufreq_calcdivs() argument
49 fclk = cfg->freq.fclk; in s3c2412_cpufreq_calcdivs()
50 armclk = cfg->freq.armclk; in s3c2412_cpufreq_calcdivs()
51 hclk_max = cfg->max.hclk; in s3c2412_cpufreq_calcdivs()
62 __func__, cfg->freq.fclk, cfg->freq.armclk, in s3c2412_cpufreq_calcdivs()
63 cfg->freq.hclk, cfg->freq.pclk); in s3c2412_cpufreq_calcdivs()
72 cfg->divs.arm_divisor = armdiv; in s3c2412_cpufreq_calcdivs()
79 cfg->freq.hclk = hclk = armdiv_clk / hdiv; in s3c2412_cpufreq_calcdivs()
82 cfg->divs.dvs = dvs = armclk < armdiv_clk; in s3c2412_cpufreq_calcdivs()
85 cfg->freq.armclk = dvs ? hclk : armdiv_clk; in s3c2412_cpufreq_calcdivs()
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| D | s3c24xx-cpufreq-debugfs.c | 41 struct s3c_cpufreq_config *cfg; in board_show() local
44 cfg = s3c_cpufreq_getconfig(); in board_show()
45 if (!cfg) { in board_show()
50 brd = cfg->board; in board_show()
81 struct s3c_cpufreq_config *cfg; in info_show() local
83 cfg = s3c_cpufreq_getconfig(); in info_show()
84 if (!cfg) { in info_show()
89 seq_printf(seq, " FCLK %ld Hz\n", cfg->freq.fclk); in info_show()
91 cfg->freq.hclk, print_ns(cfg->freq.hclk_tns)); in info_show()
92 seq_printf(seq, " PCLK %ld Hz\n", cfg->freq.hclk); in info_show()
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| D | s3c24xx-cpufreq.c | 65 static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg) in s3c_cpufreq_getcur() argument
69 cfg->freq.fclk = fclk = clk_get_rate(clk_fclk); in s3c_cpufreq_getcur()
70 cfg->freq.hclk = hclk = clk_get_rate(clk_hclk); in s3c_cpufreq_getcur()
71 cfg->freq.pclk = pclk = clk_get_rate(clk_pclk); in s3c_cpufreq_getcur()
72 cfg->freq.armclk = armclk = clk_get_rate(clk_arm); in s3c_cpufreq_getcur()
74 cfg->pll.driver_data = __raw_readl(S3C2410_MPLLCON); in s3c_cpufreq_getcur()
75 cfg->pll.frequency = fclk; in s3c_cpufreq_getcur()
77 cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); in s3c_cpufreq_getcur()
79 cfg->divs.h_divisor = fclk / hclk; in s3c_cpufreq_getcur()
80 cfg->divs.p_divisor = fclk / pclk; in s3c_cpufreq_getcur()
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| /drivers/pinctrl/sh-pfc/ |
| D | sh_pfc.h | 365 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ argument
366 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
369 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ argument
370 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
371 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
372 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
373 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
376 #define PORT_GP_CFG_8(bank, fn, sfx, cfg) \ argument
377 PORT_GP_CFG_4(bank, fn, sfx, cfg), \
378 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
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| /drivers/iommu/ |
| D | io-pgtable-arm.c | 211 struct io_pgtable_cfg *cfg) in __arm_lpae_alloc_pages() argument
213 struct device *dev = cfg->iommu_dev; in __arm_lpae_alloc_pages()
244 struct io_pgtable_cfg *cfg) in __arm_lpae_free_pages() argument
247 dma_unmap_single(cfg->iommu_dev, __arm_lpae_dma_addr(pages), in __arm_lpae_free_pages()
253 struct io_pgtable_cfg *cfg) in __arm_lpae_set_pte() argument
258 dma_sync_single_for_device(cfg->iommu_dev, in __arm_lpae_set_pte()
273 struct io_pgtable_cfg *cfg = &data->iop.cfg; in arm_lpae_init_pte() local
292 if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS) in arm_lpae_init_pte()
303 __arm_lpae_set_pte(ptep, pte, cfg); in arm_lpae_init_pte()
313 struct io_pgtable_cfg *cfg = &data->iop.cfg; in __arm_lpae_map() local
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| /drivers/acpi/ |
| D | acpi_configfs.c | 21 struct config_item cfg; member
25 static ssize_t acpi_table_aml_write(struct config_item *cfg, in acpi_table_aml_write() argument
32 table = container_of(cfg, struct acpi_table, cfg); in acpi_table_aml_write()
49 table = container_of(cfg, struct acpi_table, cfg); in acpi_table_aml_write()
64 static inline struct acpi_table_header *get_header(struct config_item *cfg) in get_header() argument
66 struct acpi_table *table = container_of(cfg, struct acpi_table, cfg); in get_header()
74 static ssize_t acpi_table_aml_read(struct config_item *cfg, in acpi_table_aml_read() argument
77 struct acpi_table_header *h = get_header(cfg); in acpi_table_aml_read()
97 ssize_t acpi_table_signature_show(struct config_item *cfg, char *str) in acpi_table_signature_show() argument
99 struct acpi_table_header *h = get_header(cfg); in acpi_table_signature_show()
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| /drivers/leds/ |
| D | leds-lp55xx-common.c | 43 struct lp55xx_device_config *cfg = chip->cfg; in lp55xx_reset_device() local
44 u8 addr = cfg->reset.addr; in lp55xx_reset_device()
45 u8 val = cfg->reset.val; in lp55xx_reset_device()
53 struct lp55xx_device_config *cfg = chip->cfg; in lp55xx_detect_device() local
54 u8 addr = cfg->enable.addr; in lp55xx_detect_device()
55 u8 val = cfg->enable.val; in lp55xx_detect_device()
68 if (val != cfg->enable.val) in lp55xx_detect_device()
76 struct lp55xx_device_config *cfg = chip->cfg; in lp55xx_post_init_device() local
78 if (!cfg->post_init_device) in lp55xx_post_init_device()
81 return cfg->post_init_device(chip); in lp55xx_post_init_device()
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| /drivers/net/ethernet/freescale/fman/ |
| D | fman_port.c | 451 struct fman_port_cfg *cfg; member
464 struct fman_port_cfg *cfg = port->cfg; in init_bmi_rx() local
468 tmp = (u32)cfg->dma_swap_data << BMI_DMA_ATTR_SWP_SHIFT; in init_bmi_rx()
474 tmp = (cfg->rx_pri_elevation / PORT_BMI_FIFO_UNITS - 1) << in init_bmi_rx()
476 tmp |= cfg->rx_fifo_thr / PORT_BMI_FIFO_UNITS - 1; in init_bmi_rx()
479 if (cfg->excessive_threshold_register) in init_bmi_rx()
484 tmp = (cfg->cheksum_last_bytes_ignore & BMI_FRAME_END_CS_IGNORE_MASK) << in init_bmi_rx()
486 tmp |= (cfg->rx_cut_end_bytes & BMI_RX_FRAME_END_CUT_MASK) << in init_bmi_rx()
488 if (cfg->errata_A006320) in init_bmi_rx()
493 tmp = ((cfg->int_context.ext_buf_offset / PORT_IC_OFFSET_UNITS) & in init_bmi_rx()
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| /drivers/usb/serial/ |
| D | kl5kusb105.c | 115 struct klsi_105_port_settings cfg; member
226 priv->cfg.pktlen = 5; in klsi_105_port_probe()
227 priv->cfg.baudrate = kl5kusb105a_sio_b9600; in klsi_105_port_probe()
228 priv->cfg.databits = kl5kusb105a_dtb_8; in klsi_105_port_probe()
229 priv->cfg.unknown1 = 0; in klsi_105_port_probe()
230 priv->cfg.unknown2 = 1; in klsi_105_port_probe()
260 struct klsi_105_port_settings *cfg; in klsi_105_open() local
270 cfg = kmalloc(sizeof(*cfg), GFP_KERNEL); in klsi_105_open()
271 if (!cfg) in klsi_105_open()
274 cfg->pktlen = 5; in klsi_105_open()
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