1 /*
2 * Copyright 2008 Simtec Electronics
3 * http://armlinux.simtec.co.uk/
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2412 CPU Frequency scalling
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/ioport.h>
19 #include <linux/cpufreq.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
22 #include <linux/clk.h>
23 #include <linux/err.h>
24 #include <linux/io.h>
25
26 #include <asm/mach/arch.h>
27 #include <asm/mach/map.h>
28
29 #include <mach/regs-clock.h>
30 #include <mach/s3c2412.h>
31
32 #include <plat/cpu.h>
33 #include <plat/cpu-freq-core.h>
34
35 /* our clock resources. */
36 static struct clk *xtal;
37 static struct clk *fclk;
38 static struct clk *hclk;
39 static struct clk *armclk;
40
41 /* HDIV: 1, 2, 3, 4, 6, 8 */
42
s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config * cfg)43 static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
44 {
45 unsigned int hdiv, pdiv, armdiv, dvs;
46 unsigned long hclk, fclk, armclk, armdiv_clk;
47 unsigned long hclk_max;
48
49 fclk = cfg->freq.fclk;
50 armclk = cfg->freq.armclk;
51 hclk_max = cfg->max.hclk;
52
53 /* We can't run hclk above armclk as at the best we have to
54 * have armclk and hclk in dvs mode. */
55
56 if (hclk_max > armclk)
57 hclk_max = armclk;
58
59 s3c_freq_dbg("%s: fclk=%lu, armclk=%lu, hclk_max=%lu\n",
60 __func__, fclk, armclk, hclk_max);
61 s3c_freq_dbg("%s: want f=%lu, arm=%lu, h=%lu, p=%lu\n",
62 __func__, cfg->freq.fclk, cfg->freq.armclk,
63 cfg->freq.hclk, cfg->freq.pclk);
64
65 armdiv = fclk / armclk;
66
67 if (armdiv < 1)
68 armdiv = 1;
69 if (armdiv > 2)
70 armdiv = 2;
71
72 cfg->divs.arm_divisor = armdiv;
73 armdiv_clk = fclk / armdiv;
74
75 hdiv = armdiv_clk / hclk_max;
76 if (hdiv < 1)
77 hdiv = 1;
78
79 cfg->freq.hclk = hclk = armdiv_clk / hdiv;
80
81 /* set dvs depending on whether we reached armclk or not. */
82 cfg->divs.dvs = dvs = armclk < armdiv_clk;
83
84 /* update the actual armclk we achieved. */
85 cfg->freq.armclk = dvs ? hclk : armdiv_clk;
86
87 s3c_freq_dbg("%s: armclk %lu, hclk %lu, armdiv %d, hdiv %d, dvs %d\n",
88 __func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs);
89
90 if (hdiv > 4)
91 goto invalid;
92
93 pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
94
95 if ((hclk / pdiv) > cfg->max.pclk)
96 pdiv++;
97
98 cfg->freq.pclk = hclk / pdiv;
99
100 s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
101
102 if (pdiv > 2)
103 goto invalid;
104
105 pdiv *= hdiv;
106
107 /* store the result, and then return */
108
109 cfg->divs.h_divisor = hdiv * armdiv;
110 cfg->divs.p_divisor = pdiv * armdiv;
111
112 return 0;
113
114 invalid:
115 return -EINVAL;
116 }
117
s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config * cfg)118 static void s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
119 {
120 unsigned long clkdiv;
121 unsigned long olddiv;
122
123 olddiv = clkdiv = __raw_readl(S3C2410_CLKDIVN);
124
125 /* clear off current clock info */
126
127 clkdiv &= ~S3C2412_CLKDIVN_ARMDIVN;
128 clkdiv &= ~S3C2412_CLKDIVN_HDIVN_MASK;
129 clkdiv &= ~S3C2412_CLKDIVN_PDIVN;
130
131 if (cfg->divs.arm_divisor == 2)
132 clkdiv |= S3C2412_CLKDIVN_ARMDIVN;
133
134 clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1);
135
136 if (cfg->divs.p_divisor != cfg->divs.h_divisor)
137 clkdiv |= S3C2412_CLKDIVN_PDIVN;
138
139 s3c_freq_dbg("%s: div %08lx => %08lx\n", __func__, olddiv, clkdiv);
140 __raw_writel(clkdiv, S3C2410_CLKDIVN);
141
142 clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
143 }
144
s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config * cfg)145 static void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
146 {
147 struct s3c_cpufreq_board *board = cfg->board;
148 unsigned long refresh;
149
150 s3c_freq_dbg("%s: refresh %u ns, hclk %lu\n", __func__,
151 board->refresh, cfg->freq.hclk);
152
153 /* Reduce both the refresh time (in ns) and the frequency (in MHz)
154 * by 10 each to ensure that we do not overflow 32 bit numbers. This
155 * should work for HCLK up to 133MHz and refresh period up to 30usec.
156 */
157
158 refresh = (board->refresh / 10);
159 refresh *= (cfg->freq.hclk / 100);
160 refresh /= (1 * 1000 * 1000); /* 10^6 */
161
162 s3c_freq_dbg("%s: setting refresh 0x%08lx\n", __func__, refresh);
163 __raw_writel(refresh, S3C2412_REFRESH);
164 }
165
166 /* set the default cpu frequency information, based on an 200MHz part
167 * as we have no other way of detecting the speed rating in software.
168 */
169
170 static struct s3c_cpufreq_info s3c2412_cpufreq_info = {
171 .max = {
172 .fclk = 200000000,
173 .hclk = 100000000,
174 .pclk = 50000000,
175 },
176
177 .latency = 5000000, /* 5ms */
178
179 .locktime_m = 150,
180 .locktime_u = 150,
181 .locktime_bits = 16,
182
183 .name = "s3c2412",
184 .set_refresh = s3c2412_cpufreq_setrefresh,
185 .set_divs = s3c2412_cpufreq_setdivs,
186 .calc_divs = s3c2412_cpufreq_calcdivs,
187
188 .calc_iotiming = s3c2412_iotiming_calc,
189 .set_iotiming = s3c2412_iotiming_set,
190 .get_iotiming = s3c2412_iotiming_get,
191
192 .debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs),
193 };
194
s3c2412_cpufreq_add(struct device * dev,struct subsys_interface * sif)195 static int s3c2412_cpufreq_add(struct device *dev,
196 struct subsys_interface *sif)
197 {
198 unsigned long fclk_rate;
199
200 hclk = clk_get(NULL, "hclk");
201 if (IS_ERR(hclk)) {
202 pr_err("cannot find hclk clock\n");
203 return -ENOENT;
204 }
205
206 fclk = clk_get(NULL, "fclk");
207 if (IS_ERR(fclk)) {
208 pr_err("cannot find fclk clock\n");
209 goto err_fclk;
210 }
211
212 fclk_rate = clk_get_rate(fclk);
213 if (fclk_rate > 200000000) {
214 pr_info("fclk %ld MHz, assuming 266MHz capable part\n",
215 fclk_rate / 1000000);
216 s3c2412_cpufreq_info.max.fclk = 266000000;
217 s3c2412_cpufreq_info.max.hclk = 133000000;
218 s3c2412_cpufreq_info.max.pclk = 66000000;
219 }
220
221 armclk = clk_get(NULL, "armclk");
222 if (IS_ERR(armclk)) {
223 pr_err("cannot find arm clock\n");
224 goto err_armclk;
225 }
226
227 xtal = clk_get(NULL, "xtal");
228 if (IS_ERR(xtal)) {
229 pr_err("cannot find xtal clock\n");
230 goto err_xtal;
231 }
232
233 return s3c_cpufreq_register(&s3c2412_cpufreq_info);
234
235 err_xtal:
236 clk_put(armclk);
237 err_armclk:
238 clk_put(fclk);
239 err_fclk:
240 clk_put(hclk);
241
242 return -ENOENT;
243 }
244
245 static struct subsys_interface s3c2412_cpufreq_interface = {
246 .name = "s3c2412_cpufreq",
247 .subsys = &s3c2412_subsys,
248 .add_dev = s3c2412_cpufreq_add,
249 };
250
s3c2412_cpufreq_init(void)251 static int s3c2412_cpufreq_init(void)
252 {
253 return subsys_interface_register(&s3c2412_cpufreq_interface);
254 }
255 arch_initcall(s3c2412_cpufreq_init);
256