Home
last modified time | relevance | path

Searched refs:clk_mask (Results 1 – 6 of 6) sorted by relevance

/drivers/clk/sunxi/
Dclk-usb.c91 u32 clk_mask; member
118 qty = find_last_bit((unsigned long *)&data->clk_mask, in sunxi_usb_clk_setup()
131 for_each_set_bit(i, (unsigned long *)&data->clk_mask, in sunxi_usb_clk_setup()
174 .clk_mask = BIT(8) | BIT(7) | BIT(6),
187 .clk_mask = BIT(8) | BIT(6),
198 .clk_mask = BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8),
209 .clk_mask = BIT(16) | BIT(11) | BIT(10) | BIT(9) | BIT(8),
220 .clk_mask = BIT(19) | BIT(18) | BIT(17) | BIT(16) |
232 .clk_mask = BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1),
246 .clk_mask = BIT(10) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1),
/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dnv50.c446 clk_mask(hwsq, mast, mastm, 0x00000000); in nv50_clk_calc()
447 clk_mask(hwsq, divs, divsm, divsv); in nv50_clk_calc()
448 clk_mask(hwsq, mast, mastm, mastv); in nv50_clk_calc()
454 clk_mask(hwsq, mast, 0x001000b0, 0x00100080); in nv50_clk_calc()
456 clk_mask(hwsq, mast, 0x000000b3, 0x00000081); in nv50_clk_calc()
463 clk_mask(hwsq, nvpll[0], 0xc03f0100, in nv50_clk_calc()
465 clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M); in nv50_clk_calc()
474 clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16)); in nv50_clk_calc()
475 clk_mask(hwsq, mast, 0x00100033, 0x00000023); in nv50_clk_calc()
481 clk_mask(hwsq, spll[0], 0xc03f0100, in nv50_clk_calc()
[all …]
Dseq.h10 #define clk_mask(s,r,m,d) hwsq_mask(&(s)->base, &(s)->r_##r, (m), (d)) macro
/drivers/gpu/drm/msm/edp/
Dedp_ctrl.c200 static int edp_clk_enable(struct edp_ctrl *ctrl, u32 clk_mask) in edp_clk_enable() argument
204 DBG("mask=%x", clk_mask); in edp_clk_enable()
206 if (clk_mask & EDP_CLK_MASK_AHB) { in edp_clk_enable()
213 if (clk_mask & EDP_CLK_MASK_AUX) { in edp_clk_enable()
226 if (clk_mask & EDP_CLK_MASK_LINK) { in edp_clk_enable()
243 if (clk_mask & EDP_CLK_MASK_PIXEL) { in edp_clk_enable()
260 if (clk_mask & EDP_CLK_MASK_MDP_CORE) { in edp_clk_enable()
271 if (clk_mask & EDP_CLK_MASK_PIXEL) in edp_clk_enable()
274 if (clk_mask & EDP_CLK_MASK_LINK) in edp_clk_enable()
277 if (clk_mask & EDP_CLK_MASK_AUX) in edp_clk_enable()
[all …]
/drivers/spi/
Dspi-ti-qspi.c146 u32 clk_ctrl_reg, clk_rate, clk_mask; in ti_qspi_setup() local
190 clk_mask = QSPI_CLK_EN | clk_div; in ti_qspi_setup()
191 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_setup()
192 ctx_reg->clkctrl = clk_mask; in ti_qspi_setup()
/drivers/gpu/drm/radeon/
Dradeon_combios.c416 u32 clk_mask, in combios_setup_i2c_bus() argument
520 if (clk_mask && data_mask) { in combios_setup_i2c_bus()
522 i2c.mask_clk_mask = clk_mask; in combios_setup_i2c_bus()
524 i2c.a_clk_mask = clk_mask; in combios_setup_i2c_bus()
526 i2c.en_clk_mask = clk_mask; in combios_setup_i2c_bus()
528 i2c.y_clk_mask = clk_mask; in combios_setup_i2c_bus()