1 /*
2 * TI QSPI driver
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 * Author: Sourav Poddar <sourav.poddar@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GPLv2.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/delay.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/omap-dma.h>
25 #include <linux/platform_device.h>
26 #include <linux/err.h>
27 #include <linux/clk.h>
28 #include <linux/io.h>
29 #include <linux/slab.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/of.h>
32 #include <linux/of_device.h>
33 #include <linux/pinctrl/consumer.h>
34 #include <linux/mfd/syscon.h>
35 #include <linux/regmap.h>
36
37 #include <linux/spi/spi.h>
38
39 struct ti_qspi_regs {
40 u32 clkctrl;
41 };
42
43 struct ti_qspi {
44 struct completion transfer_complete;
45
46 /* list synchronization */
47 struct mutex list_lock;
48
49 struct spi_master *master;
50 void __iomem *base;
51 void __iomem *mmap_base;
52 struct regmap *ctrl_base;
53 unsigned int ctrl_reg;
54 struct clk *fclk;
55 struct device *dev;
56
57 struct ti_qspi_regs ctx_reg;
58
59 dma_addr_t mmap_phys_base;
60 struct dma_chan *rx_chan;
61
62 u32 spi_max_frequency;
63 u32 cmd;
64 u32 dc;
65
66 bool mmap_enabled;
67 };
68
69 #define QSPI_PID (0x0)
70 #define QSPI_SYSCONFIG (0x10)
71 #define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
72 #define QSPI_SPI_DC_REG (0x44)
73 #define QSPI_SPI_CMD_REG (0x48)
74 #define QSPI_SPI_STATUS_REG (0x4c)
75 #define QSPI_SPI_DATA_REG (0x50)
76 #define QSPI_SPI_SETUP_REG(n) ((0x54 + 4 * n))
77 #define QSPI_SPI_SWITCH_REG (0x64)
78 #define QSPI_SPI_DATA_REG_1 (0x68)
79 #define QSPI_SPI_DATA_REG_2 (0x6c)
80 #define QSPI_SPI_DATA_REG_3 (0x70)
81
82 #define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
83
84 #define QSPI_FCLK 192000000
85
86 /* Clock Control */
87 #define QSPI_CLK_EN (1 << 31)
88 #define QSPI_CLK_DIV_MAX 0xffff
89
90 /* Command */
91 #define QSPI_EN_CS(n) (n << 28)
92 #define QSPI_WLEN(n) ((n - 1) << 19)
93 #define QSPI_3_PIN (1 << 18)
94 #define QSPI_RD_SNGL (1 << 16)
95 #define QSPI_WR_SNGL (2 << 16)
96 #define QSPI_RD_DUAL (3 << 16)
97 #define QSPI_RD_QUAD (7 << 16)
98 #define QSPI_INVAL (4 << 16)
99 #define QSPI_FLEN(n) ((n - 1) << 0)
100 #define QSPI_WLEN_MAX_BITS 128
101 #define QSPI_WLEN_MAX_BYTES 16
102 #define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
103
104 /* STATUS REGISTER */
105 #define BUSY 0x01
106 #define WC 0x02
107
108 /* Device Control */
109 #define QSPI_DD(m, n) (m << (3 + n * 8))
110 #define QSPI_CKPHA(n) (1 << (2 + n * 8))
111 #define QSPI_CSPOL(n) (1 << (1 + n * 8))
112 #define QSPI_CKPOL(n) (1 << (n * 8))
113
114 #define QSPI_FRAME 4096
115
116 #define QSPI_AUTOSUSPEND_TIMEOUT 2000
117
118 #define MEM_CS_EN(n) ((n + 1) << 8)
119 #define MEM_CS_MASK (7 << 8)
120
121 #define MM_SWITCH 0x1
122
123 #define QSPI_SETUP_RD_NORMAL (0x0 << 12)
124 #define QSPI_SETUP_RD_DUAL (0x1 << 12)
125 #define QSPI_SETUP_RD_QUAD (0x3 << 12)
126 #define QSPI_SETUP_ADDR_SHIFT 8
127 #define QSPI_SETUP_DUMMY_SHIFT 10
128
ti_qspi_read(struct ti_qspi * qspi,unsigned long reg)129 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
130 unsigned long reg)
131 {
132 return readl(qspi->base + reg);
133 }
134
ti_qspi_write(struct ti_qspi * qspi,unsigned long val,unsigned long reg)135 static inline void ti_qspi_write(struct ti_qspi *qspi,
136 unsigned long val, unsigned long reg)
137 {
138 writel(val, qspi->base + reg);
139 }
140
ti_qspi_setup(struct spi_device * spi)141 static int ti_qspi_setup(struct spi_device *spi)
142 {
143 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
144 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
145 int clk_div = 0, ret;
146 u32 clk_ctrl_reg, clk_rate, clk_mask;
147
148 if (spi->master->busy) {
149 dev_dbg(qspi->dev, "master busy doing other transfers\n");
150 return -EBUSY;
151 }
152
153 if (!qspi->spi_max_frequency) {
154 dev_err(qspi->dev, "spi max frequency not defined\n");
155 return -EINVAL;
156 }
157
158 clk_rate = clk_get_rate(qspi->fclk);
159
160 clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
161
162 if (clk_div < 0) {
163 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
164 return -EINVAL;
165 }
166
167 if (clk_div > QSPI_CLK_DIV_MAX) {
168 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
169 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
170 return -EINVAL;
171 }
172
173 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
174 qspi->spi_max_frequency, clk_div);
175
176 ret = pm_runtime_get_sync(qspi->dev);
177 if (ret < 0) {
178 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
179 return ret;
180 }
181
182 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
183
184 clk_ctrl_reg &= ~QSPI_CLK_EN;
185
186 /* disable SCLK */
187 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
188
189 /* enable SCLK */
190 clk_mask = QSPI_CLK_EN | clk_div;
191 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
192 ctx_reg->clkctrl = clk_mask;
193
194 pm_runtime_mark_last_busy(qspi->dev);
195 ret = pm_runtime_put_autosuspend(qspi->dev);
196 if (ret < 0) {
197 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
198 return ret;
199 }
200
201 return 0;
202 }
203
ti_qspi_restore_ctx(struct ti_qspi * qspi)204 static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
205 {
206 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
207
208 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
209 }
210
qspi_is_busy(struct ti_qspi * qspi)211 static inline u32 qspi_is_busy(struct ti_qspi *qspi)
212 {
213 u32 stat;
214 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
215
216 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
217 while ((stat & BUSY) && time_after(timeout, jiffies)) {
218 cpu_relax();
219 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
220 }
221
222 WARN(stat & BUSY, "qspi busy\n");
223 return stat & BUSY;
224 }
225
ti_qspi_poll_wc(struct ti_qspi * qspi)226 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
227 {
228 u32 stat;
229 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
230
231 do {
232 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
233 if (stat & WC)
234 return 0;
235 cpu_relax();
236 } while (time_after(timeout, jiffies));
237
238 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
239 if (stat & WC)
240 return 0;
241 return -ETIMEDOUT;
242 }
243
qspi_write_msg(struct ti_qspi * qspi,struct spi_transfer * t,int count)244 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
245 int count)
246 {
247 int wlen, xfer_len;
248 unsigned int cmd;
249 const u8 *txbuf;
250 u32 data;
251
252 txbuf = t->tx_buf;
253 cmd = qspi->cmd | QSPI_WR_SNGL;
254 wlen = t->bits_per_word >> 3; /* in bytes */
255 xfer_len = wlen;
256
257 while (count) {
258 if (qspi_is_busy(qspi))
259 return -EBUSY;
260
261 switch (wlen) {
262 case 1:
263 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
264 cmd, qspi->dc, *txbuf);
265 if (count >= QSPI_WLEN_MAX_BYTES) {
266 u32 *txp = (u32 *)txbuf;
267
268 data = cpu_to_be32(*txp++);
269 writel(data, qspi->base +
270 QSPI_SPI_DATA_REG_3);
271 data = cpu_to_be32(*txp++);
272 writel(data, qspi->base +
273 QSPI_SPI_DATA_REG_2);
274 data = cpu_to_be32(*txp++);
275 writel(data, qspi->base +
276 QSPI_SPI_DATA_REG_1);
277 data = cpu_to_be32(*txp++);
278 writel(data, qspi->base +
279 QSPI_SPI_DATA_REG);
280 xfer_len = QSPI_WLEN_MAX_BYTES;
281 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
282 } else {
283 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
284 cmd = qspi->cmd | QSPI_WR_SNGL;
285 xfer_len = wlen;
286 cmd |= QSPI_WLEN(wlen);
287 }
288 break;
289 case 2:
290 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
291 cmd, qspi->dc, *txbuf);
292 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
293 break;
294 case 4:
295 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
296 cmd, qspi->dc, *txbuf);
297 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
298 break;
299 }
300
301 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
302 if (ti_qspi_poll_wc(qspi)) {
303 dev_err(qspi->dev, "write timed out\n");
304 return -ETIMEDOUT;
305 }
306 txbuf += xfer_len;
307 count -= xfer_len;
308 }
309
310 return 0;
311 }
312
qspi_read_msg(struct ti_qspi * qspi,struct spi_transfer * t,int count)313 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
314 int count)
315 {
316 int wlen;
317 unsigned int cmd;
318 u8 *rxbuf;
319
320 rxbuf = t->rx_buf;
321 cmd = qspi->cmd;
322 switch (t->rx_nbits) {
323 case SPI_NBITS_DUAL:
324 cmd |= QSPI_RD_DUAL;
325 break;
326 case SPI_NBITS_QUAD:
327 cmd |= QSPI_RD_QUAD;
328 break;
329 default:
330 cmd |= QSPI_RD_SNGL;
331 break;
332 }
333 wlen = t->bits_per_word >> 3; /* in bytes */
334
335 while (count) {
336 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
337 if (qspi_is_busy(qspi))
338 return -EBUSY;
339
340 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
341 if (ti_qspi_poll_wc(qspi)) {
342 dev_err(qspi->dev, "read timed out\n");
343 return -ETIMEDOUT;
344 }
345 switch (wlen) {
346 case 1:
347 *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
348 break;
349 case 2:
350 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
351 break;
352 case 4:
353 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
354 break;
355 }
356 rxbuf += wlen;
357 count -= wlen;
358 }
359
360 return 0;
361 }
362
qspi_transfer_msg(struct ti_qspi * qspi,struct spi_transfer * t,int count)363 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
364 int count)
365 {
366 int ret;
367
368 if (t->tx_buf) {
369 ret = qspi_write_msg(qspi, t, count);
370 if (ret) {
371 dev_dbg(qspi->dev, "Error while writing\n");
372 return ret;
373 }
374 }
375
376 if (t->rx_buf) {
377 ret = qspi_read_msg(qspi, t, count);
378 if (ret) {
379 dev_dbg(qspi->dev, "Error while reading\n");
380 return ret;
381 }
382 }
383
384 return 0;
385 }
386
ti_qspi_dma_callback(void * param)387 static void ti_qspi_dma_callback(void *param)
388 {
389 struct ti_qspi *qspi = param;
390
391 complete(&qspi->transfer_complete);
392 }
393
ti_qspi_dma_xfer(struct ti_qspi * qspi,dma_addr_t dma_dst,dma_addr_t dma_src,size_t len)394 static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
395 dma_addr_t dma_src, size_t len)
396 {
397 struct dma_chan *chan = qspi->rx_chan;
398 struct dma_device *dma_dev = chan->device;
399 dma_cookie_t cookie;
400 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
401 struct dma_async_tx_descriptor *tx;
402 int ret;
403
404 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
405 len, flags);
406 if (!tx) {
407 dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
408 return -EIO;
409 }
410
411 tx->callback = ti_qspi_dma_callback;
412 tx->callback_param = qspi;
413 cookie = tx->tx_submit(tx);
414
415 ret = dma_submit_error(cookie);
416 if (ret) {
417 dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
418 return -EIO;
419 }
420
421 dma_async_issue_pending(chan);
422 ret = wait_for_completion_timeout(&qspi->transfer_complete,
423 msecs_to_jiffies(len));
424 if (ret <= 0) {
425 dmaengine_terminate_sync(chan);
426 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
427 return -ETIMEDOUT;
428 }
429
430 return 0;
431 }
432
ti_qspi_dma_xfer_sg(struct ti_qspi * qspi,struct sg_table rx_sg,loff_t from)433 static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
434 loff_t from)
435 {
436 struct scatterlist *sg;
437 dma_addr_t dma_src = qspi->mmap_phys_base + from;
438 dma_addr_t dma_dst;
439 int i, len, ret;
440
441 for_each_sg(rx_sg.sgl, sg, rx_sg.nents, i) {
442 dma_dst = sg_dma_address(sg);
443 len = sg_dma_len(sg);
444 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
445 if (ret)
446 return ret;
447 dma_src += len;
448 }
449
450 return 0;
451 }
452
ti_qspi_enable_memory_map(struct spi_device * spi)453 static void ti_qspi_enable_memory_map(struct spi_device *spi)
454 {
455 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
456
457 ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
458 if (qspi->ctrl_base) {
459 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
460 MEM_CS_EN(spi->chip_select),
461 MEM_CS_MASK);
462 }
463 qspi->mmap_enabled = true;
464 }
465
ti_qspi_disable_memory_map(struct spi_device * spi)466 static void ti_qspi_disable_memory_map(struct spi_device *spi)
467 {
468 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
469
470 ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
471 if (qspi->ctrl_base)
472 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
473 0, MEM_CS_MASK);
474 qspi->mmap_enabled = false;
475 }
476
ti_qspi_setup_mmap_read(struct spi_device * spi,struct spi_flash_read_message * msg)477 static void ti_qspi_setup_mmap_read(struct spi_device *spi,
478 struct spi_flash_read_message *msg)
479 {
480 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
481 u32 memval = msg->read_opcode;
482
483 switch (msg->data_nbits) {
484 case SPI_NBITS_QUAD:
485 memval |= QSPI_SETUP_RD_QUAD;
486 break;
487 case SPI_NBITS_DUAL:
488 memval |= QSPI_SETUP_RD_DUAL;
489 break;
490 default:
491 memval |= QSPI_SETUP_RD_NORMAL;
492 break;
493 }
494 memval |= ((msg->addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
495 msg->dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
496 ti_qspi_write(qspi, memval,
497 QSPI_SPI_SETUP_REG(spi->chip_select));
498 }
499
ti_qspi_spi_flash_read(struct spi_device * spi,struct spi_flash_read_message * msg)500 static int ti_qspi_spi_flash_read(struct spi_device *spi,
501 struct spi_flash_read_message *msg)
502 {
503 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
504 int ret = 0;
505
506 mutex_lock(&qspi->list_lock);
507
508 if (!qspi->mmap_enabled)
509 ti_qspi_enable_memory_map(spi);
510 ti_qspi_setup_mmap_read(spi, msg);
511
512 if (qspi->rx_chan) {
513 if (msg->cur_msg_mapped) {
514 ret = ti_qspi_dma_xfer_sg(qspi, msg->rx_sg, msg->from);
515 if (ret)
516 goto err_unlock;
517 } else {
518 dev_err(qspi->dev, "Invalid address for DMA\n");
519 ret = -EIO;
520 goto err_unlock;
521 }
522 } else {
523 memcpy_fromio(msg->buf, qspi->mmap_base + msg->from, msg->len);
524 }
525 msg->retlen = msg->len;
526
527 err_unlock:
528 mutex_unlock(&qspi->list_lock);
529
530 return ret;
531 }
532
ti_qspi_start_transfer_one(struct spi_master * master,struct spi_message * m)533 static int ti_qspi_start_transfer_one(struct spi_master *master,
534 struct spi_message *m)
535 {
536 struct ti_qspi *qspi = spi_master_get_devdata(master);
537 struct spi_device *spi = m->spi;
538 struct spi_transfer *t;
539 int status = 0, ret;
540 unsigned int frame_len_words, transfer_len_words;
541 int wlen;
542
543 /* setup device control reg */
544 qspi->dc = 0;
545
546 if (spi->mode & SPI_CPHA)
547 qspi->dc |= QSPI_CKPHA(spi->chip_select);
548 if (spi->mode & SPI_CPOL)
549 qspi->dc |= QSPI_CKPOL(spi->chip_select);
550 if (spi->mode & SPI_CS_HIGH)
551 qspi->dc |= QSPI_CSPOL(spi->chip_select);
552
553 frame_len_words = 0;
554 list_for_each_entry(t, &m->transfers, transfer_list)
555 frame_len_words += t->len / (t->bits_per_word >> 3);
556 frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
557
558 /* setup command reg */
559 qspi->cmd = 0;
560 qspi->cmd |= QSPI_EN_CS(spi->chip_select);
561 qspi->cmd |= QSPI_FLEN(frame_len_words);
562
563 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
564
565 mutex_lock(&qspi->list_lock);
566
567 if (qspi->mmap_enabled)
568 ti_qspi_disable_memory_map(spi);
569
570 list_for_each_entry(t, &m->transfers, transfer_list) {
571 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
572 QSPI_WLEN(t->bits_per_word));
573
574 wlen = t->bits_per_word >> 3;
575 transfer_len_words = min(t->len / wlen, frame_len_words);
576
577 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
578 if (ret) {
579 dev_dbg(qspi->dev, "transfer message failed\n");
580 mutex_unlock(&qspi->list_lock);
581 return -EINVAL;
582 }
583
584 m->actual_length += transfer_len_words * wlen;
585 frame_len_words -= transfer_len_words;
586 if (frame_len_words == 0)
587 break;
588 }
589
590 mutex_unlock(&qspi->list_lock);
591
592 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
593 m->status = status;
594 spi_finalize_current_message(master);
595
596 return status;
597 }
598
ti_qspi_runtime_resume(struct device * dev)599 static int ti_qspi_runtime_resume(struct device *dev)
600 {
601 struct ti_qspi *qspi;
602
603 qspi = dev_get_drvdata(dev);
604 ti_qspi_restore_ctx(qspi);
605
606 return 0;
607 }
608
609 static const struct of_device_id ti_qspi_match[] = {
610 {.compatible = "ti,dra7xxx-qspi" },
611 {.compatible = "ti,am4372-qspi" },
612 {},
613 };
614 MODULE_DEVICE_TABLE(of, ti_qspi_match);
615
ti_qspi_probe(struct platform_device * pdev)616 static int ti_qspi_probe(struct platform_device *pdev)
617 {
618 struct ti_qspi *qspi;
619 struct spi_master *master;
620 struct resource *r, *res_mmap;
621 struct device_node *np = pdev->dev.of_node;
622 u32 max_freq;
623 int ret = 0, num_cs, irq;
624 dma_cap_mask_t mask;
625
626 master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
627 if (!master)
628 return -ENOMEM;
629
630 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
631
632 master->flags = SPI_MASTER_HALF_DUPLEX;
633 master->setup = ti_qspi_setup;
634 master->auto_runtime_pm = true;
635 master->transfer_one_message = ti_qspi_start_transfer_one;
636 master->dev.of_node = pdev->dev.of_node;
637 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
638 SPI_BPW_MASK(8);
639 master->spi_flash_read = ti_qspi_spi_flash_read;
640
641 if (!of_property_read_u32(np, "num-cs", &num_cs))
642 master->num_chipselect = num_cs;
643
644 qspi = spi_master_get_devdata(master);
645 qspi->master = master;
646 qspi->dev = &pdev->dev;
647 platform_set_drvdata(pdev, qspi);
648
649 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
650 if (r == NULL) {
651 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
652 if (r == NULL) {
653 dev_err(&pdev->dev, "missing platform data\n");
654 return -ENODEV;
655 }
656 }
657
658 res_mmap = platform_get_resource_byname(pdev,
659 IORESOURCE_MEM, "qspi_mmap");
660 if (res_mmap == NULL) {
661 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
662 if (res_mmap == NULL) {
663 dev_err(&pdev->dev,
664 "memory mapped resource not required\n");
665 }
666 }
667
668 irq = platform_get_irq(pdev, 0);
669 if (irq < 0) {
670 dev_err(&pdev->dev, "no irq resource?\n");
671 return irq;
672 }
673
674 mutex_init(&qspi->list_lock);
675
676 qspi->base = devm_ioremap_resource(&pdev->dev, r);
677 if (IS_ERR(qspi->base)) {
678 ret = PTR_ERR(qspi->base);
679 goto free_master;
680 }
681
682
683 if (of_property_read_bool(np, "syscon-chipselects")) {
684 qspi->ctrl_base =
685 syscon_regmap_lookup_by_phandle(np,
686 "syscon-chipselects");
687 if (IS_ERR(qspi->ctrl_base))
688 return PTR_ERR(qspi->ctrl_base);
689 ret = of_property_read_u32_index(np,
690 "syscon-chipselects",
691 1, &qspi->ctrl_reg);
692 if (ret) {
693 dev_err(&pdev->dev,
694 "couldn't get ctrl_mod reg index\n");
695 return ret;
696 }
697 }
698
699 qspi->fclk = devm_clk_get(&pdev->dev, "fck");
700 if (IS_ERR(qspi->fclk)) {
701 ret = PTR_ERR(qspi->fclk);
702 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
703 }
704
705 pm_runtime_use_autosuspend(&pdev->dev);
706 pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
707 pm_runtime_enable(&pdev->dev);
708
709 if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
710 qspi->spi_max_frequency = max_freq;
711
712 dma_cap_zero(mask);
713 dma_cap_set(DMA_MEMCPY, mask);
714
715 qspi->rx_chan = dma_request_chan_by_mask(&mask);
716 if (!qspi->rx_chan) {
717 dev_err(qspi->dev,
718 "No Rx DMA available, trying mmap mode\n");
719 ret = 0;
720 goto no_dma;
721 }
722 master->dma_rx = qspi->rx_chan;
723 init_completion(&qspi->transfer_complete);
724 if (res_mmap)
725 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
726
727 no_dma:
728 if (!qspi->rx_chan && res_mmap) {
729 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
730 if (IS_ERR(qspi->mmap_base)) {
731 dev_info(&pdev->dev,
732 "mmap failed with error %ld using PIO mode\n",
733 PTR_ERR(qspi->mmap_base));
734 qspi->mmap_base = NULL;
735 master->spi_flash_read = NULL;
736 }
737 }
738 qspi->mmap_enabled = false;
739
740 ret = devm_spi_register_master(&pdev->dev, master);
741 if (!ret)
742 return 0;
743
744 free_master:
745 spi_master_put(master);
746 return ret;
747 }
748
ti_qspi_remove(struct platform_device * pdev)749 static int ti_qspi_remove(struct platform_device *pdev)
750 {
751 struct ti_qspi *qspi = platform_get_drvdata(pdev);
752 int rc;
753
754 rc = spi_master_suspend(qspi->master);
755 if (rc)
756 return rc;
757
758 pm_runtime_put_sync(&pdev->dev);
759 pm_runtime_disable(&pdev->dev);
760
761 if (qspi->rx_chan)
762 dma_release_channel(qspi->rx_chan);
763
764 return 0;
765 }
766
767 static const struct dev_pm_ops ti_qspi_pm_ops = {
768 .runtime_resume = ti_qspi_runtime_resume,
769 };
770
771 static struct platform_driver ti_qspi_driver = {
772 .probe = ti_qspi_probe,
773 .remove = ti_qspi_remove,
774 .driver = {
775 .name = "ti-qspi",
776 .pm = &ti_qspi_pm_ops,
777 .of_match_table = ti_qspi_match,
778 }
779 };
780
781 module_platform_driver(ti_qspi_driver);
782
783 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
784 MODULE_LICENSE("GPL v2");
785 MODULE_DESCRIPTION("TI QSPI controller driver");
786 MODULE_ALIAS("platform:ti-qspi");
787