| /drivers/gpu/drm/nouveau/nvkm/subdev/therm/ |
| D | fanpwm.c | 44 u32 divs, duty; in nvkm_fanpwm_get() local
47 ret = therm->func->pwm_get(therm, fan->func.line, &divs, &duty); in nvkm_fanpwm_get()
48 if (ret == 0 && divs) { in nvkm_fanpwm_get()
49 divs = max(divs, duty); in nvkm_fanpwm_get()
51 duty = divs - duty; in nvkm_fanpwm_get()
52 return (duty * 100) / divs; in nvkm_fanpwm_get()
63 u32 divs, duty; in nvkm_fanpwm_set() local
66 divs = fan->base.perf.pwm_divisor; in nvkm_fanpwm_set()
68 divs = 1; in nvkm_fanpwm_set()
70 divs = therm->func->pwm_clock(therm, fan->func.line); in nvkm_fanpwm_set()
[all …]
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| D | gf119.c | 67 gf119_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in gf119_fan_pwm_get() argument
75 *divs = nvkm_rd32(device, 0x00e114 + (indx * 8)); in gf119_fan_pwm_get()
80 *divs = nvkm_rd32(device, 0x0200d8) & 0x1fff; in gf119_fan_pwm_get()
89 gf119_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in gf119_fan_pwm_set() argument
96 nvkm_wr32(device, 0x00e114 + (indx * 8), divs); in gf119_fan_pwm_set()
99 nvkm_mask(device, 0x0200d8, 0x1fff, divs); /* keep the high bits */ in gf119_fan_pwm_set()
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| D | nv40.c | 121 nv40_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in nv40_fan_pwm_get() argument
129 *divs = (reg & 0x00007fff); in nv40_fan_pwm_get()
136 *divs = nvkm_rd32(device, 0x0015f8); in nv40_fan_pwm_get()
149 nv40_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in nv40_fan_pwm_set() argument
154 nvkm_mask(device, 0x0010f0, 0x7fff7fff, (duty << 16) | divs); in nv40_fan_pwm_set()
157 nvkm_wr32(device, 0x0015f8, divs); in nv40_fan_pwm_set()
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| D | gm107.c | 34 gm107_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in gm107_fan_pwm_get() argument
37 *divs = nvkm_rd32(device, 0x10eb20) & 0x1fff; in gm107_fan_pwm_get()
43 gm107_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in gm107_fan_pwm_set() argument
46 nvkm_mask(device, 0x10eb10, 0x1fff, divs); /* keep the high bits */ in gm107_fan_pwm_set()
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| D | nv50.c | 66 nv50_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in nv50_fan_pwm_get() argument
74 *divs = nvkm_rd32(device, 0x00e114 + (id * 8)); in nv50_fan_pwm_get()
83 nv50_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in nv50_fan_pwm_set() argument
90 nvkm_wr32(device, 0x00e114 + (id * 8), divs); in nv50_fan_pwm_set()
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| /drivers/cpufreq/ |
| D | s3c2440-cpufreq.c | 114 cfg->divs.dvs = 1; in s3c2440_cpufreq_calcdivs()
117 cfg->divs.dvs = 0; in s3c2440_cpufreq_calcdivs()
123 cfg->divs.h_divisor = hdiv; in s3c2440_cpufreq_calcdivs()
124 cfg->divs.p_divisor = pdiv; in s3c2440_cpufreq_calcdivs()
147 cfg->divs.h_divisor, cfg->divs.p_divisor); in s3c2440_cpufreq_setdivs()
155 switch (cfg->divs.h_divisor) { in s3c2440_cpufreq_setdivs()
180 if (cfg->divs.p_divisor != cfg->divs.h_divisor) in s3c2440_cpufreq_setdivs()
196 clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk); in s3c2440_cpufreq_setdivs()
200 int *divs, in run_freq_for() argument
208 for (div = *divs; div > 0; div = *divs++) { in run_freq_for()
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| D | s3c2412-cpufreq.c | 72 cfg->divs.arm_divisor = armdiv; in s3c2412_cpufreq_calcdivs()
82 cfg->divs.dvs = dvs = armclk < armdiv_clk; in s3c2412_cpufreq_calcdivs()
88 __func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs); in s3c2412_cpufreq_calcdivs()
109 cfg->divs.h_divisor = hdiv * armdiv; in s3c2412_cpufreq_calcdivs()
110 cfg->divs.p_divisor = pdiv * armdiv; in s3c2412_cpufreq_calcdivs()
131 if (cfg->divs.arm_divisor == 2) in s3c2412_cpufreq_setdivs()
134 clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1); in s3c2412_cpufreq_setdivs()
136 if (cfg->divs.p_divisor != cfg->divs.h_divisor) in s3c2412_cpufreq_setdivs()
142 clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk); in s3c2412_cpufreq_setdivs()
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| D | s3c2410-cpufreq.c | 37 if (cfg->divs.h_divisor == 2) in s3c2410_cpufreq_setdivs()
40 if (cfg->divs.p_divisor != cfg->divs.h_divisor) in s3c2410_cpufreq_setdivs()
79 cfg->divs.p_divisor = pdiv; in s3c2410_cpufreq_calcdivs()
80 cfg->divs.h_divisor = hdiv; in s3c2410_cpufreq_calcdivs()
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| D | s3c24xx-cpufreq-debugfs.c | 99 cfg->divs.h_divisor, cfg->divs.p_divisor, in info_show()
100 cfg->divs.arm_divisor, cfg->divs.dvs ? "on" : "off"); in info_show()
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| D | s3c24xx-cpufreq.c | 79 cfg->divs.h_divisor = fclk / hclk; in s3c_cpufreq_getcur()
80 cfg->divs.p_divisor = fclk / pclk; in s3c_cpufreq_getcur()
88 cfg->freq.hclk = pll / cfg->divs.h_divisor; in s3c_cpufreq_calc()
89 cfg->freq.pclk = pll / cfg->divs.p_divisor; in s3c_cpufreq_calc()
108 cfg->freq.hclk, cfg->divs.h_divisor, in s3c_cpufreq_show()
109 cfg->freq.pclk, cfg->divs.p_divisor); in s3c_cpufreq_show()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | mcp77.c | 212 int divs = 0; in mcp77_clk_calc() local
216 out = calc_P(nvkm_clk_read(&clk->base, nv_clk_src_hclkm4), core, &divs); in mcp77_clk_calc()
223 clk->cctrl = divs << 16; in mcp77_clk_calc()
247 out = calc_P((core << 1), shader, &divs); in mcp77_clk_calc()
251 (divs + P2) <= 7) { in mcp77_clk_calc()
253 clk->sctrl = (divs + P2) << 16; in mcp77_clk_calc()
262 out = calc_P(core, vdec, &divs); in mcp77_clk_calc()
266 clk->vdiv = divs << 16; in mcp77_clk_calc()
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| D | nv50.c | 447 clk_mask(hwsq, divs, divsm, divsv); in nv50_clk_calc()
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| /drivers/gpu/drm/msm/edp/ |
| D | edp_ctrl.c | 1326 const struct edp_pixel_clk_div *divs; in msm_edp_ctrl_pixel_clock_valid() local
1332 divs = clk_divs[0]; in msm_edp_ctrl_pixel_clock_valid()
1334 divs = clk_divs[1]; in msm_edp_ctrl_pixel_clock_valid()
1341 clk_err = abs(divs[i].rate - pixel_rate); in msm_edp_ctrl_pixel_clock_valid()
1342 if ((divs[i].rate * err / 100) >= clk_err) { in msm_edp_ctrl_pixel_clock_valid()
1344 *pm = divs[i].m; in msm_edp_ctrl_pixel_clock_valid()
1346 *pn = divs[i].n; in msm_edp_ctrl_pixel_clock_valid()
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| /drivers/clk/rockchip/ |
| D | clk-cpu.c | 111 for (i = 0; i < ARRAY_SIZE(rate->divs); i++) { in rockchip_cpuclk_set_dividers()
112 const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i]; in rockchip_cpuclk_set_dividers()
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| D | clk-rk3188.c | 138 .divs = { \
176 .divs = { \
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| D | clk-rk3368.c | 210 .divs = { \
220 .divs = { \
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| D | clk-rk3036.c | 101 .divs = { \
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| D | clk.h | 251 struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS]; member
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| D | clk-rk3399.c | 343 .divs = { \
353 .divs = { \
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| D | clk-rk3228.c | 99 .divs = { \
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| D | clk-rk3288.c | 141 .divs = { \
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| /drivers/i2c/busses/ |
| D | i2c-s3c2410.c | 813 unsigned int *div1, unsigned int *divs) in s3c24xx_i2c_calcdivisor() argument
831 *divs = calc_divs; in s3c24xx_i2c_calcdivisor()
846 unsigned int divs, div1; in s3c24xx_i2c_clockrate() local
860 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); in s3c24xx_i2c_clockrate()
873 iiccon |= (divs-1); in s3c24xx_i2c_clockrate()
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