Searched refs:dpm_level_enable_mask (Results 1 – 10 of 10) sorted by relevance
2626 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()3287 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()3341 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_populate_all_memory_levels()3805 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3808 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()3815 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3818 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()3825 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3828 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()3925 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_enable_uvd_dpm()[all …]
237 struct ci_dpm_level_enable_mask dpm_level_enable_mask; member
2753 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()3420 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()3474 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_populate_all_memory_levels()3942 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3945 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()3952 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3955 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()3963 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()3966 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()4061 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_enable_uvd_dpm()[all …]
239 struct ci_dpm_level_enable_mask dpm_level_enable_mask; member
2341 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { in smu7_force_dpm_highest()2343 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask; in smu7_force_dpm_highest()2354 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { in smu7_force_dpm_highest()2356 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; in smu7_force_dpm_highest()2368 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { in smu7_force_dpm_highest()2370 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask; in smu7_force_dpm_highest()2393 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) in smu7_upload_dpm_level_enable_mask()2396 data->dpm_level_enable_mask.sclk_dpm_enable_mask); in smu7_upload_dpm_level_enable_mask()2400 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) in smu7_upload_dpm_level_enable_mask()2403 data->dpm_level_enable_mask.mclk_dpm_enable_mask); in smu7_upload_dpm_level_enable_mask()[all …]
278 struct smu7_dpmlevel_enable_mask dpm_level_enable_mask; member
607 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in fiji_populate_smc_link_level()819 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in fiji_populate_all_graphic_levels()831 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in fiji_populate_all_graphic_levels()832 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in fiji_populate_all_graphic_levels()836 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in fiji_populate_all_graphic_levels()837 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in fiji_populate_all_graphic_levels()842 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in fiji_populate_all_graphic_levels()1039 data->dpm_level_enable_mask.mclk_dpm_enable_mask = in fiji_populate_all_memory_levels()
545 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in polaris10_populate_smc_link_level()793 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask = in polaris10_populate_all_graphic_levels()806 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in polaris10_populate_all_graphic_levels()807 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in polaris10_populate_all_graphic_levels()811 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask && in polaris10_populate_all_graphic_levels()812 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in polaris10_populate_all_graphic_levels()817 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask & in polaris10_populate_all_graphic_levels()938 hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask = in polaris10_populate_all_memory_levels()
430 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in tonga_populate_smc_link_level()645 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in tonga_populate_all_graphic_levels()658 if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask) in tonga_populate_all_graphic_levels()661 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in tonga_populate_all_graphic_levels()662 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in tonga_populate_all_graphic_levels()667 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && in tonga_populate_all_graphic_levels()668 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in tonga_populate_all_graphic_levels()674 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in tonga_populate_all_graphic_levels()1046 …data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table-… in tonga_populate_all_memory_levels()
625 data->dpm_level_enable_mask.pcie_dpm_enable_mask = in iceland_populate_smc_link_level()860 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in iceland_populate_all_graphic_levels()863 while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in iceland_populate_all_graphic_levels()868 while ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in iceland_populate_all_graphic_levels()874 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & in iceland_populate_all_graphic_levels()1255 …data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table-… in iceland_populate_all_memory_levels()