| /drivers/clk/ |
| D | clk-vt8500.c | 464 u32 mul; in wm8750_find_pll_bits() local
473 for (mul = 0; mul <= 255; mul++) { in wm8750_find_pll_bits()
474 tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2)); in wm8750_find_pll_bits()
481 *multiplier = mul; in wm8750_find_pll_bits()
489 *multiplier = mul; in wm8750_find_pll_bits()
512 u32 mul; in wm8850_find_pll_bits() local
521 for (mul = 0; mul <= 127; mul++) { in wm8850_find_pll_bits()
522 tclk = parent_rate * ((mul + 1) * 2) / in wm8850_find_pll_bits()
529 *multiplier = mul; in wm8850_find_pll_bits()
537 *multiplier = mul; in wm8850_find_pll_bits()
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| D | clk-cdce706.c | 76 unsigned mul; member
172 __func__, hwd->idx, hwd->mux, hwd->mul, hwd->div); in cdce706_pll_recalc_rate()
175 if (hwd->div && hwd->mul) { in cdce706_pll_recalc_rate()
176 u64 res = (u64)parent_rate * hwd->mul; in cdce706_pll_recalc_rate()
192 unsigned long mul, div; in cdce706_pll_round_rate() local
201 &mul, &div); in cdce706_pll_round_rate()
202 hwd->mul = mul; in cdce706_pll_round_rate()
207 __func__, hwd->idx, mul, div); in cdce706_pll_round_rate()
209 res = (u64)*parent_rate * hwd->mul; in cdce706_pll_round_rate()
218 unsigned long mul = hwd->mul, div = hwd->div; in cdce706_pll_set_rate() local
[all …]
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| D | clk-tango4.c | 24 u32 val, mul, div; in make_pll() local
28 mul = extract_pll_n(val) + 1; in make_pll()
30 clk_register_fixed_factor(NULL, name, parent, 0, mul, div); in make_pll()
38 u32 val, mul, div; in make_cd() local
42 mul = 1 << 27; in make_cd()
44 clk_register_fixed_factor(NULL, name, "pll2", 0, mul, div); in make_cd()
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| D | clk-nomadik.c | 227 u8 mul; in pll_clk_recalc_rate() local
230 mul = (val >> 8) & 0x3FU; in pll_clk_recalc_rate()
231 mul += 2; in pll_clk_recalc_rate()
233 return (parent_rate * mul) >> div; in pll_clk_recalc_rate()
237 u8 mul; in pll_clk_recalc_rate() local
239 mul = (val >> 24) & 0x3FU; in pll_clk_recalc_rate()
240 mul += 2; in pll_clk_recalc_rate()
241 return (parent_rate * mul); in pll_clk_recalc_rate()
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| D | clk-moxart.c | 24 unsigned int mul; in moxart_of_pll_clk_init() local
37 mul = readl(base + 0x30) >> 3 & 0x3f; in moxart_of_pll_clk_init()
46 hw = clk_hw_register_fixed_factor(NULL, name, parent_name, 0, mul, 1); in moxart_of_pll_clk_init()
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| /drivers/clk/tegra/ |
| D | clk-divider.c | 37 int mul; in get_div() local
42 mul = get_mul(divider); in get_div()
45 divider_ux1 *= mul; in get_div()
53 divider_ux1 *= mul; in get_div()
55 divider_ux1 -= mul; in get_div()
71 int div, mul; in clk_frac_div_recalc_rate() local
77 mul = get_mul(divider); in clk_frac_div_recalc_rate()
78 div += mul; in clk_frac_div_recalc_rate()
80 rate *= mul; in clk_frac_div_recalc_rate()
91 int div, mul; in clk_frac_div_round_rate() local
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| D | clk-periph-fixed.c | 67 rate = (unsigned long long)parent_rate * fixed->mul; in tegra_clk_periph_fixed_recalc_rate()
84 unsigned int mul, in tegra_clk_register_periph_fixed() argument
109 fixed->mul = mul; in tegra_clk_register_periph_fixed()
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| /drivers/clk/at91/ |
| D | clk-pll.c | 59 u16 mul; member
87 u16 mul; in clk_pll_prepare() local
91 mul = PLL_MUL(pllr, layout); in clk_pll_prepare()
95 (div == pll->div && mul == pll->mul)) in clk_pll_prepare()
108 ((pll->mul & layout->mul_mask) << layout->mul_shift)); in clk_pll_prepare()
136 u16 mul; in clk_pll_recalc_rate() local
142 mul = PLL_MUL(pllr, pll->layout); in clk_pll_recalc_rate()
144 if (!div || !mul) in clk_pll_recalc_rate()
147 return (parent_rate / div) * (mul + 1); in clk_pll_recalc_rate()
152 u32 *div, u32 *mul, in clk_pll_get_best_div_mul() argument
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| /drivers/cpufreq/ |
| D | cpufreq-nforce2.c | 25 #define NFORCE2_PLL(mul, div) (0x100000 | (mul << 8) | div) argument
69 unsigned char mul, div; in nforce2_calc_fsb() local
71 mul = (pll >> 8) & 0xff; in nforce2_calc_fsb()
75 return NFORCE2_XTAL * mul / div; in nforce2_calc_fsb()
89 unsigned char mul = 0, div = 0; in nforce2_calc_pll() local
93 while (((mul == 0) || (div == 0)) && (tried <= 3)) { in nforce2_calc_pll()
98 mul = xmul; in nforce2_calc_pll()
104 if ((mul == 0) || (div == 0)) in nforce2_calc_pll()
107 return NFORCE2_PLL(mul, div); in nforce2_calc_pll()
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| /drivers/pwm/ |
| D | pwm-img.c | 92 unsigned long mul, output_clk_hz, input_clk_hz; in img_pwm_config() local
105 mul = DIV_ROUND_UP(input_clk_hz, output_clk_hz); in img_pwm_config()
106 if (mul <= max_timebase) { in img_pwm_config()
108 timebase = DIV_ROUND_UP(mul, 1); in img_pwm_config()
109 } else if (mul <= max_timebase * 8) { in img_pwm_config()
111 timebase = DIV_ROUND_UP(mul, 8); in img_pwm_config()
112 } else if (mul <= max_timebase * 64) { in img_pwm_config()
114 timebase = DIV_ROUND_UP(mul, 64); in img_pwm_config()
115 } else if (mul <= max_timebase * 512) { in img_pwm_config()
117 timebase = DIV_ROUND_UP(mul, 512); in img_pwm_config()
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| /drivers/net/wireless/ath/ath9k/ |
| D | common.h | 39 #define ATH_EP_MUL(x, mul) ((x) * (mul)) argument
47 #define ATH_EP_RND(x, mul) \ argument
48 (((x) + ((mul)/2)) / (mul))
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| /drivers/media/i2c/ |
| D | smiapp-pll.c | 162 struct smiapp_pll *pll, struct smiapp_pll_branch *op_pll, uint32_t mul, in __smiapp_pll_calculate() argument
187 more_mul_max = limits->max_pll_multiplier / mul; in __smiapp_pll_calculate()
195 / (pll->ext_clk_freq_hz / pll->pre_pll_clk_div * mul)); in __smiapp_pll_calculate()
206 DIV_ROUND_UP(limits->max_pll_multiplier, mul)); in __smiapp_pll_calculate()
213 * mul); in __smiapp_pll_calculate()
218 DIV_ROUND_UP(limits->min_pll_multiplier, mul)); in __smiapp_pll_calculate()
243 pll->pll_multiplier = mul * i; in __smiapp_pll_calculate()
403 uint32_t mul, div; in smiapp_pll_calculate() local
457 mul = div_u64(pll->pll_op_clk_freq_hz, i); in smiapp_pll_calculate()
459 dev_dbg(dev, "mul %u / div %u\n", mul, div); in smiapp_pll_calculate()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_afmt.c | 54 unsigned long div, mul; in amdgpu_afmt_calc_cts() local
70 mul = ((128*freq/1000) + (n-1))/n; in amdgpu_afmt_calc_cts()
72 n *= mul; in amdgpu_afmt_calc_cts()
73 cts *= mul; in amdgpu_afmt_calc_cts()
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| /drivers/gpu/drm/tegra/ |
| D | dsi.c | 44 unsigned int mul; member
502 unsigned int hact, hsw, hbp, hfp, i, mul, div; in tegra_dsi_configure() local
513 mul = state->mul; in tegra_dsi_configure()
560 hact = mode->hdisplay * mul / div; in tegra_dsi_configure()
563 hsw = (mode->hsync_end - mode->hsync_start) * mul / div; in tegra_dsi_configure()
566 hbp = (mode->htotal - mode->hsync_end) * mul / div; in tegra_dsi_configure()
572 hfp = (mode->hsync_start - mode->hdisplay) * mul / div; in tegra_dsi_configure()
585 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY); in tegra_dsi_configure()
595 bytes = 1 + (mode->hdisplay / 2) * mul / div; in tegra_dsi_configure()
598 bytes = 1 + mode->hdisplay * mul / div; in tegra_dsi_configure()
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| /drivers/media/radio/si4713/ |
| D | si4713.c | 940 s32 *bit, s32 *mask, u16 *property, int *mul, in si4713_choose_econtrol_action() argument
949 *mul = 1; in si4713_choose_econtrol_action()
953 *mul = 1; in si4713_choose_econtrol_action()
957 *mul = 1; in si4713_choose_econtrol_action()
961 *mul = 1; in si4713_choose_econtrol_action()
965 *mul = ATTACK_TIME_UNIT; in si4713_choose_econtrol_action()
969 *mul = 10; in si4713_choose_econtrol_action()
973 *mul = 10; in si4713_choose_econtrol_action()
977 *mul = 1; in si4713_choose_econtrol_action()
1124 int mul = 0; in si4713_s_ctrl() local
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| /drivers/usb/gadget/udc/bdc/ |
| D | bdc_cmd.c | 144 u32 mps, mbs, mul, si; in bdc_config_ep() local
149 cmd_sc = mul = mbs = param2 = 0; in bdc_config_ep()
171 mul = comp_desc->bmAttributes; in bdc_config_ep()
174 param2 |= mul << EPM_SHIFT; in bdc_config_ep()
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| /drivers/ata/ |
| D | pata_at91.c | 190 unsigned long mul; in calc_mck_cycles() local
199 mul = (mck_hz / 10000) << 16; in calc_mck_cycles()
200 mul /= 100000; in calc_mck_cycles()
202 return (ns * mul + 65536) >> 16; /* rounding */ in calc_mck_cycles()
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| /drivers/clk/h8300/ |
| D | clk-h8s2678.c | 30 int mul = 1 << (readb(pll_clock->pllcr) & 3); in pll_recalc_rate() local
32 return parent_rate * mul; in pll_recalc_rate()
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| /drivers/net/wireless/intersil/p54/ |
| D | eeprom.h | 98 __le16 mul; member
103 __le16 mul; member
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| /drivers/usb/core/ |
| D | devices.c | 314 int mul; in usb_dump_config_descriptor() local
319 mul = 8; in usb_dump_config_descriptor()
321 mul = 2; in usb_dump_config_descriptor()
328 desc->bMaxPower * mul); in usb_dump_config_descriptor()
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| D | usb.h | 48 unsigned mul = (udev->speed >= USB_SPEED_SUPER ? 8 : 2); in usb_get_max_power() local
50 return c->desc.bMaxPower * mul; in usb_get_max_power()
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| /drivers/tty/serial/8250/ |
| D | 8250_mid.c | 169 unsigned long mul, div; in mid8250_set_termios() local
186 rational_best_approximation(fuart, mid->board->freq, w, w, &mul, &div); in mid8250_set_termios()
190 writel(mul, p->membase + INTEL_MID_UART_MUL); /* set MUL */ in mid8250_set_termios()
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| /drivers/gpu/drm/i915/ |
| D | intel_panel.c | 1262 u32 mul; in spt_hz_to_pwm() local
1265 mul = 128; in spt_hz_to_pwm()
1267 mul = 16; in spt_hz_to_pwm()
1269 return DIV_ROUND_CLOSEST(MHz(24), pwm_freq_hz * mul); in spt_hz_to_pwm()
1281 u32 mul, clock; in lpt_hz_to_pwm() local
1284 mul = 16; in lpt_hz_to_pwm()
1286 mul = 128; in lpt_hz_to_pwm()
1293 return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * mul); in lpt_hz_to_pwm()
1355 int mul, clock; in vlv_hz_to_pwm() local
1362 mul = 16; in vlv_hz_to_pwm()
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| /drivers/clk/microchip/ |
| D | clk-core.c | 608 u32 mul, div, best_mul = 1, best_div = 1; in spll_calc_mult_div() local
615 for (mul = 1; mul <= PLL_MULT_MAX; mul++) { in spll_calc_mult_div()
618 rate64 *= mul; in spll_calc_mult_div()
625 best_mul = mul; in spll_calc_mult_div()
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| /drivers/spi/ |
| D | spi-pxa2xx.c | 839 u32 mul; in quark_x1000_get_clk_div() local
844 mul = (1 << 24) >> 1; in quark_x1000_get_clk_div()
855 mul >>= scale - 9; in quark_x1000_get_clk_div()
865 mul >>= scale; in quark_x1000_get_clk_div()
868 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); in quark_x1000_get_clk_div()
888 mul = (1 << 24) * 2 / 5; in quark_x1000_get_clk_div()
909 mul = m; in quark_x1000_get_clk_div()
913 *dds = mul; in quark_x1000_get_clk_div()
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