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Searched refs:performance_level_count (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/radeon/
Dni_dpm.c807 for (i = 0; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()
824 ps->performance_levels[ps->performance_level_count - 1].mclk; in ni_apply_state_adjust_rules()
826 ps->performance_levels[ps->performance_level_count - 1].vddci; in ni_apply_state_adjust_rules()
833 for (i = 1; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()
844 for (i = 1; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()
850 for (i = 0; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()
855 for (i = 1; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()
863 for (i = 1; i < ps->performance_level_count; i++) in ni_apply_state_adjust_rules()
868 for (i = 0; i < ps->performance_level_count; i++) in ni_apply_state_adjust_rules()
872 for (i = 0; i < ps->performance_level_count; i++) { in ni_apply_state_adjust_rules()
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Dsi_dpm.c2307 if (state->performance_level_count == 0) in si_populate_power_containment_values()
2310 if (smc_state->levelCount != state->performance_level_count) in si_populate_power_containment_values()
2321 for (i = 1; i < state->performance_level_count; i++) { in si_populate_power_containment_values()
2389 if (state->performance_level_count == 0) in si_populate_sq_ramping_values()
2392 if (smc_state->levelCount != state->performance_level_count) in si_populate_sq_ramping_values()
2413 for (i = 0; i < state->performance_level_count; i++) { in si_populate_sq_ramping_values()
3085 for (i = ps->performance_level_count - 2; i >= 0; i--) { in si_apply_state_adjust_rules()
3090 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3110 for (i = 0; i < ps->performance_level_count; i++) { in si_apply_state_adjust_rules()
3136 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in si_apply_state_adjust_rules()
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Dni_dpm.h173 u16 performance_level_count; member
Dci_dpm.h46 u16 performance_level_count; member
Dci_dpm.c833 for (i = 0; i < ps->performance_level_count; i++) { in ci_apply_state_adjust_rules()
844 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in ci_apply_state_adjust_rules()
3738 if (state->performance_level_count < 1) in ci_trim_dpm_states()
3741 if (state->performance_level_count == 1) in ci_trim_dpm_states()
3843 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; in ci_find_dpm_states_clocks_in_dpm_table()
3845 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; in ci_find_dpm_states_clocks_in_dpm_table()
3884 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()
3885 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()
4786 for (i = 0; i < state->performance_level_count; i++) { in ci_get_maximum_link_speed()
5462 ps->performance_level_count = index + 1; in ci_parse_pplib_clock_info()
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/drivers/gpu/drm/amd/powerplay/hwmgr/
Dsmu7_hwmgr.c2523 PP_ASSERT_WITH_CODE(smu7_ps->performance_level_count == 2, in smu7_apply_state_adjust_rules()
2533 for (i = 0; i < smu7_ps->performance_level_count; i++) { in smu7_apply_state_adjust_rules()
2620 [smu7_ps->performance_level_count - 1].memory_clock; in smu7_apply_state_adjust_rules()
2654 for (i = 0; i < smu7_ps->performance_level_count; i++) { in smu7_apply_state_adjust_rules()
2684 [smu7_ps->performance_level_count-1].memory_clock; in smu7_dpm_get_mclk()
2706 [smu7_ps->performance_level_count-1].engine_clock; in smu7_dpm_get_sclk()
2821 [smu7_power_state->performance_level_count++]); in smu7_get_pp_table_entry_callback_func_v1()
2824 …(smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS… in smu7_get_pp_table_entry_callback_func_v1()
2829 (smu7_power_state->performance_level_count <= in smu7_get_pp_table_entry_callback_func_v1()
2849 [smu7_power_state->performance_level_count++]); in smu7_get_pp_table_entry_callback_func_v1()
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Dsmu7_hwmgr.h87 uint16_t performance_level_count; member
/drivers/gpu/drm/amd/amdgpu/
Dsi_dpm.c2402 if (state->performance_level_count == 0) in si_populate_power_containment_values()
2405 if (smc_state->levelCount != state->performance_level_count) in si_populate_power_containment_values()
2416 for (i = 1; i < state->performance_level_count; i++) { in si_populate_power_containment_values()
2483 if (state->performance_level_count == 0) in si_populate_sq_ramping_values()
2486 if (smc_state->levelCount != state->performance_level_count) in si_populate_sq_ramping_values()
2507 for (i = 0; i < state->performance_level_count; i++) { in si_populate_sq_ramping_values()
3199 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= in ni_set_uvd_clock_before_set_eng_clock()
3200 current_state->performance_levels[current_state->performance_level_count - 1].sclk) in ni_set_uvd_clock_before_set_eng_clock()
3217 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < in ni_set_uvd_clock_after_set_eng_clock()
3218 current_state->performance_levels[current_state->performance_level_count - 1].sclk) in ni_set_uvd_clock_after_set_eng_clock()
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Dci_dpm.h47 u16 performance_level_count; member
Dci_dpm.c951 for (i = 0; i < ps->performance_level_count; i++) { in ci_apply_state_adjust_rules()
962 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in ci_apply_state_adjust_rules()
3875 if (state->performance_level_count < 1) in ci_trim_dpm_states()
3878 if (state->performance_level_count == 1) in ci_trim_dpm_states()
3982 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; in ci_find_dpm_states_clocks_in_dpm_table()
3984 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; in ci_find_dpm_states_clocks_in_dpm_table()
4020 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()
4021 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk; in ci_populate_and_upload_sclk_mclk_dpm_levels()
4933 for (i = 0; i < state->performance_level_count; i++) { in ci_get_maximum_link_speed()
5562 ps->performance_level_count = index + 1; in ci_parse_pplib_clock_info()
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Dsi_dpm.h615 u16 performance_level_count; member