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Searched refs:reg_off (Results 1 – 23 of 23) sorted by relevance

/drivers/clk/meson/
Dclk-pll.c60 reg = readl(pll->base + p->reg_off); in meson_clk_pll_recalc_rate()
64 reg = readl(pll->base + p->reg_off); in meson_clk_pll_recalc_rate()
68 reg = readl(pll->base + p->reg_off); in meson_clk_pll_recalc_rate()
73 reg = readl(pll->base + p->reg_off); in meson_clk_pll_recalc_rate()
79 reg = readl(pll->base + p->reg_off); in meson_clk_pll_recalc_rate()
126 reg = readl(pll->base + p_n->reg_off); in meson_clk_pll_wait_lock()
156 reg = readl(pll->base + p->reg_off); in meson_clk_pll_set_rate()
157 writel(reg | MESON_PLL_RESET, pll->base + p->reg_off); in meson_clk_pll_set_rate()
160 writel(reg, pll->base + p->reg_off); in meson_clk_pll_set_rate()
163 reg = readl(pll->base + p->reg_off); in meson_clk_pll_set_rate()
[all …]
Dclk-cpu.c82 reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL1); in meson_clk_cpu_set_rate()
84 writel(reg, clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL1); in meson_clk_cpu_set_rate()
86 reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL); in meson_clk_cpu_set_rate()
88 writel(reg, clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL); in meson_clk_cpu_set_rate()
101 reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL1); in meson_clk_cpu_recalc_rate()
104 reg = readl(clk_cpu->base + clk_cpu->reg_off + MESON_CPU_CLK_CNTL); in meson_clk_cpu_recalc_rate()
122 cpu_clk_cntl = readl(clk_cpu->base + clk_cpu->reg_off in meson_clk_cpu_pre_rate_change()
125 writel(cpu_clk_cntl, clk_cpu->base + clk_cpu->reg_off in meson_clk_cpu_pre_rate_change()
131 writel(cpu_clk_cntl, clk_cpu->base + clk_cpu->reg_off in meson_clk_cpu_pre_rate_change()
144 cpu_clk_cntl = readl(clk_cpu->base + clk_cpu->reg_off in meson_clk_cpu_post_rate_change()
[all …]
Dgxbb.c267 .reg_off = HHI_MPLL_CNTL,
272 .reg_off = HHI_MPLL_CNTL,
277 .reg_off = HHI_MPLL_CNTL,
293 .reg_off = HHI_HDMI_PLL_CNTL,
298 .reg_off = HHI_HDMI_PLL_CNTL,
303 .reg_off = HHI_HDMI_PLL_CNTL2,
308 .reg_off = HHI_HDMI_PLL_CNTL2,
313 .reg_off = HHI_HDMI_PLL_CNTL2,
329 .reg_off = HHI_SYS_PLL_CNTL,
334 .reg_off = HHI_SYS_PLL_CNTL,
[all …]
Dmeson8b.c116 .reg_off = HHI_MPLL_CNTL,
121 .reg_off = HHI_MPLL_CNTL,
126 .reg_off = HHI_MPLL_CNTL,
142 .reg_off = HHI_VID_PLL_CNTL,
147 .reg_off = HHI_VID_PLL_CNTL,
152 .reg_off = HHI_VID_PLL_CNTL,
168 .reg_off = HHI_SYS_PLL_CNTL,
173 .reg_off = HHI_SYS_PLL_CNTL,
178 .reg_off = HHI_SYS_PLL_CNTL,
255 .reg_off = HHI_SYS_CPU_CLK_CNTL1,
Dclk-mpll.c80 reg = readl(mpll->base + p->reg_off); in mpll_recalc_rate()
84 reg = readl(mpll->base + p->reg_off); in mpll_recalc_rate()
Dclkc.h33 u16 reg_off; member
83 u16 reg_off; member
/drivers/pinctrl/
Dpinctrl-digicolor.c134 int bit_off, reg_off; in dc_set_mux() local
137 dc_client_sel(group, &reg_off, &bit_off); in dc_set_mux()
139 reg = readb_relaxed(pmap->regs + reg_off); in dc_set_mux()
142 writeb_relaxed(reg, pmap->regs + reg_off); in dc_set_mux()
152 int bit_off, reg_off; in dc_pmx_request_gpio() local
155 dc_client_sel(offset, &reg_off, &bit_off); in dc_pmx_request_gpio()
157 reg = readb_relaxed(pmap->regs + reg_off); in dc_pmx_request_gpio()
175 int reg_off = GP_DRIVE0(gpio/PINS_PER_COLLECTION); in dc_gpio_direction_input() local
181 drive = readb_relaxed(pmap->regs + reg_off); in dc_gpio_direction_input()
183 writeb_relaxed(drive, pmap->regs + reg_off); in dc_gpio_direction_input()
[all …]
/drivers/net/ethernet/cavium/liquidio/
Docteon_device.h608 #define octeon_write_csr(oct_dev, reg_off, value) \ argument
609 writel(value, oct_dev->mmio[0].hw_addr + reg_off)
611 #define octeon_write_csr64(oct_dev, reg_off, val64) \ argument
612 writeq(val64, oct_dev->mmio[0].hw_addr + reg_off)
614 #define octeon_read_csr(oct_dev, reg_off) \ argument
615 readl(oct_dev->mmio[0].hw_addr + reg_off)
617 #define octeon_read_csr64(oct_dev, reg_off) \ argument
618 readq(oct_dev->mmio[0].hw_addr + reg_off)
/drivers/pinctrl/spear/
Dpinctrl-plgpio.c83 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in is_plgpio_set() local
84 u32 val = readl_relaxed(reg_off); in is_plgpio_set()
92 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in plgpio_reg_set() local
93 u32 val = readl_relaxed(reg_off); in plgpio_reg_set()
95 writel_relaxed(val | (1 << offset), reg_off); in plgpio_reg_set()
101 void __iomem *reg_off = REG_OFFSET(base, reg, pin); in plgpio_reg_reset() local
102 u32 val = readl_relaxed(reg_off); in plgpio_reg_reset()
104 writel_relaxed(val & ~(1 << offset), reg_off); in plgpio_reg_reset()
323 void __iomem *reg_off; in plgpio_irq_set_type() local
340 reg_off = REG_OFFSET(plgpio->base, plgpio->regs.eit, offset); in plgpio_irq_set_type()
[all …]
/drivers/mtd/nand/
Dqcom_nandc.c460 int reg_off, const void *vaddr, int size, in prep_dma_desc() argument
497 slave_conf.src_addr = nandc->base_dma + reg_off; in prep_dma_desc()
501 slave_conf.dst_addr = nandc->base_dma + reg_off; in prep_dma_desc()
592 static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off, in read_data_dma() argument
595 return prep_dma_desc(nandc, true, reg_off, vaddr, size, false); in read_data_dma()
606 static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off, in write_data_dma() argument
609 return prep_dma_desc(nandc, false, reg_off, vaddr, size, false); in write_data_dma()
1238 int reg_off = FLASH_BUF_ACC; in qcom_nandc_read_page_raw() local
1255 read_data_dma(nandc, reg_off, data_buf, data_size1); in qcom_nandc_read_page_raw()
1256 reg_off += data_size1; in qcom_nandc_read_page_raw()
[all …]
/drivers/staging/vt6656/
Dusbpipe.c78 void vnt_control_out_u8(struct vnt_private *priv, u8 reg, u8 reg_off, u8 data) in vnt_control_out_u8() argument
81 reg_off, reg, sizeof(u8), &data); in vnt_control_out_u8()
119 void vnt_control_in_u8(struct vnt_private *priv, u8 reg, u8 reg_off, u8 *data) in vnt_control_in_u8() argument
122 reg_off, reg, sizeof(u8), data); in vnt_control_in_u8()
/drivers/rtc/
Drtc-sh.c454 static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off) in sh_rtc_read_alarm_value() argument
459 byte = readb(rtc->regbase + reg_off); in sh_rtc_read_alarm_value()
493 int value, int reg_off) in sh_rtc_write_alarm_value() argument
497 writeb(0, rtc->regbase + reg_off); in sh_rtc_write_alarm_value()
499 writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off); in sh_rtc_write_alarm_value()
/drivers/lguest/x86/
Dcore.c185 unsigned long *lguest_arch_regptr(struct lg_cpu *cpu, size_t reg_off, bool any) in lguest_arch_regptr() argument
187 switch (reg_off) { in lguest_arch_regptr()
210 switch (reg_off) { in lguest_arch_regptr()
/drivers/mmc/host/
Dsunxi-mmc.c684 static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off) in sunxi_mmc_calibrate() argument
686 u32 reg = readl(host->reg_base + reg_off); in sunxi_mmc_calibrate()
696 writel(reg | SDXC_CAL_START, host->reg_base + reg_off); in sunxi_mmc_calibrate()
702 while (!((reg = readl(host->reg_base + reg_off)) & SDXC_CAL_DONE)) { in sunxi_mmc_calibrate()
707 writel(reg, host->reg_base + reg_off); in sunxi_mmc_calibrate()
718 writel(reg, host->reg_base + reg_off); in sunxi_mmc_calibrate()
/drivers/thermal/samsung/
Dexynos_tmu.c677 unsigned int reg_off, bit_off; in exynos7_tmu_initialize() local
715 reg_off = ((7 - i) / 2) * 4; in exynos7_tmu_initialize()
727 EXYNOS7_THD_TEMP_RISE7_6 + reg_off); in exynos7_tmu_initialize()
731 data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); in exynos7_tmu_initialize()
738 data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); in exynos7_tmu_initialize()
/drivers/lguest/
Dlg.h211 unsigned long *lguest_arch_regptr(struct lg_cpu *cpu, size_t reg_off, bool any);
/drivers/thermal/tegra/
Dsoctherm.c484 u32 r, reg_off; in throttrip_program() local
493 reg_off = THERMCTL_LVL_REG(sg->thermctl_lvl0_offset, throt + 1); in throttrip_program()
507 r = readl(ts->regs + reg_off); in throttrip_program()
513 writel(r, ts->regs + reg_off); in throttrip_program()
/drivers/scsi/bnx2i/
Dbnx2i_hwi.c2732 u32 reg_off; in bnx2i_map_ep_dbell_regs() local
2743 reg_off = (1 << BNX2X_DB_SHIFT) * (cid_num & 0x1FFFF); in bnx2i_map_ep_dbell_regs()
2744 ep->qp.ctx_base = ioremap_nocache(reg_base + reg_off, 4); in bnx2i_map_ep_dbell_regs()
2754 reg_off = CTX_OFFSET + MAX_CID_CNT * MB_KERNEL_CTX_SIZE in bnx2i_map_ep_dbell_regs()
2758 reg_off = CTX_OFFSET + (MB_KERNEL_CTX_SIZE * cid_num); in bnx2i_map_ep_dbell_regs()
2761 reg_off = CTX_OFFSET + (MB_KERNEL_CTX_SIZE * cid_num); in bnx2i_map_ep_dbell_regs()
2763 ep->qp.ctx_base = ioremap_nocache(ep->hba->reg_base + reg_off, in bnx2i_map_ep_dbell_regs()
/drivers/net/ethernet/amazon/ena/
Dena_admin_defs.h879 u16 reg_off; member
Dena_com.c640 read_resp->reg_off); in ena_com_reg_bar_read32()
645 if (read_resp->reg_off != offset) { in ena_com_reg_bar_read32()
/drivers/scsi/bnx2fc/
Dbnx2fc_hwi.c1418 u32 reg_off; in bnx2fc_map_doorbell() local
1425 reg_off = (1 << BNX2X_DB_SHIFT) * (context_id & 0x1FFFF); in bnx2fc_map_doorbell()
1426 tgt->ctx_base = ioremap_nocache(reg_base + reg_off, 4); in bnx2fc_map_doorbell()
/drivers/scsi/
Dadvansys.c1895 #define AdvReadByteRegister(iop_base, reg_off) \ argument
1896 (ADV_MEM_READB((iop_base) + (reg_off)))
1899 #define AdvWriteByteRegister(iop_base, reg_off, byte) \ argument
1900 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1903 #define AdvReadWordRegister(iop_base, reg_off) \ argument
1904 (ADV_MEM_READW((iop_base) + (reg_off)))
1907 #define AdvWriteWordRegister(iop_base, reg_off, word) \ argument
1908 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
1911 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \ argument
1912 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
/drivers/iommu/
Darm-smmu-v3.c2092 unsigned int reg_off, unsigned int ack_off) in arm_smmu_write_reg_sync() argument
2096 writel_relaxed(val, smmu->base + reg_off); in arm_smmu_write_reg_sync()