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Searched refs:wr_regl (Results 1 – 6 of 6) sorted by relevance

/drivers/tty/serial/
Dsirfsoc_uart.c111 wr_regl(port, ureg->sirfsoc_line_ctrl, in sirfsoc_uart_set_mctrl()
115 wr_regl(port, ureg->sirfsoc_mode1, in sirfsoc_uart_set_mctrl()
120 wr_regl(port, ureg->sirfsoc_line_ctrl, in sirfsoc_uart_set_mctrl()
124 wr_regl(port, ureg->sirfsoc_mode1, in sirfsoc_uart_set_mctrl()
134 wr_regl(port, ureg->sirfsoc_afc_ctrl, val); in sirfsoc_uart_set_mctrl()
155 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_stop_tx()
159 wr_regl(port, ureg->sirfsoc_int_en_clr_reg, in sirfsoc_uart_stop_tx()
164 wr_regl(port, ureg->sirfsoc_tx_rx_en, rd_regl(port, in sirfsoc_uart_stop_tx()
167 wr_regl(port, ureg->sirfsoc_int_en_reg, in sirfsoc_uart_stop_tx()
171 wr_regl(port, ureg->sirfsoc_int_en_clr_reg, in sirfsoc_uart_stop_tx()
[all …]
Dsamsung.c135 wr_regl(port, S3C2410_UFCON, ufcon); in s3c24xx_serial_rx_enable()
139 wr_regl(port, S3C2410_UCON, ucon); in s3c24xx_serial_rx_enable()
154 wr_regl(port, S3C2410_UCON, ucon); in s3c24xx_serial_rx_disable()
247 wr_regl(port, S3C2410_UCON, ucon); in enable_tx_dma()
260 wr_regl(port, S3C2410_UFCON, ufcon); in enable_tx_pio()
266 wr_regl(port, S3C2410_UCON, ucon); in enable_tx_pio()
523 wr_regl(port, S3C2410_UCON, ucon); in enable_rx_dma()
543 wr_regl(port, S3C2410_UCON, ucon); in enable_rx_pio()
590 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT); in s3c24xx_serial_rx_chars_dma()
633 wr_regl(port, S3C2410_UFCON, ufcon); in s3c24xx_serial_rx_drain_fifo()
[all …]
Dsamsung.h124 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg)) macro
137 wr_regl(port, reg, val); in s3c24xx_set_bit()
150 wr_regl(port, reg, val); in s3c24xx_clear_bit()
Dsirfsoc_uart.h442 #define wr_regl(port, reg, val) __raw_writel(val, portaddr(port, reg)) macro
/drivers/atm/
Dhorizon.c370 static inline void wr_regl (const hrz_dev * dev, unsigned char reg, u32 data) { in wr_regl() function
399 wr_regl (dev, MEM_WR_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW)); in wr_mem()
400 wr_regl (dev, MEMORY_PORT_OFF, data); in wr_mem()
405 wr_regl (dev, MEM_RD_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW)); in rd_mem()
410 wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr | 0x80000000); in wr_framer()
411 wr_regl (dev, MEMORY_PORT_OFF, data); in wr_framer()
415 wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr | 0x80000000); in rd_framer()
448 wr_regl (dev, TX_CHANNEL_PORT_OFF, tx_channel); in SELECT_TX_CHANNEL()
950 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0); in rx_schedule()
1033 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0); in rx_schedule()
[all …]
Dhorizon.h493 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | GREEN_LED)
495 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ GREEN_LED)
497 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | YELLOW_LED)
499 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ YELLOW_LED)