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1* ARM SMMUv3 Architecture Implementation
2
3The SMMUv3 architecture is a significant departure from previous
4revisions, replacing the MMIO register interface with in-memory command
5and event queues and adding support for the ATS and PRI components of
6the PCIe specification.
7
8** SMMUv3 required properties:
9
10- compatible        : Should include:
11
12                      * "arm,smmu-v3" for any SMMUv3 compliant
13                        implementation. This entry should be last in the
14                        compatible list.
15
16- reg               : Base address and size of the SMMU.
17
18- interrupts        : Non-secure interrupt list describing the wired
19                      interrupt sources corresponding to entries in
20                      interrupt-names. If no wired interrupts are
21                      present then this property may be omitted.
22
23- interrupt-names   : When the interrupts property is present, should
24                      include the following:
25                      * "eventq"    - Event Queue not empty
26                      * "priq"      - PRI Queue not empty
27                      * "cmdq-sync" - CMD_SYNC complete
28                      * "gerror"    - Global Error activated
29
30- #iommu-cells      : See the generic IOMMU binding described in
31                        devicetree/bindings/pci/pci-iommu.txt
32                      for details. For SMMUv3, must be 1, with each cell
33                      describing a single stream ID. All possible stream
34                      IDs which a device may emit must be described.
35
36** SMMUv3 optional properties:
37
38- dma-coherent      : Present if DMA operations made by the SMMU (page
39                      table walks, stream table accesses etc) are cache
40                      coherent with the CPU.
41
42                      NOTE: this only applies to the SMMU itself, not
43                      masters connected upstream of the SMMU.
44
45- msi-parent        : See the generic MSI binding described in
46                        devicetree/bindings/interrupt-controller/msi.txt
47                      for a description of the msi-parent property.
48
49- hisilicon,broken-prefetch-cmd
50                    : Avoid sending CMD_PREFETCH_* commands to the SMMU.
51
52** Example
53
54        smmu@2b400000 {
55                compatible = "arm,smmu-v3";
56                reg = <0x0 0x2b400000 0x0 0x20000>;
57                interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
58                             <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
59                             <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
60                             <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
61                interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";
62                dma-coherent;
63                #iommu-cells = <1>;
64                msi-parent = <&its 0xff0000>;
65        };
66