1* Mediatek Universal Asynchronous Receiver/Transmitter (UART) 2 3Required properties: 4- compatible should contain: 5 * "mediatek,mt2701-uart" for MT2701 compatible UARTS 6 * "mediatek,mt6580-uart" for MT6580 compatible UARTS 7 * "mediatek,mt6582-uart" for MT6582 compatible UARTS 8 * "mediatek,mt6589-uart" for MT6589 compatible UARTS 9 * "mediatek,mt6755-uart" for MT6755 compatible UARTS 10 * "mediatek,mt6795-uart" for MT6795 compatible UARTS 11 * "mediatek,mt7623-uart" for MT7623 compatible UARTS 12 * "mediatek,mt8127-uart" for MT8127 compatible UARTS 13 * "mediatek,mt8135-uart" for MT8135 compatible UARTS 14 * "mediatek,mt8173-uart" for MT8173 compatible UARTS 15 * "mediatek,mt6577-uart" for MT6577 and all of the above 16 17- reg: The base address of the UART register bank. 18 19- interrupts: A single interrupt specifier. 20 21- clocks : Must contain an entry for each entry in clock-names. 22 See ../clocks/clock-bindings.txt for details. 23- clock-names: 24 - "baud": The clock the baudrate is derived from 25 - "bus": The bus clock for register accesses (optional) 26 27For compatibility with older device trees an unnamed clock is used for the 28baud clock if the baudclk does not exist. Do not use this for new designs. 29 30Example: 31 32 uart0: serial@11006000 { 33 compatible = "mediatek,mt6589-uart", "mediatek,mt6577-uart"; 34 reg = <0x11006000 0x400>; 35 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; 36 clocks = <&uart_clk>, <&bus_clk>; 37 clock-names = "baud", "bus"; 38 }; 39