1/* 2 * Copyright 2014 Linaro Ltd 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 23/dts-v1/; 24#include <dt-bindings/interrupt-controller/irq.h> 25#include <dt-bindings/gpio/gpio.h> 26#include "skeleton.dtsi" 27 28/ { 29 model = "ARM RealView PB1176"; 30 compatible = "arm,realview-pb1176"; 31 32 chosen { }; 33 34 aliases { 35 serial0 = &pb1176_serial0; 36 serial1 = &pb1176_serial1; 37 serial2 = &pb1176_serial2; 38 serial3 = &pb1176_serial3; 39 serial4 = &fpga_serial; 40 }; 41 42 memory { 43 /* 128 MiB memory @ 0x0 */ 44 reg = <0x00000000 0x08000000>; 45 }; 46 47 /* The voltage to the MMC card is hardwired at 3.3V */ 48 vmmc: fixedregulator@0 { 49 compatible = "regulator-fixed"; 50 regulator-name = "vmmc"; 51 regulator-min-microvolt = <3300000>; 52 regulator-max-microvolt = <3300000>; 53 regulator-boot-on; 54 }; 55 56 veth: fixedregulator@0 { 57 compatible = "regulator-fixed"; 58 regulator-name = "veth"; 59 regulator-min-microvolt = <3300000>; 60 regulator-max-microvolt = <3300000>; 61 regulator-boot-on; 62 }; 63 64 xtal24mhz: xtal24mhz@24M { 65 #clock-cells = <0>; 66 compatible = "fixed-clock"; 67 clock-frequency = <24000000>; 68 }; 69 70 timclk: timclk@1M { 71 #clock-cells = <0>; 72 compatible = "fixed-factor-clock"; 73 clock-div = <24>; 74 clock-mult = <1>; 75 clocks = <&xtal24mhz>; 76 }; 77 78 mclk: mclk@24M { 79 #clock-cells = <0>; 80 compatible = "fixed-factor-clock"; 81 clock-div = <1>; 82 clock-mult = <1>; 83 clocks = <&xtal24mhz>; 84 }; 85 86 kmiclk: kmiclk@24M { 87 #clock-cells = <0>; 88 compatible = "fixed-factor-clock"; 89 clock-div = <1>; 90 clock-mult = <1>; 91 clocks = <&xtal24mhz>; 92 }; 93 94 sspclk: sspclk@24M { 95 #clock-cells = <0>; 96 compatible = "fixed-factor-clock"; 97 clock-div = <1>; 98 clock-mult = <1>; 99 clocks = <&xtal24mhz>; 100 }; 101 102 uartclk: uartclk@24M { 103 #clock-cells = <0>; 104 compatible = "fixed-factor-clock"; 105 clock-div = <1>; 106 clock-mult = <1>; 107 clocks = <&xtal24mhz>; 108 }; 109 110 /* FIXME: this actually hangs off the PLL clocks */ 111 pclk: pclk@0 { 112 #clock-cells = <0>; 113 compatible = "fixed-clock"; 114 clock-frequency = <0>; 115 }; 116 117 flash@30000000 { 118 compatible = "arm,versatile-flash", "cfi-flash"; 119 reg = <0x30000000 0x4000000>; 120 bank-width = <4>; 121 }; 122 123 fpga_flash@38000000 { 124 compatible = "arm,versatile-flash", "cfi-flash"; 125 reg = <0x38000000 0x800000>; 126 bank-width = <4>; 127 }; 128 129 /* 130 * The "secure flash" contains things like the boot 131 * monitor so we don't want people to accidentally 132 * screw this up. Mark the device tree node disabled 133 * by default. 134 */ 135 secflash@3c000000 { 136 compatible = "arm,versatile-flash", "cfi-flash"; 137 reg = <0x3c000000 0x4000000>; 138 bank-width = <4>; 139 status = "disabled"; 140 }; 141 142 /* SMSC 9118 ethernet with PHY and EEPROM */ 143 ethernet@3a000000 { 144 compatible = "smsc,lan9118", "smsc,lan9115"; 145 reg = <0x3a000000 0x10000>; 146 interrupt-parent = <&intc_fpga1176>; 147 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 148 phy-mode = "mii"; 149 reg-io-width = <4>; 150 smsc,irq-active-high; 151 smsc,irq-push-pull; 152 vdd33a-supply = <&veth>; 153 vddvario-supply = <&veth>; 154 }; 155 156 usb@3b000000 { 157 compatible = "nxp,usb-isp1761"; 158 reg = <0x3b000000 0x20000>; 159 interrupt-parent = <&intc_fpga1176>; 160 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; 161 port1-otg; 162 }; 163 164 soc { 165 #address-cells = <1>; 166 #size-cells = <1>; 167 compatible = "arm,realview-pb1176-soc", "simple-bus"; 168 regmap = <&syscon>; 169 ranges; 170 171 syscon: syscon@10000000 { 172 compatible = "arm,realview-pb1176-syscon", "syscon", "simple-mfd"; 173 reg = <0x10000000 0x1000>; 174 175 led@08.0 { 176 compatible = "register-bit-led"; 177 offset = <0x08>; 178 mask = <0x01>; 179 label = "versatile:0"; 180 linux,default-trigger = "heartbeat"; 181 default-state = "on"; 182 }; 183 led@08.1 { 184 compatible = "register-bit-led"; 185 offset = <0x08>; 186 mask = <0x02>; 187 label = "versatile:1"; 188 linux,default-trigger = "mmc0"; 189 default-state = "off"; 190 }; 191 led@08.2 { 192 compatible = "register-bit-led"; 193 offset = <0x08>; 194 mask = <0x04>; 195 label = "versatile:2"; 196 linux,default-trigger = "cpu0"; 197 default-state = "off"; 198 }; 199 led@08.3 { 200 compatible = "register-bit-led"; 201 offset = <0x08>; 202 mask = <0x08>; 203 label = "versatile:3"; 204 default-state = "off"; 205 }; 206 led@08.4 { 207 compatible = "register-bit-led"; 208 offset = <0x08>; 209 mask = <0x10>; 210 label = "versatile:4"; 211 default-state = "off"; 212 }; 213 led@08.5 { 214 compatible = "register-bit-led"; 215 offset = <0x08>; 216 mask = <0x20>; 217 label = "versatile:5"; 218 default-state = "off"; 219 }; 220 led@08.6 { 221 compatible = "register-bit-led"; 222 offset = <0x08>; 223 mask = <0x40>; 224 label = "versatile:6"; 225 default-state = "off"; 226 }; 227 led@08.7 { 228 compatible = "register-bit-led"; 229 offset = <0x08>; 230 mask = <0x80>; 231 label = "versatile:7"; 232 default-state = "off"; 233 }; 234 oscclk0: osc0@0c { 235 compatible = "arm,syscon-icst307"; 236 #clock-cells = <0>; 237 lock-offset = <0x20>; 238 vco-offset = <0x0C>; 239 clocks = <&xtal24mhz>; 240 }; 241 oscclk1: osc1@10 { 242 compatible = "arm,syscon-icst307"; 243 #clock-cells = <0>; 244 lock-offset = <0x20>; 245 vco-offset = <0x10>; 246 clocks = <&xtal24mhz>; 247 }; 248 oscclk2: osc2@14 { 249 compatible = "arm,syscon-icst307"; 250 #clock-cells = <0>; 251 lock-offset = <0x20>; 252 vco-offset = <0x14>; 253 clocks = <&xtal24mhz>; 254 }; 255 oscclk3: osc3@18 { 256 compatible = "arm,syscon-icst307"; 257 #clock-cells = <0>; 258 lock-offset = <0x20>; 259 vco-offset = <0x18>; 260 clocks = <&xtal24mhz>; 261 }; 262 oscclk4: osc4@1c { 263 compatible = "arm,syscon-icst307"; 264 #clock-cells = <0>; 265 lock-offset = <0x20>; 266 vco-offset = <0x1c>; 267 clocks = <&xtal24mhz>; 268 }; 269 }; 270 271 /* Primary DevChip GIC synthesized with the CPU */ 272 intc_dc1176: interrupt-controller@10120000 { 273 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; 274 #interrupt-cells = <3>; 275 #address-cells = <1>; 276 interrupt-controller; 277 reg = <0x10121000 0x1000>, 278 <0x10120000 0x100>; 279 }; 280 281 L2: l2-cache { 282 compatible = "arm,l220-cache"; 283 reg = <0x10110000 0x1000>; 284 interrupt-parent = <&intc_dc1176>; 285 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; 286 cache-unified; 287 cache-level = <2>; 288 /* 289 * Override default cache size, sets and 290 * associativity as these may be erroneously set 291 * up by boot loader(s). 292 */ 293 arm,override-auxreg; 294 cache-size = <131072>; // 128kB 295 cache-sets = <512>; 296 cache-line-size = <32>; 297 }; 298 299 pmu { 300 compatible = "arm,arm1176-pmu"; 301 interrupt-parent = <&intc_dc1176>; 302 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 303 }; 304 305 timer01: timer@10104000 { 306 compatible = "arm,sp804", "arm,primecell"; 307 reg = <0x10104000 0x1000>; 308 interrupt-parent = <&intc_dc1176>; 309 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&timclk>, <&timclk>, <&pclk>; 311 clock-names = "timer1", "timer2", "apb_pclk"; 312 }; 313 314 timer23: timer@10105000 { 315 compatible = "arm,sp804", "arm,primecell"; 316 reg = <0x10105000 0x1000>; 317 interrupt-parent = <&intc_dc1176>; 318 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 319 arm,sp804-has-irq = <1>; 320 clocks = <&timclk>, <&timclk>, <&pclk>; 321 clock-names = "timer1", "timer2", "apb_pclk"; 322 }; 323 324 pb1176_rtc: rtc@10108000 { 325 compatible = "arm,pl031", "arm,primecell"; 326 reg = <0x10108000 0x1000>; 327 interrupt-parent = <&intc_dc1176>; 328 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&pclk>; 330 clock-names = "apb_pclk"; 331 }; 332 333 pb1176_gpio0: gpio@1010a000 { 334 compatible = "arm,pl061", "arm,primecell"; 335 reg = <0x1010a000 0x1000>; 336 gpio-controller; 337 interrupt-parent = <&intc_dc1176>; 338 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; 339 #gpio-cells = <2>; 340 interrupt-controller; 341 #interrupt-cells = <2>; 342 clocks = <&pclk>; 343 clock-names = "apb_pclk"; 344 }; 345 346 pb1176_ssp: ssp@1010b000 { 347 compatible = "arm,pl022", "arm,primecell"; 348 reg = <0x1010b000 0x1000>; 349 interrupt-parent = <&intc_dc1176>; 350 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&sspclk>, <&pclk>; 352 clock-names = "SSPCLK", "apb_pclk"; 353 }; 354 355 pb1176_serial0: serial@1010c000 { 356 compatible = "arm,pl011", "arm,primecell"; 357 reg = <0x1010c000 0x1000>; 358 interrupt-parent = <&intc_dc1176>; 359 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&uartclk>, <&pclk>; 361 clock-names = "uartclk", "apb_pclk"; 362 }; 363 364 pb1176_serial1: serial@1010d000 { 365 compatible = "arm,pl011", "arm,primecell"; 366 reg = <0x1010d000 0x1000>; 367 interrupt-parent = <&intc_dc1176>; 368 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&uartclk>, <&pclk>; 370 clock-names = "uartclk", "apb_pclk"; 371 }; 372 373 pb1176_serial2: serial@1010e000 { 374 compatible = "arm,pl011", "arm,primecell"; 375 reg = <0x1010e000 0x1000>; 376 interrupt-parent = <&intc_dc1176>; 377 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&uartclk>, <&pclk>; 379 clock-names = "uartclk", "apb_pclk"; 380 }; 381 382 pb1176_serial3: serial@1010f000 { 383 compatible = "arm,pl011", "arm,primecell"; 384 reg = <0x1010f000 0x1000>; 385 interrupt-parent = <&intc_dc1176>; 386 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&uartclk>, <&pclk>; 388 clock-names = "uartclk", "apb_pclk"; 389 }; 390 391 /* Direct-mapped development chip ROM */ 392 pb1176_rom@10200000 { 393 compatible = "direct-mapped"; 394 reg = <0x10200000 0x4000>; 395 bank-width = <1>; 396 }; 397 398 clcd@10112000 { 399 compatible = "arm,pl111", "arm,primecell"; 400 reg = <0x10112000 0x1000>; 401 interrupt-parent = <&intc_dc1176>; 402 interrupt-names = "combined"; 403 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&oscclk0>, <&pclk>; 405 clock-names = "clcdclk", "apb_pclk"; 406 407 port { 408 clcd_pads: endpoint { 409 remote-endpoint = <&clcd_panel>; 410 arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 411 }; 412 }; 413 414 panel { 415 compatible = "panel-dpi"; 416 417 port { 418 clcd_panel: endpoint { 419 remote-endpoint = <&clcd_pads>; 420 }; 421 }; 422 423 /* Standard 640x480 VGA timings */ 424 panel-timing { 425 clock-frequency = <25175000>; 426 hactive = <640>; 427 hback-porch = <48>; 428 hfront-porch = <16>; 429 hsync-len = <96>; 430 vactive = <480>; 431 vback-porch = <33>; 432 vfront-porch = <10>; 433 vsync-len = <2>; 434 }; 435 }; 436 }; 437 }; 438 439 /* These peripherals are inside the FPGA rather than the DevChip */ 440 fpga { 441 #address-cells = <1>; 442 #size-cells = <1>; 443 compatible = "simple-bus"; 444 ranges; 445 446 i2c0: i2c@10002000 { 447 #address-cells = <1>; 448 #size-cells = <0>; 449 compatible = "arm,versatile-i2c"; 450 reg = <0x10002000 0x1000>; 451 452 rtc@68 { 453 compatible = "dallas,ds1338"; 454 reg = <0x68>; 455 }; 456 }; 457 458 fpga_aaci: aaci@10004000 { 459 compatible = "arm,pl041", "arm,primecell"; 460 reg = <0x10004000 0x1000>; 461 interrupt-parent = <&intc_fpga1176>; 462 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&pclk>; 464 clock-names = "apb_pclk"; 465 }; 466 467 fpga_mci: mmcsd@10005000 { 468 compatible = "arm,pl18x", "arm,primecell"; 469 reg = <0x10005000 0x1000>; 470 interrupt-parent = <&intc_fpga1176>; 471 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>, 472 <0 2 IRQ_TYPE_LEVEL_HIGH>; 473 /* Due to frequent FIFO overruns, use just 500 kHz */ 474 max-frequency = <500000>; 475 bus-width = <4>; 476 cap-sd-highspeed; 477 cap-mmc-highspeed; 478 clocks = <&mclk>, <&pclk>; 479 clock-names = "mclk", "apb_pclk"; 480 vmmc-supply = <&vmmc>; 481 cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>; 482 wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>; 483 }; 484 485 fpga_kmi0: kmi@10006000 { 486 compatible = "arm,pl050", "arm,primecell"; 487 reg = <0x10006000 0x1000>; 488 interrupt-parent = <&intc_fpga1176>; 489 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&kmiclk>, <&pclk>; 491 clock-names = "KMIREFCLK", "apb_pclk"; 492 }; 493 494 fpga_kmi1: kmi@10007000 { 495 compatible = "arm,pl050", "arm,primecell"; 496 reg = <0x10007000 0x1000>; 497 interrupt-parent = <&intc_fpga1176>; 498 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&kmiclk>, <&pclk>; 500 clock-names = "KMIREFCLK", "apb_pclk"; 501 }; 502 503 fpga_charlcd: charlcd@10008000 { 504 compatible = "arm,versatile-lcd"; 505 reg = <0x10008000 0x1000>; 506 interrupt-parent = <&intc_fpga1176>; 507 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&pclk>; 509 clock-names = "apb_pclk"; 510 }; 511 512 fpga_serial: serial@10009000 { 513 compatible = "arm,pl011", "arm,primecell"; 514 reg = <0x10009000 0x1000>; 515 interrupt-parent = <&intc_fpga1176>; 516 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&uartclk>, <&pclk>; 518 clock-names = "uartclk", "apb_pclk"; 519 }; 520 521 /* This GIC on the board is cascaded off the DevChip GIC */ 522 intc_fpga1176: interrupt-controller@10040000 { 523 compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; 524 #interrupt-cells = <3>; 525 #address-cells = <1>; 526 interrupt-controller; 527 reg = <0x10041000 0x1000>, 528 <0x10040000 0x100>; 529 interrupt-parent = <&intc_dc1176>; 530 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 531 }; 532 533 fpga_gpio0: gpio@10014000 { 534 compatible = "arm,pl061", "arm,primecell"; 535 reg = <0x10014000 0x1000>; 536 gpio-controller; 537 interrupt-parent = <&intc_fpga1176>; 538 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; 539 #gpio-cells = <2>; 540 interrupt-controller; 541 #interrupt-cells = <2>; 542 clocks = <&pclk>; 543 clock-names = "apb_pclk"; 544 }; 545 546 fpga_gpio1: gpio@10015000 { 547 compatible = "arm,pl061", "arm,primecell"; 548 reg = <0x10015000 0x1000>; 549 gpio-controller; 550 interrupt-parent = <&intc_fpga1176>; 551 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; 552 #gpio-cells = <2>; 553 interrupt-controller; 554 #interrupt-cells = <2>; 555 clocks = <&pclk>; 556 clock-names = "apb_pclk"; 557 }; 558 559 fpga_rtc: rtc@10017000 { 560 compatible = "arm,pl031", "arm,primecell"; 561 reg = <0x10017000 0x1000>; 562 interrupt-parent = <&intc_fpga1176>; 563 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&pclk>; 565 clock-names = "apb_pclk"; 566 }; 567 568 569 }; 570}; 571