1/* 2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * Based on "omap4.dtsi" 8 */ 9 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/dra.h> 12 13#define MAX_SOURCES 400 14 15/ { 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 compatible = "ti,dra7xx"; 20 interrupt-parent = <&crossbar_mpu>; 21 chosen { }; 22 23 aliases { 24 i2c0 = &i2c1; 25 i2c1 = &i2c2; 26 i2c2 = &i2c3; 27 i2c3 = &i2c4; 28 i2c4 = &i2c5; 29 serial0 = &uart1; 30 serial1 = &uart2; 31 serial2 = &uart3; 32 serial3 = &uart4; 33 serial4 = &uart5; 34 serial5 = &uart6; 35 serial6 = &uart7; 36 serial7 = &uart8; 37 serial8 = &uart9; 38 serial9 = &uart10; 39 ethernet0 = &cpsw_emac0; 40 ethernet1 = &cpsw_emac1; 41 d_can0 = &dcan1; 42 d_can1 = &dcan2; 43 spi0 = &qspi; 44 }; 45 46 timer { 47 compatible = "arm,armv7-timer"; 48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 52 interrupt-parent = <&gic>; 53 }; 54 55 gic: interrupt-controller@48211000 { 56 compatible = "arm,cortex-a15-gic"; 57 interrupt-controller; 58 #interrupt-cells = <3>; 59 reg = <0x0 0x48211000 0x0 0x1000>, 60 <0x0 0x48212000 0x0 0x1000>, 61 <0x0 0x48214000 0x0 0x2000>, 62 <0x0 0x48216000 0x0 0x2000>; 63 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 64 interrupt-parent = <&gic>; 65 }; 66 67 wakeupgen: interrupt-controller@48281000 { 68 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; 69 interrupt-controller; 70 #interrupt-cells = <3>; 71 reg = <0x0 0x48281000 0x0 0x1000>; 72 interrupt-parent = <&gic>; 73 }; 74 75 cpus { 76 #address-cells = <1>; 77 #size-cells = <0>; 78 79 cpu0: cpu@0 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a15"; 82 reg = <0>; 83 84 operating-points = < 85 /* kHz uV */ 86 1000000 1060000 87 1176000 1160000 88 >; 89 90 clocks = <&dpll_mpu_ck>; 91 clock-names = "cpu"; 92 93 clock-latency = <300000>; /* From omap-cpufreq driver */ 94 95 /* cooling options */ 96 cooling-min-level = <0>; 97 cooling-max-level = <2>; 98 #cooling-cells = <2>; /* min followed by max */ 99 }; 100 }; 101 102 /* 103 * The soc node represents the soc top level view. It is used for IPs 104 * that are not memory mapped in the MPU view or for the MPU itself. 105 */ 106 soc { 107 compatible = "ti,omap-infra"; 108 mpu { 109 compatible = "ti,omap5-mpu"; 110 ti,hwmods = "mpu"; 111 }; 112 }; 113 114 /* 115 * XXX: Use a flat representation of the SOC interconnect. 116 * The real OMAP interconnect network is quite complex. 117 * Since it will not bring real advantage to represent that in DT for 118 * the moment, just use a fake OCP bus entry to represent the whole bus 119 * hierarchy. 120 */ 121 ocp { 122 compatible = "ti,dra7-l3-noc", "simple-bus"; 123 #address-cells = <1>; 124 #size-cells = <1>; 125 ranges = <0x0 0x0 0x0 0xc0000000>; 126 ti,hwmods = "l3_main_1", "l3_main_2"; 127 reg = <0x0 0x44000000 0x0 0x1000000>, 128 <0x0 0x45000000 0x0 0x1000>; 129 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 130 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 131 132 l4_cfg: l4@4a000000 { 133 compatible = "ti,dra7-l4-cfg", "simple-bus"; 134 #address-cells = <1>; 135 #size-cells = <1>; 136 ranges = <0 0x4a000000 0x22c000>; 137 138 scm: scm@2000 { 139 compatible = "ti,dra7-scm-core", "simple-bus"; 140 reg = <0x2000 0x2000>; 141 #address-cells = <1>; 142 #size-cells = <1>; 143 ranges = <0 0x2000 0x2000>; 144 145 scm_conf: scm_conf@0 { 146 compatible = "syscon", "simple-bus"; 147 reg = <0x0 0x1400>; 148 #address-cells = <1>; 149 #size-cells = <1>; 150 ranges = <0 0x0 0x1400>; 151 152 pbias_regulator: pbias_regulator@e00 { 153 compatible = "ti,pbias-dra7", "ti,pbias-omap"; 154 reg = <0xe00 0x4>; 155 syscon = <&scm_conf>; 156 pbias_mmc_reg: pbias_mmc_omap5 { 157 regulator-name = "pbias_mmc_omap5"; 158 regulator-min-microvolt = <1800000>; 159 regulator-max-microvolt = <3000000>; 160 }; 161 }; 162 163 scm_conf_clocks: clocks { 164 #address-cells = <1>; 165 #size-cells = <0>; 166 }; 167 }; 168 169 dra7_pmx_core: pinmux@1400 { 170 compatible = "ti,dra7-padconf", 171 "pinctrl-single"; 172 reg = <0x1400 0x0468>; 173 #address-cells = <1>; 174 #size-cells = <0>; 175 #interrupt-cells = <1>; 176 interrupt-controller; 177 pinctrl-single,register-width = <32>; 178 pinctrl-single,function-mask = <0x3fffffff>; 179 }; 180 181 scm_conf1: scm_conf@1c04 { 182 compatible = "syscon"; 183 reg = <0x1c04 0x0020>; 184 }; 185 186 scm_conf_pcie: scm_conf@1c24 { 187 compatible = "syscon"; 188 reg = <0x1c24 0x0024>; 189 }; 190 191 sdma_xbar: dma-router@b78 { 192 compatible = "ti,dra7-dma-crossbar"; 193 reg = <0xb78 0xfc>; 194 #dma-cells = <1>; 195 dma-requests = <205>; 196 ti,dma-safe-map = <0>; 197 dma-masters = <&sdma>; 198 }; 199 200 edma_xbar: dma-router@c78 { 201 compatible = "ti,dra7-dma-crossbar"; 202 reg = <0xc78 0x7c>; 203 #dma-cells = <2>; 204 dma-requests = <204>; 205 ti,dma-safe-map = <0>; 206 dma-masters = <&edma>; 207 }; 208 }; 209 210 cm_core_aon: cm_core_aon@5000 { 211 compatible = "ti,dra7-cm-core-aon"; 212 reg = <0x5000 0x2000>; 213 214 cm_core_aon_clocks: clocks { 215 #address-cells = <1>; 216 #size-cells = <0>; 217 }; 218 219 cm_core_aon_clockdomains: clockdomains { 220 }; 221 }; 222 223 cm_core: cm_core@8000 { 224 compatible = "ti,dra7-cm-core"; 225 reg = <0x8000 0x3000>; 226 227 cm_core_clocks: clocks { 228 #address-cells = <1>; 229 #size-cells = <0>; 230 }; 231 232 cm_core_clockdomains: clockdomains { 233 }; 234 }; 235 }; 236 237 l4_wkup: l4@4ae00000 { 238 compatible = "ti,dra7-l4-wkup", "simple-bus"; 239 #address-cells = <1>; 240 #size-cells = <1>; 241 ranges = <0 0x4ae00000 0x3f000>; 242 243 counter32k: counter@4000 { 244 compatible = "ti,omap-counter32k"; 245 reg = <0x4000 0x40>; 246 ti,hwmods = "counter_32k"; 247 }; 248 249 prm: prm@6000 { 250 compatible = "ti,dra7-prm"; 251 reg = <0x6000 0x3000>; 252 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 253 254 prm_clocks: clocks { 255 #address-cells = <1>; 256 #size-cells = <0>; 257 }; 258 259 prm_clockdomains: clockdomains { 260 }; 261 }; 262 263 scm_wkup: scm_conf@c000 { 264 compatible = "syscon"; 265 reg = <0xc000 0x1000>; 266 }; 267 }; 268 269 axi@0 { 270 compatible = "simple-bus"; 271 #size-cells = <1>; 272 #address-cells = <1>; 273 ranges = <0x51000000 0x51000000 0x3000 274 0x0 0x20000000 0x10000000>; 275 pcie1: pcie@51000000 { 276 compatible = "ti,dra7-pcie"; 277 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; 278 reg-names = "rc_dbics", "ti_conf", "config"; 279 interrupts = <0 232 0x4>, <0 233 0x4>; 280 #address-cells = <3>; 281 #size-cells = <2>; 282 device_type = "pci"; 283 ranges = <0x81000000 0 0 0x03000 0 0x00010000 284 0x82000000 0 0x20013000 0x13000 0 0xffed000>; 285 bus-range = <0x00 0xff>; 286 #interrupt-cells = <1>; 287 num-lanes = <1>; 288 linux,pci-domain = <0>; 289 ti,hwmods = "pcie1"; 290 phys = <&pcie1_phy>; 291 phy-names = "pcie-phy0"; 292 interrupt-map-mask = <0 0 0 7>; 293 interrupt-map = <0 0 0 1 &pcie1_intc 1>, 294 <0 0 0 2 &pcie1_intc 2>, 295 <0 0 0 3 &pcie1_intc 3>, 296 <0 0 0 4 &pcie1_intc 4>; 297 pcie1_intc: interrupt-controller { 298 interrupt-controller; 299 #address-cells = <0>; 300 #interrupt-cells = <1>; 301 }; 302 }; 303 }; 304 305 axi@1 { 306 compatible = "simple-bus"; 307 #size-cells = <1>; 308 #address-cells = <1>; 309 ranges = <0x51800000 0x51800000 0x3000 310 0x0 0x30000000 0x10000000>; 311 status = "disabled"; 312 pcie@51800000 { 313 compatible = "ti,dra7-pcie"; 314 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; 315 reg-names = "rc_dbics", "ti_conf", "config"; 316 interrupts = <0 355 0x4>, <0 356 0x4>; 317 #address-cells = <3>; 318 #size-cells = <2>; 319 device_type = "pci"; 320 ranges = <0x81000000 0 0 0x03000 0 0x00010000 321 0x82000000 0 0x30013000 0x13000 0 0xffed000>; 322 bus-range = <0x00 0xff>; 323 #interrupt-cells = <1>; 324 num-lanes = <1>; 325 linux,pci-domain = <1>; 326 ti,hwmods = "pcie2"; 327 phys = <&pcie2_phy>; 328 phy-names = "pcie-phy0"; 329 interrupt-map-mask = <0 0 0 7>; 330 interrupt-map = <0 0 0 1 &pcie2_intc 1>, 331 <0 0 0 2 &pcie2_intc 2>, 332 <0 0 0 3 &pcie2_intc 3>, 333 <0 0 0 4 &pcie2_intc 4>; 334 pcie2_intc: interrupt-controller { 335 interrupt-controller; 336 #address-cells = <0>; 337 #interrupt-cells = <1>; 338 }; 339 }; 340 }; 341 342 ocmcram1: ocmcram@40300000 { 343 compatible = "mmio-sram"; 344 reg = <0x40300000 0x80000>; 345 ranges = <0x0 0x40300000 0x80000>; 346 #address-cells = <1>; 347 #size-cells = <1>; 348 /* 349 * This is a placeholder for an optional reserved 350 * region for use by secure software. The size 351 * of this region is not known until runtime so it 352 * is set as zero to either be updated to reserve 353 * space or left unchanged to leave all SRAM for use. 354 * On HS parts that that require the reserved region 355 * either the bootloader can update the size to 356 * the required amount or the node can be overridden 357 * from the board dts file for the secure platform. 358 */ 359 sram-hs@0 { 360 compatible = "ti,secure-ram"; 361 reg = <0x0 0x0>; 362 }; 363 }; 364 365 /* 366 * NOTE: ocmcram2 and ocmcram3 are not available on all 367 * DRA7xx and AM57xx variants. Confirm availability in 368 * the data manual for the exact part number in use 369 * before enabling these nodes in the board dts file. 370 */ 371 ocmcram2: ocmcram@40400000 { 372 status = "disabled"; 373 compatible = "mmio-sram"; 374 reg = <0x40400000 0x100000>; 375 ranges = <0x0 0x40400000 0x100000>; 376 #address-cells = <1>; 377 #size-cells = <1>; 378 }; 379 380 ocmcram3: ocmcram@40500000 { 381 status = "disabled"; 382 compatible = "mmio-sram"; 383 reg = <0x40500000 0x100000>; 384 ranges = <0x0 0x40500000 0x100000>; 385 #address-cells = <1>; 386 #size-cells = <1>; 387 }; 388 389 bandgap: bandgap@4a0021e0 { 390 reg = <0x4a0021e0 0xc 391 0x4a00232c 0xc 392 0x4a002380 0x2c 393 0x4a0023C0 0x3c 394 0x4a002564 0x8 395 0x4a002574 0x50>; 396 compatible = "ti,dra752-bandgap"; 397 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 398 #thermal-sensor-cells = <1>; 399 }; 400 401 dsp1_system: dsp_system@40d00000 { 402 compatible = "syscon"; 403 reg = <0x40d00000 0x100>; 404 }; 405 406 sdma: dma-controller@4a056000 { 407 compatible = "ti,omap4430-sdma"; 408 reg = <0x4a056000 0x1000>; 409 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 413 #dma-cells = <1>; 414 dma-channels = <32>; 415 dma-requests = <127>; 416 }; 417 418 edma: edma@43300000 { 419 compatible = "ti,edma3-tpcc"; 420 ti,hwmods = "tpcc"; 421 reg = <0x43300000 0x100000>; 422 reg-names = "edma3_cc"; 423 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 426 interrupt-names = "edma3_ccint", "edma3_mperr", 427 "edma3_ccerrint"; 428 dma-requests = <64>; 429 #dma-cells = <2>; 430 431 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; 432 433 /* 434 * memcpy is disabled, can be enabled with: 435 * ti,edma-memcpy-channels = <20 21>; 436 * for example. Note that these channels need to be 437 * masked in the xbar as well. 438 */ 439 }; 440 441 edma_tptc0: tptc@43400000 { 442 compatible = "ti,edma3-tptc"; 443 ti,hwmods = "tptc0"; 444 reg = <0x43400000 0x100000>; 445 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 446 interrupt-names = "edma3_tcerrint"; 447 }; 448 449 edma_tptc1: tptc@43500000 { 450 compatible = "ti,edma3-tptc"; 451 ti,hwmods = "tptc1"; 452 reg = <0x43500000 0x100000>; 453 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 454 interrupt-names = "edma3_tcerrint"; 455 }; 456 457 gpio1: gpio@4ae10000 { 458 compatible = "ti,omap4-gpio"; 459 reg = <0x4ae10000 0x200>; 460 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 461 ti,hwmods = "gpio1"; 462 gpio-controller; 463 #gpio-cells = <2>; 464 interrupt-controller; 465 #interrupt-cells = <2>; 466 }; 467 468 gpio2: gpio@48055000 { 469 compatible = "ti,omap4-gpio"; 470 reg = <0x48055000 0x200>; 471 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 472 ti,hwmods = "gpio2"; 473 gpio-controller; 474 #gpio-cells = <2>; 475 interrupt-controller; 476 #interrupt-cells = <2>; 477 }; 478 479 gpio3: gpio@48057000 { 480 compatible = "ti,omap4-gpio"; 481 reg = <0x48057000 0x200>; 482 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 483 ti,hwmods = "gpio3"; 484 gpio-controller; 485 #gpio-cells = <2>; 486 interrupt-controller; 487 #interrupt-cells = <2>; 488 }; 489 490 gpio4: gpio@48059000 { 491 compatible = "ti,omap4-gpio"; 492 reg = <0x48059000 0x200>; 493 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 494 ti,hwmods = "gpio4"; 495 gpio-controller; 496 #gpio-cells = <2>; 497 interrupt-controller; 498 #interrupt-cells = <2>; 499 }; 500 501 gpio5: gpio@4805b000 { 502 compatible = "ti,omap4-gpio"; 503 reg = <0x4805b000 0x200>; 504 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 505 ti,hwmods = "gpio5"; 506 gpio-controller; 507 #gpio-cells = <2>; 508 interrupt-controller; 509 #interrupt-cells = <2>; 510 }; 511 512 gpio6: gpio@4805d000 { 513 compatible = "ti,omap4-gpio"; 514 reg = <0x4805d000 0x200>; 515 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 516 ti,hwmods = "gpio6"; 517 gpio-controller; 518 #gpio-cells = <2>; 519 interrupt-controller; 520 #interrupt-cells = <2>; 521 }; 522 523 gpio7: gpio@48051000 { 524 compatible = "ti,omap4-gpio"; 525 reg = <0x48051000 0x200>; 526 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 527 ti,hwmods = "gpio7"; 528 gpio-controller; 529 #gpio-cells = <2>; 530 interrupt-controller; 531 #interrupt-cells = <2>; 532 }; 533 534 gpio8: gpio@48053000 { 535 compatible = "ti,omap4-gpio"; 536 reg = <0x48053000 0x200>; 537 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 538 ti,hwmods = "gpio8"; 539 gpio-controller; 540 #gpio-cells = <2>; 541 interrupt-controller; 542 #interrupt-cells = <2>; 543 }; 544 545 uart1: serial@4806a000 { 546 compatible = "ti,dra742-uart", "ti,omap4-uart"; 547 reg = <0x4806a000 0x100>; 548 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 549 ti,hwmods = "uart1"; 550 clock-frequency = <48000000>; 551 status = "disabled"; 552 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; 553 dma-names = "tx", "rx"; 554 }; 555 556 uart2: serial@4806c000 { 557 compatible = "ti,dra742-uart", "ti,omap4-uart"; 558 reg = <0x4806c000 0x100>; 559 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 560 ti,hwmods = "uart2"; 561 clock-frequency = <48000000>; 562 status = "disabled"; 563 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; 564 dma-names = "tx", "rx"; 565 }; 566 567 uart3: serial@48020000 { 568 compatible = "ti,dra742-uart", "ti,omap4-uart"; 569 reg = <0x48020000 0x100>; 570 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 571 ti,hwmods = "uart3"; 572 clock-frequency = <48000000>; 573 status = "disabled"; 574 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; 575 dma-names = "tx", "rx"; 576 }; 577 578 uart4: serial@4806e000 { 579 compatible = "ti,dra742-uart", "ti,omap4-uart"; 580 reg = <0x4806e000 0x100>; 581 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 582 ti,hwmods = "uart4"; 583 clock-frequency = <48000000>; 584 status = "disabled"; 585 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; 586 dma-names = "tx", "rx"; 587 }; 588 589 uart5: serial@48066000 { 590 compatible = "ti,dra742-uart", "ti,omap4-uart"; 591 reg = <0x48066000 0x100>; 592 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 593 ti,hwmods = "uart5"; 594 clock-frequency = <48000000>; 595 status = "disabled"; 596 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; 597 dma-names = "tx", "rx"; 598 }; 599 600 uart6: serial@48068000 { 601 compatible = "ti,dra742-uart", "ti,omap4-uart"; 602 reg = <0x48068000 0x100>; 603 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 604 ti,hwmods = "uart6"; 605 clock-frequency = <48000000>; 606 status = "disabled"; 607 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; 608 dma-names = "tx", "rx"; 609 }; 610 611 uart7: serial@48420000 { 612 compatible = "ti,dra742-uart", "ti,omap4-uart"; 613 reg = <0x48420000 0x100>; 614 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 615 ti,hwmods = "uart7"; 616 clock-frequency = <48000000>; 617 status = "disabled"; 618 }; 619 620 uart8: serial@48422000 { 621 compatible = "ti,dra742-uart", "ti,omap4-uart"; 622 reg = <0x48422000 0x100>; 623 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 624 ti,hwmods = "uart8"; 625 clock-frequency = <48000000>; 626 status = "disabled"; 627 }; 628 629 uart9: serial@48424000 { 630 compatible = "ti,dra742-uart", "ti,omap4-uart"; 631 reg = <0x48424000 0x100>; 632 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 633 ti,hwmods = "uart9"; 634 clock-frequency = <48000000>; 635 status = "disabled"; 636 }; 637 638 uart10: serial@4ae2b000 { 639 compatible = "ti,dra742-uart", "ti,omap4-uart"; 640 reg = <0x4ae2b000 0x100>; 641 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 642 ti,hwmods = "uart10"; 643 clock-frequency = <48000000>; 644 status = "disabled"; 645 }; 646 647 mailbox1: mailbox@4a0f4000 { 648 compatible = "ti,omap4-mailbox"; 649 reg = <0x4a0f4000 0x200>; 650 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 653 ti,hwmods = "mailbox1"; 654 #mbox-cells = <1>; 655 ti,mbox-num-users = <3>; 656 ti,mbox-num-fifos = <8>; 657 status = "disabled"; 658 }; 659 660 mailbox2: mailbox@4883a000 { 661 compatible = "ti,omap4-mailbox"; 662 reg = <0x4883a000 0x200>; 663 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 667 ti,hwmods = "mailbox2"; 668 #mbox-cells = <1>; 669 ti,mbox-num-users = <4>; 670 ti,mbox-num-fifos = <12>; 671 status = "disabled"; 672 }; 673 674 mailbox3: mailbox@4883c000 { 675 compatible = "ti,omap4-mailbox"; 676 reg = <0x4883c000 0x200>; 677 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 681 ti,hwmods = "mailbox3"; 682 #mbox-cells = <1>; 683 ti,mbox-num-users = <4>; 684 ti,mbox-num-fifos = <12>; 685 status = "disabled"; 686 }; 687 688 mailbox4: mailbox@4883e000 { 689 compatible = "ti,omap4-mailbox"; 690 reg = <0x4883e000 0x200>; 691 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 695 ti,hwmods = "mailbox4"; 696 #mbox-cells = <1>; 697 ti,mbox-num-users = <4>; 698 ti,mbox-num-fifos = <12>; 699 status = "disabled"; 700 }; 701 702 mailbox5: mailbox@48840000 { 703 compatible = "ti,omap4-mailbox"; 704 reg = <0x48840000 0x200>; 705 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 709 ti,hwmods = "mailbox5"; 710 #mbox-cells = <1>; 711 ti,mbox-num-users = <4>; 712 ti,mbox-num-fifos = <12>; 713 status = "disabled"; 714 }; 715 716 mailbox6: mailbox@48842000 { 717 compatible = "ti,omap4-mailbox"; 718 reg = <0x48842000 0x200>; 719 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 723 ti,hwmods = "mailbox6"; 724 #mbox-cells = <1>; 725 ti,mbox-num-users = <4>; 726 ti,mbox-num-fifos = <12>; 727 status = "disabled"; 728 }; 729 730 mailbox7: mailbox@48844000 { 731 compatible = "ti,omap4-mailbox"; 732 reg = <0x48844000 0x200>; 733 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 737 ti,hwmods = "mailbox7"; 738 #mbox-cells = <1>; 739 ti,mbox-num-users = <4>; 740 ti,mbox-num-fifos = <12>; 741 status = "disabled"; 742 }; 743 744 mailbox8: mailbox@48846000 { 745 compatible = "ti,omap4-mailbox"; 746 reg = <0x48846000 0x200>; 747 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; 751 ti,hwmods = "mailbox8"; 752 #mbox-cells = <1>; 753 ti,mbox-num-users = <4>; 754 ti,mbox-num-fifos = <12>; 755 status = "disabled"; 756 }; 757 758 mailbox9: mailbox@4885e000 { 759 compatible = "ti,omap4-mailbox"; 760 reg = <0x4885e000 0x200>; 761 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 765 ti,hwmods = "mailbox9"; 766 #mbox-cells = <1>; 767 ti,mbox-num-users = <4>; 768 ti,mbox-num-fifos = <12>; 769 status = "disabled"; 770 }; 771 772 mailbox10: mailbox@48860000 { 773 compatible = "ti,omap4-mailbox"; 774 reg = <0x48860000 0x200>; 775 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 779 ti,hwmods = "mailbox10"; 780 #mbox-cells = <1>; 781 ti,mbox-num-users = <4>; 782 ti,mbox-num-fifos = <12>; 783 status = "disabled"; 784 }; 785 786 mailbox11: mailbox@48862000 { 787 compatible = "ti,omap4-mailbox"; 788 reg = <0x48862000 0x200>; 789 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 793 ti,hwmods = "mailbox11"; 794 #mbox-cells = <1>; 795 ti,mbox-num-users = <4>; 796 ti,mbox-num-fifos = <12>; 797 status = "disabled"; 798 }; 799 800 mailbox12: mailbox@48864000 { 801 compatible = "ti,omap4-mailbox"; 802 reg = <0x48864000 0x200>; 803 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 807 ti,hwmods = "mailbox12"; 808 #mbox-cells = <1>; 809 ti,mbox-num-users = <4>; 810 ti,mbox-num-fifos = <12>; 811 status = "disabled"; 812 }; 813 814 mailbox13: mailbox@48802000 { 815 compatible = "ti,omap4-mailbox"; 816 reg = <0x48802000 0x200>; 817 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; 821 ti,hwmods = "mailbox13"; 822 #mbox-cells = <1>; 823 ti,mbox-num-users = <4>; 824 ti,mbox-num-fifos = <12>; 825 status = "disabled"; 826 }; 827 828 timer1: timer@4ae18000 { 829 compatible = "ti,omap5430-timer"; 830 reg = <0x4ae18000 0x80>; 831 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 832 ti,hwmods = "timer1"; 833 ti,timer-alwon; 834 }; 835 836 timer2: timer@48032000 { 837 compatible = "ti,omap5430-timer"; 838 reg = <0x48032000 0x80>; 839 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 840 ti,hwmods = "timer2"; 841 }; 842 843 timer3: timer@48034000 { 844 compatible = "ti,omap5430-timer"; 845 reg = <0x48034000 0x80>; 846 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 847 ti,hwmods = "timer3"; 848 }; 849 850 timer4: timer@48036000 { 851 compatible = "ti,omap5430-timer"; 852 reg = <0x48036000 0x80>; 853 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 854 ti,hwmods = "timer4"; 855 }; 856 857 timer5: timer@48820000 { 858 compatible = "ti,omap5430-timer"; 859 reg = <0x48820000 0x80>; 860 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 861 ti,hwmods = "timer5"; 862 }; 863 864 timer6: timer@48822000 { 865 compatible = "ti,omap5430-timer"; 866 reg = <0x48822000 0x80>; 867 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 868 ti,hwmods = "timer6"; 869 }; 870 871 timer7: timer@48824000 { 872 compatible = "ti,omap5430-timer"; 873 reg = <0x48824000 0x80>; 874 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 875 ti,hwmods = "timer7"; 876 }; 877 878 timer8: timer@48826000 { 879 compatible = "ti,omap5430-timer"; 880 reg = <0x48826000 0x80>; 881 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 882 ti,hwmods = "timer8"; 883 }; 884 885 timer9: timer@4803e000 { 886 compatible = "ti,omap5430-timer"; 887 reg = <0x4803e000 0x80>; 888 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 889 ti,hwmods = "timer9"; 890 }; 891 892 timer10: timer@48086000 { 893 compatible = "ti,omap5430-timer"; 894 reg = <0x48086000 0x80>; 895 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 896 ti,hwmods = "timer10"; 897 }; 898 899 timer11: timer@48088000 { 900 compatible = "ti,omap5430-timer"; 901 reg = <0x48088000 0x80>; 902 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 903 ti,hwmods = "timer11"; 904 }; 905 906 timer12: timer@4ae20000 { 907 compatible = "ti,omap5430-timer"; 908 reg = <0x4ae20000 0x80>; 909 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 910 ti,hwmods = "timer12"; 911 ti,timer-alwon; 912 ti,timer-secure; 913 }; 914 915 timer13: timer@48828000 { 916 compatible = "ti,omap5430-timer"; 917 reg = <0x48828000 0x80>; 918 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 919 ti,hwmods = "timer13"; 920 }; 921 922 timer14: timer@4882a000 { 923 compatible = "ti,omap5430-timer"; 924 reg = <0x4882a000 0x80>; 925 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; 926 ti,hwmods = "timer14"; 927 }; 928 929 timer15: timer@4882c000 { 930 compatible = "ti,omap5430-timer"; 931 reg = <0x4882c000 0x80>; 932 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 933 ti,hwmods = "timer15"; 934 }; 935 936 timer16: timer@4882e000 { 937 compatible = "ti,omap5430-timer"; 938 reg = <0x4882e000 0x80>; 939 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 940 ti,hwmods = "timer16"; 941 }; 942 943 wdt2: wdt@4ae14000 { 944 compatible = "ti,omap3-wdt"; 945 reg = <0x4ae14000 0x80>; 946 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 947 ti,hwmods = "wd_timer2"; 948 }; 949 950 hwspinlock: spinlock@4a0f6000 { 951 compatible = "ti,omap4-hwspinlock"; 952 reg = <0x4a0f6000 0x1000>; 953 ti,hwmods = "spinlock"; 954 #hwlock-cells = <1>; 955 }; 956 957 dmm@4e000000 { 958 compatible = "ti,omap5-dmm"; 959 reg = <0x4e000000 0x800>; 960 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 961 ti,hwmods = "dmm"; 962 }; 963 964 i2c1: i2c@48070000 { 965 compatible = "ti,omap4-i2c"; 966 reg = <0x48070000 0x100>; 967 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 ti,hwmods = "i2c1"; 971 status = "disabled"; 972 }; 973 974 i2c2: i2c@48072000 { 975 compatible = "ti,omap4-i2c"; 976 reg = <0x48072000 0x100>; 977 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 978 #address-cells = <1>; 979 #size-cells = <0>; 980 ti,hwmods = "i2c2"; 981 status = "disabled"; 982 }; 983 984 i2c3: i2c@48060000 { 985 compatible = "ti,omap4-i2c"; 986 reg = <0x48060000 0x100>; 987 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 988 #address-cells = <1>; 989 #size-cells = <0>; 990 ti,hwmods = "i2c3"; 991 status = "disabled"; 992 }; 993 994 i2c4: i2c@4807a000 { 995 compatible = "ti,omap4-i2c"; 996 reg = <0x4807a000 0x100>; 997 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 ti,hwmods = "i2c4"; 1001 status = "disabled"; 1002 }; 1003 1004 i2c5: i2c@4807c000 { 1005 compatible = "ti,omap4-i2c"; 1006 reg = <0x4807c000 0x100>; 1007 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 ti,hwmods = "i2c5"; 1011 status = "disabled"; 1012 }; 1013 1014 mmc1: mmc@4809c000 { 1015 compatible = "ti,omap4-hsmmc"; 1016 reg = <0x4809c000 0x400>; 1017 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1018 ti,hwmods = "mmc1"; 1019 ti,dual-volt; 1020 ti,needs-special-reset; 1021 dmas = <&sdma_xbar 61>, <&sdma_xbar 62>; 1022 dma-names = "tx", "rx"; 1023 status = "disabled"; 1024 pbias-supply = <&pbias_mmc_reg>; 1025 }; 1026 1027 mmc2: mmc@480b4000 { 1028 compatible = "ti,omap4-hsmmc"; 1029 reg = <0x480b4000 0x400>; 1030 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1031 ti,hwmods = "mmc2"; 1032 ti,needs-special-reset; 1033 dmas = <&sdma_xbar 47>, <&sdma_xbar 48>; 1034 dma-names = "tx", "rx"; 1035 status = "disabled"; 1036 }; 1037 1038 mmc3: mmc@480ad000 { 1039 compatible = "ti,omap4-hsmmc"; 1040 reg = <0x480ad000 0x400>; 1041 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1042 ti,hwmods = "mmc3"; 1043 ti,needs-special-reset; 1044 dmas = <&sdma_xbar 77>, <&sdma_xbar 78>; 1045 dma-names = "tx", "rx"; 1046 status = "disabled"; 1047 }; 1048 1049 mmc4: mmc@480d1000 { 1050 compatible = "ti,omap4-hsmmc"; 1051 reg = <0x480d1000 0x400>; 1052 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1053 ti,hwmods = "mmc4"; 1054 ti,needs-special-reset; 1055 dmas = <&sdma_xbar 57>, <&sdma_xbar 58>; 1056 dma-names = "tx", "rx"; 1057 status = "disabled"; 1058 }; 1059 1060 mmu0_dsp1: mmu@40d01000 { 1061 compatible = "ti,dra7-dsp-iommu"; 1062 reg = <0x40d01000 0x100>; 1063 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1064 ti,hwmods = "mmu0_dsp1"; 1065 #iommu-cells = <0>; 1066 ti,syscon-mmuconfig = <&dsp1_system 0x0>; 1067 status = "disabled"; 1068 }; 1069 1070 mmu1_dsp1: mmu@40d02000 { 1071 compatible = "ti,dra7-dsp-iommu"; 1072 reg = <0x40d02000 0x100>; 1073 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 1074 ti,hwmods = "mmu1_dsp1"; 1075 #iommu-cells = <0>; 1076 ti,syscon-mmuconfig = <&dsp1_system 0x1>; 1077 status = "disabled"; 1078 }; 1079 1080 mmu_ipu1: mmu@58882000 { 1081 compatible = "ti,dra7-iommu"; 1082 reg = <0x58882000 0x100>; 1083 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; 1084 ti,hwmods = "mmu_ipu1"; 1085 #iommu-cells = <0>; 1086 ti,iommu-bus-err-back; 1087 status = "disabled"; 1088 }; 1089 1090 mmu_ipu2: mmu@55082000 { 1091 compatible = "ti,dra7-iommu"; 1092 reg = <0x55082000 0x100>; 1093 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; 1094 ti,hwmods = "mmu_ipu2"; 1095 #iommu-cells = <0>; 1096 ti,iommu-bus-err-back; 1097 status = "disabled"; 1098 }; 1099 1100 abb_mpu: regulator-abb-mpu { 1101 compatible = "ti,abb-v3"; 1102 regulator-name = "abb_mpu"; 1103 #address-cells = <0>; 1104 #size-cells = <0>; 1105 clocks = <&sys_clkin1>; 1106 ti,settling-time = <50>; 1107 ti,clock-cycles = <16>; 1108 1109 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, 1110 <0x4ae06014 0x4>, <0x4a003b20 0xc>, 1111 <0x4ae0c158 0x4>; 1112 reg-names = "setup-address", "control-address", 1113 "int-address", "efuse-address", 1114 "ldo-address"; 1115 ti,tranxdone-status-mask = <0x80>; 1116 /* LDOVBBMPU_FBB_MUX_CTRL */ 1117 ti,ldovbb-override-mask = <0x400>; 1118 /* LDOVBBMPU_FBB_VSET_OUT */ 1119 ti,ldovbb-vset-mask = <0x1F>; 1120 1121 /* 1122 * NOTE: only FBB mode used but actual vset will 1123 * determine final biasing 1124 */ 1125 ti,abb_info = < 1126 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1127 1060000 0 0x0 0 0x02000000 0x01F00000 1128 1160000 0 0x4 0 0x02000000 0x01F00000 1129 1210000 0 0x8 0 0x02000000 0x01F00000 1130 >; 1131 }; 1132 1133 abb_ivahd: regulator-abb-ivahd { 1134 compatible = "ti,abb-v3"; 1135 regulator-name = "abb_ivahd"; 1136 #address-cells = <0>; 1137 #size-cells = <0>; 1138 clocks = <&sys_clkin1>; 1139 ti,settling-time = <50>; 1140 ti,clock-cycles = <16>; 1141 1142 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, 1143 <0x4ae06010 0x4>, <0x4a0025cc 0xc>, 1144 <0x4a002470 0x4>; 1145 reg-names = "setup-address", "control-address", 1146 "int-address", "efuse-address", 1147 "ldo-address"; 1148 ti,tranxdone-status-mask = <0x40000000>; 1149 /* LDOVBBIVA_FBB_MUX_CTRL */ 1150 ti,ldovbb-override-mask = <0x400>; 1151 /* LDOVBBIVA_FBB_VSET_OUT */ 1152 ti,ldovbb-vset-mask = <0x1F>; 1153 1154 /* 1155 * NOTE: only FBB mode used but actual vset will 1156 * determine final biasing 1157 */ 1158 ti,abb_info = < 1159 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1160 1055000 0 0x0 0 0x02000000 0x01F00000 1161 1150000 0 0x4 0 0x02000000 0x01F00000 1162 1250000 0 0x8 0 0x02000000 0x01F00000 1163 >; 1164 }; 1165 1166 abb_dspeve: regulator-abb-dspeve { 1167 compatible = "ti,abb-v3"; 1168 regulator-name = "abb_dspeve"; 1169 #address-cells = <0>; 1170 #size-cells = <0>; 1171 clocks = <&sys_clkin1>; 1172 ti,settling-time = <50>; 1173 ti,clock-cycles = <16>; 1174 1175 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, 1176 <0x4ae06010 0x4>, <0x4a0025e0 0xc>, 1177 <0x4a00246c 0x4>; 1178 reg-names = "setup-address", "control-address", 1179 "int-address", "efuse-address", 1180 "ldo-address"; 1181 ti,tranxdone-status-mask = <0x20000000>; 1182 /* LDOVBBDSPEVE_FBB_MUX_CTRL */ 1183 ti,ldovbb-override-mask = <0x400>; 1184 /* LDOVBBDSPEVE_FBB_VSET_OUT */ 1185 ti,ldovbb-vset-mask = <0x1F>; 1186 1187 /* 1188 * NOTE: only FBB mode used but actual vset will 1189 * determine final biasing 1190 */ 1191 ti,abb_info = < 1192 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1193 1055000 0 0x0 0 0x02000000 0x01F00000 1194 1150000 0 0x4 0 0x02000000 0x01F00000 1195 1250000 0 0x8 0 0x02000000 0x01F00000 1196 >; 1197 }; 1198 1199 abb_gpu: regulator-abb-gpu { 1200 compatible = "ti,abb-v3"; 1201 regulator-name = "abb_gpu"; 1202 #address-cells = <0>; 1203 #size-cells = <0>; 1204 clocks = <&sys_clkin1>; 1205 ti,settling-time = <50>; 1206 ti,clock-cycles = <16>; 1207 1208 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, 1209 <0x4ae06010 0x4>, <0x4a003b08 0xc>, 1210 <0x4ae0c154 0x4>; 1211 reg-names = "setup-address", "control-address", 1212 "int-address", "efuse-address", 1213 "ldo-address"; 1214 ti,tranxdone-status-mask = <0x10000000>; 1215 /* LDOVBBGPU_FBB_MUX_CTRL */ 1216 ti,ldovbb-override-mask = <0x400>; 1217 /* LDOVBBGPU_FBB_VSET_OUT */ 1218 ti,ldovbb-vset-mask = <0x1F>; 1219 1220 /* 1221 * NOTE: only FBB mode used but actual vset will 1222 * determine final biasing 1223 */ 1224 ti,abb_info = < 1225 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1226 1090000 0 0x0 0 0x02000000 0x01F00000 1227 1210000 0 0x4 0 0x02000000 0x01F00000 1228 1280000 0 0x8 0 0x02000000 0x01F00000 1229 >; 1230 }; 1231 1232 mcspi1: spi@48098000 { 1233 compatible = "ti,omap4-mcspi"; 1234 reg = <0x48098000 0x200>; 1235 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 ti,hwmods = "mcspi1"; 1239 ti,spi-num-cs = <4>; 1240 dmas = <&sdma_xbar 35>, 1241 <&sdma_xbar 36>, 1242 <&sdma_xbar 37>, 1243 <&sdma_xbar 38>, 1244 <&sdma_xbar 39>, 1245 <&sdma_xbar 40>, 1246 <&sdma_xbar 41>, 1247 <&sdma_xbar 42>; 1248 dma-names = "tx0", "rx0", "tx1", "rx1", 1249 "tx2", "rx2", "tx3", "rx3"; 1250 status = "disabled"; 1251 }; 1252 1253 mcspi2: spi@4809a000 { 1254 compatible = "ti,omap4-mcspi"; 1255 reg = <0x4809a000 0x200>; 1256 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1257 #address-cells = <1>; 1258 #size-cells = <0>; 1259 ti,hwmods = "mcspi2"; 1260 ti,spi-num-cs = <2>; 1261 dmas = <&sdma_xbar 43>, 1262 <&sdma_xbar 44>, 1263 <&sdma_xbar 45>, 1264 <&sdma_xbar 46>; 1265 dma-names = "tx0", "rx0", "tx1", "rx1"; 1266 status = "disabled"; 1267 }; 1268 1269 mcspi3: spi@480b8000 { 1270 compatible = "ti,omap4-mcspi"; 1271 reg = <0x480b8000 0x200>; 1272 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1273 #address-cells = <1>; 1274 #size-cells = <0>; 1275 ti,hwmods = "mcspi3"; 1276 ti,spi-num-cs = <2>; 1277 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; 1278 dma-names = "tx0", "rx0"; 1279 status = "disabled"; 1280 }; 1281 1282 mcspi4: spi@480ba000 { 1283 compatible = "ti,omap4-mcspi"; 1284 reg = <0x480ba000 0x200>; 1285 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 ti,hwmods = "mcspi4"; 1289 ti,spi-num-cs = <1>; 1290 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; 1291 dma-names = "tx0", "rx0"; 1292 status = "disabled"; 1293 }; 1294 1295 qspi: qspi@4b300000 { 1296 compatible = "ti,dra7xxx-qspi"; 1297 reg = <0x4b300000 0x100>, 1298 <0x5c000000 0x4000000>; 1299 reg-names = "qspi_base", "qspi_mmap"; 1300 syscon-chipselects = <&scm_conf 0x558>; 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 ti,hwmods = "qspi"; 1304 clocks = <&qspi_gfclk_div>; 1305 clock-names = "fck"; 1306 num-cs = <4>; 1307 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 1308 status = "disabled"; 1309 }; 1310 1311 /* OCP2SCP3 */ 1312 ocp2scp@4a090000 { 1313 compatible = "ti,omap-ocp2scp"; 1314 #address-cells = <1>; 1315 #size-cells = <1>; 1316 ranges; 1317 reg = <0x4a090000 0x20>; 1318 ti,hwmods = "ocp2scp3"; 1319 sata_phy: phy@4A096000 { 1320 compatible = "ti,phy-pipe3-sata"; 1321 reg = <0x4A096000 0x80>, /* phy_rx */ 1322 <0x4A096400 0x64>, /* phy_tx */ 1323 <0x4A096800 0x40>; /* pll_ctrl */ 1324 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 1325 syscon-phy-power = <&scm_conf 0x374>; 1326 clocks = <&sys_clkin1>, <&sata_ref_clk>; 1327 clock-names = "sysclk", "refclk"; 1328 syscon-pllreset = <&scm_conf 0x3fc>; 1329 #phy-cells = <0>; 1330 }; 1331 1332 pcie1_phy: pciephy@4a094000 { 1333 compatible = "ti,phy-pipe3-pcie"; 1334 reg = <0x4a094000 0x80>, /* phy_rx */ 1335 <0x4a094400 0x64>; /* phy_tx */ 1336 reg-names = "phy_rx", "phy_tx"; 1337 syscon-phy-power = <&scm_conf_pcie 0x1c>; 1338 syscon-pcs = <&scm_conf_pcie 0x10>; 1339 clocks = <&dpll_pcie_ref_ck>, 1340 <&dpll_pcie_ref_m2ldo_ck>, 1341 <&optfclk_pciephy1_32khz>, 1342 <&optfclk_pciephy1_clk>, 1343 <&optfclk_pciephy1_div_clk>, 1344 <&optfclk_pciephy_div>, 1345 <&sys_clkin1>; 1346 clock-names = "dpll_ref", "dpll_ref_m2", 1347 "wkupclk", "refclk", 1348 "div-clk", "phy-div", "sysclk"; 1349 #phy-cells = <0>; 1350 }; 1351 1352 pcie2_phy: pciephy@4a095000 { 1353 compatible = "ti,phy-pipe3-pcie"; 1354 reg = <0x4a095000 0x80>, /* phy_rx */ 1355 <0x4a095400 0x64>; /* phy_tx */ 1356 reg-names = "phy_rx", "phy_tx"; 1357 syscon-phy-power = <&scm_conf_pcie 0x20>; 1358 syscon-pcs = <&scm_conf_pcie 0x10>; 1359 clocks = <&dpll_pcie_ref_ck>, 1360 <&dpll_pcie_ref_m2ldo_ck>, 1361 <&optfclk_pciephy2_32khz>, 1362 <&optfclk_pciephy2_clk>, 1363 <&optfclk_pciephy2_div_clk>, 1364 <&optfclk_pciephy_div>, 1365 <&sys_clkin1>; 1366 clock-names = "dpll_ref", "dpll_ref_m2", 1367 "wkupclk", "refclk", 1368 "div-clk", "phy-div", "sysclk"; 1369 #phy-cells = <0>; 1370 status = "disabled"; 1371 }; 1372 }; 1373 1374 sata: sata@4a141100 { 1375 compatible = "snps,dwc-ahci"; 1376 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; 1377 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1378 phys = <&sata_phy>; 1379 phy-names = "sata-phy"; 1380 clocks = <&sata_ref_clk>; 1381 ti,hwmods = "sata"; 1382 ports-implemented = <0x1>; 1383 }; 1384 1385 rtc: rtc@48838000 { 1386 compatible = "ti,am3352-rtc"; 1387 reg = <0x48838000 0x100>; 1388 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1389 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 1390 ti,hwmods = "rtcss"; 1391 clocks = <&sys_32k_ck>; 1392 }; 1393 1394 /* OCP2SCP1 */ 1395 ocp2scp@4a080000 { 1396 compatible = "ti,omap-ocp2scp"; 1397 #address-cells = <1>; 1398 #size-cells = <1>; 1399 ranges; 1400 reg = <0x4a080000 0x20>; 1401 ti,hwmods = "ocp2scp1"; 1402 1403 usb2_phy1: phy@4a084000 { 1404 compatible = "ti,dra7x-usb2", "ti,omap-usb2"; 1405 reg = <0x4a084000 0x400>; 1406 syscon-phy-power = <&scm_conf 0x300>; 1407 clocks = <&usb_phy1_always_on_clk32k>, 1408 <&usb_otg_ss1_refclk960m>; 1409 clock-names = "wkupclk", 1410 "refclk"; 1411 #phy-cells = <0>; 1412 }; 1413 1414 usb2_phy2: phy@4a085000 { 1415 compatible = "ti,dra7x-usb2-phy2", 1416 "ti,omap-usb2"; 1417 reg = <0x4a085000 0x400>; 1418 syscon-phy-power = <&scm_conf 0xe74>; 1419 clocks = <&usb_phy2_always_on_clk32k>, 1420 <&usb_otg_ss2_refclk960m>; 1421 clock-names = "wkupclk", 1422 "refclk"; 1423 #phy-cells = <0>; 1424 }; 1425 1426 usb3_phy1: phy@4a084400 { 1427 compatible = "ti,omap-usb3"; 1428 reg = <0x4a084400 0x80>, 1429 <0x4a084800 0x64>, 1430 <0x4a084c00 0x40>; 1431 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 1432 syscon-phy-power = <&scm_conf 0x370>; 1433 clocks = <&usb_phy3_always_on_clk32k>, 1434 <&sys_clkin1>, 1435 <&usb_otg_ss1_refclk960m>; 1436 clock-names = "wkupclk", 1437 "sysclk", 1438 "refclk"; 1439 #phy-cells = <0>; 1440 }; 1441 }; 1442 1443 omap_dwc3_1: omap_dwc3_1@48880000 { 1444 compatible = "ti,dwc3"; 1445 ti,hwmods = "usb_otg_ss1"; 1446 reg = <0x48880000 0x10000>; 1447 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1448 #address-cells = <1>; 1449 #size-cells = <1>; 1450 utmi-mode = <2>; 1451 ranges; 1452 usb1: usb@48890000 { 1453 compatible = "snps,dwc3"; 1454 reg = <0x48890000 0x17000>; 1455 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1458 interrupt-names = "peripheral", 1459 "host", 1460 "otg"; 1461 phys = <&usb2_phy1>, <&usb3_phy1>; 1462 phy-names = "usb2-phy", "usb3-phy"; 1463 maximum-speed = "super-speed"; 1464 dr_mode = "otg"; 1465 snps,dis_u3_susphy_quirk; 1466 snps,dis_u2_susphy_quirk; 1467 }; 1468 }; 1469 1470 omap_dwc3_2: omap_dwc3_2@488c0000 { 1471 compatible = "ti,dwc3"; 1472 ti,hwmods = "usb_otg_ss2"; 1473 reg = <0x488c0000 0x10000>; 1474 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1475 #address-cells = <1>; 1476 #size-cells = <1>; 1477 utmi-mode = <2>; 1478 ranges; 1479 usb2: usb@488d0000 { 1480 compatible = "snps,dwc3"; 1481 reg = <0x488d0000 0x17000>; 1482 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1485 interrupt-names = "peripheral", 1486 "host", 1487 "otg"; 1488 phys = <&usb2_phy2>; 1489 phy-names = "usb2-phy"; 1490 maximum-speed = "high-speed"; 1491 dr_mode = "otg"; 1492 snps,dis_u3_susphy_quirk; 1493 snps,dis_u2_susphy_quirk; 1494 }; 1495 }; 1496 1497 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ 1498 omap_dwc3_3: omap_dwc3_3@48900000 { 1499 compatible = "ti,dwc3"; 1500 ti,hwmods = "usb_otg_ss3"; 1501 reg = <0x48900000 0x10000>; 1502 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1503 #address-cells = <1>; 1504 #size-cells = <1>; 1505 utmi-mode = <2>; 1506 ranges; 1507 status = "disabled"; 1508 usb3: usb@48910000 { 1509 compatible = "snps,dwc3"; 1510 reg = <0x48910000 0x17000>; 1511 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1514 interrupt-names = "peripheral", 1515 "host", 1516 "otg"; 1517 maximum-speed = "high-speed"; 1518 dr_mode = "otg"; 1519 snps,dis_u3_susphy_quirk; 1520 snps,dis_u2_susphy_quirk; 1521 }; 1522 }; 1523 1524 elm: elm@48078000 { 1525 compatible = "ti,am3352-elm"; 1526 reg = <0x48078000 0xfc0>; /* device IO registers */ 1527 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1528 ti,hwmods = "elm"; 1529 status = "disabled"; 1530 }; 1531 1532 gpmc: gpmc@50000000 { 1533 compatible = "ti,am3352-gpmc"; 1534 ti,hwmods = "gpmc"; 1535 reg = <0x50000000 0x37c>; /* device IO registers */ 1536 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1537 dmas = <&edma_xbar 4 0>; 1538 dma-names = "rxtx"; 1539 gpmc,num-cs = <8>; 1540 gpmc,num-waitpins = <2>; 1541 #address-cells = <2>; 1542 #size-cells = <1>; 1543 interrupt-controller; 1544 #interrupt-cells = <2>; 1545 gpio-controller; 1546 #gpio-cells = <2>; 1547 status = "disabled"; 1548 }; 1549 1550 atl: atl@4843c000 { 1551 compatible = "ti,dra7-atl"; 1552 reg = <0x4843c000 0x3ff>; 1553 ti,hwmods = "atl"; 1554 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, 1555 <&atl_clkin2_ck>, <&atl_clkin3_ck>; 1556 clocks = <&atl_gfclk_mux>; 1557 clock-names = "fck"; 1558 status = "disabled"; 1559 }; 1560 1561 mcasp1: mcasp@48460000 { 1562 compatible = "ti,dra7-mcasp-audio"; 1563 ti,hwmods = "mcasp1"; 1564 reg = <0x48460000 0x2000>, 1565 <0x45800000 0x1000>; 1566 reg-names = "mpu","dat"; 1567 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1568 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1569 interrupt-names = "tx", "rx"; 1570 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; 1571 dma-names = "tx", "rx"; 1572 clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>, 1573 <&mcasp1_ahclkr_mux>; 1574 clock-names = "fck", "ahclkx", "ahclkr"; 1575 status = "disabled"; 1576 }; 1577 1578 mcasp2: mcasp@48464000 { 1579 compatible = "ti,dra7-mcasp-audio"; 1580 ti,hwmods = "mcasp2"; 1581 reg = <0x48464000 0x2000>, 1582 <0x45c00000 0x1000>; 1583 reg-names = "mpu","dat"; 1584 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1586 interrupt-names = "tx", "rx"; 1587 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; 1588 dma-names = "tx", "rx"; 1589 clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>, 1590 <&mcasp2_ahclkr_mux>; 1591 clock-names = "fck", "ahclkx", "ahclkr"; 1592 status = "disabled"; 1593 }; 1594 1595 mcasp3: mcasp@48468000 { 1596 compatible = "ti,dra7-mcasp-audio"; 1597 ti,hwmods = "mcasp3"; 1598 reg = <0x48468000 0x2000>, 1599 <0x46000000 0x1000>; 1600 reg-names = "mpu","dat"; 1601 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1603 interrupt-names = "tx", "rx"; 1604 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; 1605 dma-names = "tx", "rx"; 1606 clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>; 1607 clock-names = "fck", "ahclkx"; 1608 status = "disabled"; 1609 }; 1610 1611 mcasp4: mcasp@4846c000 { 1612 compatible = "ti,dra7-mcasp-audio"; 1613 ti,hwmods = "mcasp4"; 1614 reg = <0x4846c000 0x2000>, 1615 <0x48436000 0x1000>; 1616 reg-names = "mpu","dat"; 1617 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1618 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1619 interrupt-names = "tx", "rx"; 1620 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; 1621 dma-names = "tx", "rx"; 1622 clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>; 1623 clock-names = "fck", "ahclkx"; 1624 status = "disabled"; 1625 }; 1626 1627 mcasp5: mcasp@48470000 { 1628 compatible = "ti,dra7-mcasp-audio"; 1629 ti,hwmods = "mcasp5"; 1630 reg = <0x48470000 0x2000>, 1631 <0x4843a000 0x1000>; 1632 reg-names = "mpu","dat"; 1633 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1635 interrupt-names = "tx", "rx"; 1636 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; 1637 dma-names = "tx", "rx"; 1638 clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>; 1639 clock-names = "fck", "ahclkx"; 1640 status = "disabled"; 1641 }; 1642 1643 mcasp6: mcasp@48474000 { 1644 compatible = "ti,dra7-mcasp-audio"; 1645 ti,hwmods = "mcasp6"; 1646 reg = <0x48474000 0x2000>, 1647 <0x4844c000 0x1000>; 1648 reg-names = "mpu","dat"; 1649 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1651 interrupt-names = "tx", "rx"; 1652 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; 1653 dma-names = "tx", "rx"; 1654 clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>; 1655 clock-names = "fck", "ahclkx"; 1656 status = "disabled"; 1657 }; 1658 1659 mcasp7: mcasp@48478000 { 1660 compatible = "ti,dra7-mcasp-audio"; 1661 ti,hwmods = "mcasp7"; 1662 reg = <0x48478000 0x2000>, 1663 <0x48450000 0x1000>; 1664 reg-names = "mpu","dat"; 1665 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1666 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1667 interrupt-names = "tx", "rx"; 1668 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; 1669 dma-names = "tx", "rx"; 1670 clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>; 1671 clock-names = "fck", "ahclkx"; 1672 status = "disabled"; 1673 }; 1674 1675 mcasp8: mcasp@4847c000 { 1676 compatible = "ti,dra7-mcasp-audio"; 1677 ti,hwmods = "mcasp8"; 1678 reg = <0x4847c000 0x2000>, 1679 <0x48454000 0x1000>; 1680 reg-names = "mpu","dat"; 1681 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1682 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1683 interrupt-names = "tx", "rx"; 1684 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; 1685 dma-names = "tx", "rx"; 1686 clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>; 1687 clock-names = "fck", "ahclkx"; 1688 status = "disabled"; 1689 }; 1690 1691 crossbar_mpu: crossbar@4a002a48 { 1692 compatible = "ti,irq-crossbar"; 1693 reg = <0x4a002a48 0x130>; 1694 interrupt-controller; 1695 interrupt-parent = <&wakeupgen>; 1696 #interrupt-cells = <3>; 1697 ti,max-irqs = <160>; 1698 ti,max-crossbar-sources = <MAX_SOURCES>; 1699 ti,reg-size = <2>; 1700 ti,irqs-reserved = <0 1 2 3 5 6 131 132>; 1701 ti,irqs-skip = <10 133 139 140>; 1702 ti,irqs-safe-map = <0>; 1703 }; 1704 1705 mac: ethernet@48484000 { 1706 compatible = "ti,dra7-cpsw","ti,cpsw"; 1707 ti,hwmods = "gmac"; 1708 clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>; 1709 clock-names = "fck", "cpts"; 1710 cpdma_channels = <8>; 1711 ale_entries = <1024>; 1712 bd_ram_size = <0x2000>; 1713 no_bd_ram = <0>; 1714 mac_control = <0x20>; 1715 slaves = <2>; 1716 active_slave = <0>; 1717 cpts_clock_mult = <0x784CFE14>; 1718 cpts_clock_shift = <29>; 1719 reg = <0x48484000 0x1000 1720 0x48485200 0x2E00>; 1721 #address-cells = <1>; 1722 #size-cells = <1>; 1723 1724 /* 1725 * Do not allow gating of cpsw clock as workaround 1726 * for errata i877. Keeping internal clock disabled 1727 * causes the device switching characteristics 1728 * to degrade over time and eventually fail to meet 1729 * the data manual delay time/skew specs. 1730 */ 1731 ti,no-idle; 1732 1733 /* 1734 * rx_thresh_pend 1735 * rx_pend 1736 * tx_pend 1737 * misc_pend 1738 */ 1739 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 1743 ranges; 1744 syscon = <&scm_conf>; 1745 status = "disabled"; 1746 1747 davinci_mdio: mdio@48485000 { 1748 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 1749 #address-cells = <1>; 1750 #size-cells = <0>; 1751 ti,hwmods = "davinci_mdio"; 1752 bus_freq = <1000000>; 1753 reg = <0x48485000 0x100>; 1754 }; 1755 1756 cpsw_emac0: slave@48480200 { 1757 /* Filled in by U-Boot */ 1758 mac-address = [ 00 00 00 00 00 00 ]; 1759 }; 1760 1761 cpsw_emac1: slave@48480300 { 1762 /* Filled in by U-Boot */ 1763 mac-address = [ 00 00 00 00 00 00 ]; 1764 }; 1765 1766 phy_sel: cpsw-phy-sel@4a002554 { 1767 compatible = "ti,dra7xx-cpsw-phy-sel"; 1768 reg= <0x4a002554 0x4>; 1769 reg-names = "gmii-sel"; 1770 }; 1771 }; 1772 1773 dcan1: can@481cc000 { 1774 compatible = "ti,dra7-d_can"; 1775 ti,hwmods = "dcan1"; 1776 reg = <0x4ae3c000 0x2000>; 1777 syscon-raminit = <&scm_conf 0x558 0>; 1778 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1779 clocks = <&dcan1_sys_clk_mux>; 1780 status = "disabled"; 1781 }; 1782 1783 dcan2: can@481d0000 { 1784 compatible = "ti,dra7-d_can"; 1785 ti,hwmods = "dcan2"; 1786 reg = <0x48480000 0x2000>; 1787 syscon-raminit = <&scm_conf 0x558 1>; 1788 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1789 clocks = <&sys_clkin1>; 1790 status = "disabled"; 1791 }; 1792 1793 dss: dss@58000000 { 1794 compatible = "ti,dra7-dss"; 1795 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ 1796 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ 1797 status = "disabled"; 1798 ti,hwmods = "dss_core"; 1799 /* CTRL_CORE_DSS_PLL_CONTROL */ 1800 syscon-pll-ctrl = <&scm_conf 0x538>; 1801 #address-cells = <1>; 1802 #size-cells = <1>; 1803 ranges; 1804 1805 dispc@58001000 { 1806 compatible = "ti,dra7-dispc"; 1807 reg = <0x58001000 0x1000>; 1808 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1809 ti,hwmods = "dss_dispc"; 1810 clocks = <&dss_dss_clk>; 1811 clock-names = "fck"; 1812 /* CTRL_CORE_SMA_SW_1 */ 1813 syscon-pol = <&scm_conf 0x534>; 1814 }; 1815 1816 hdmi: encoder@58060000 { 1817 compatible = "ti,dra7-hdmi"; 1818 reg = <0x58040000 0x200>, 1819 <0x58040200 0x80>, 1820 <0x58040300 0x80>, 1821 <0x58060000 0x19000>; 1822 reg-names = "wp", "pll", "phy", "core"; 1823 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1824 status = "disabled"; 1825 ti,hwmods = "dss_hdmi"; 1826 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>; 1827 clock-names = "fck", "sys_clk"; 1828 }; 1829 }; 1830 1831 epwmss0: epwmss@4843e000 { 1832 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 1833 reg = <0x4843e000 0x30>; 1834 ti,hwmods = "epwmss0"; 1835 #address-cells = <1>; 1836 #size-cells = <1>; 1837 status = "disabled"; 1838 ranges; 1839 1840 ehrpwm0: pwm@4843e200 { 1841 compatible = "ti,dra746-ehrpwm", 1842 "ti,am3352-ehrpwm"; 1843 #pwm-cells = <3>; 1844 reg = <0x4843e200 0x80>; 1845 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; 1846 clock-names = "tbclk", "fck"; 1847 status = "disabled"; 1848 }; 1849 1850 ecap0: ecap@4843e100 { 1851 compatible = "ti,dra746-ecap", 1852 "ti,am3352-ecap"; 1853 #pwm-cells = <3>; 1854 reg = <0x4843e100 0x80>; 1855 clocks = <&l4_root_clk_div>; 1856 clock-names = "fck"; 1857 status = "disabled"; 1858 }; 1859 }; 1860 1861 epwmss1: epwmss@48440000 { 1862 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 1863 reg = <0x48440000 0x30>; 1864 ti,hwmods = "epwmss1"; 1865 #address-cells = <1>; 1866 #size-cells = <1>; 1867 status = "disabled"; 1868 ranges; 1869 1870 ehrpwm1: pwm@48440200 { 1871 compatible = "ti,dra746-ehrpwm", 1872 "ti,am3352-ehrpwm"; 1873 #pwm-cells = <3>; 1874 reg = <0x48440200 0x80>; 1875 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; 1876 clock-names = "tbclk", "fck"; 1877 status = "disabled"; 1878 }; 1879 1880 ecap1: ecap@48440100 { 1881 compatible = "ti,dra746-ecap", 1882 "ti,am3352-ecap"; 1883 #pwm-cells = <3>; 1884 reg = <0x48440100 0x80>; 1885 clocks = <&l4_root_clk_div>; 1886 clock-names = "fck"; 1887 status = "disabled"; 1888 }; 1889 }; 1890 1891 epwmss2: epwmss@48442000 { 1892 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 1893 reg = <0x48442000 0x30>; 1894 ti,hwmods = "epwmss2"; 1895 #address-cells = <1>; 1896 #size-cells = <1>; 1897 status = "disabled"; 1898 ranges; 1899 1900 ehrpwm2: pwm@48442200 { 1901 compatible = "ti,dra746-ehrpwm", 1902 "ti,am3352-ehrpwm"; 1903 #pwm-cells = <3>; 1904 reg = <0x48442200 0x80>; 1905 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; 1906 clock-names = "tbclk", "fck"; 1907 status = "disabled"; 1908 }; 1909 1910 ecap2: ecap@48442100 { 1911 compatible = "ti,dra746-ecap", 1912 "ti,am3352-ecap"; 1913 #pwm-cells = <3>; 1914 reg = <0x48442100 0x80>; 1915 clocks = <&l4_root_clk_div>; 1916 clock-names = "fck"; 1917 status = "disabled"; 1918 }; 1919 }; 1920 1921 aes1: aes@4b500000 { 1922 compatible = "ti,omap4-aes"; 1923 ti,hwmods = "aes1"; 1924 reg = <0x4b500000 0xa0>; 1925 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1926 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; 1927 dma-names = "tx", "rx"; 1928 clocks = <&l3_iclk_div>; 1929 clock-names = "fck"; 1930 }; 1931 1932 aes2: aes@4b700000 { 1933 compatible = "ti,omap4-aes"; 1934 ti,hwmods = "aes2"; 1935 reg = <0x4b700000 0xa0>; 1936 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1937 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; 1938 dma-names = "tx", "rx"; 1939 clocks = <&l3_iclk_div>; 1940 clock-names = "fck"; 1941 }; 1942 1943 des: des@480a5000 { 1944 compatible = "ti,omap4-des"; 1945 ti,hwmods = "des"; 1946 reg = <0x480a5000 0xa0>; 1947 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1948 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>; 1949 dma-names = "tx", "rx"; 1950 clocks = <&l3_iclk_div>; 1951 clock-names = "fck"; 1952 }; 1953 1954 sham: sham@53100000 { 1955 compatible = "ti,omap5-sham"; 1956 ti,hwmods = "sham"; 1957 reg = <0x4b101000 0x300>; 1958 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1959 dmas = <&edma_xbar 119 0>; 1960 dma-names = "rx"; 1961 clocks = <&l3_iclk_div>; 1962 clock-names = "fck"; 1963 }; 1964 1965 rng: rng@48090000 { 1966 compatible = "ti,omap4-rng"; 1967 ti,hwmods = "rng"; 1968 reg = <0x48090000 0x2000>; 1969 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1970 clocks = <&l3_iclk_div>; 1971 clock-names = "fck"; 1972 }; 1973 }; 1974 1975 thermal_zones: thermal-zones { 1976 #include "omap4-cpu-thermal.dtsi" 1977 #include "omap5-gpu-thermal.dtsi" 1978 #include "omap5-core-thermal.dtsi" 1979 #include "dra7-dspeve-thermal.dtsi" 1980 #include "dra7-iva-thermal.dtsi" 1981 }; 1982 1983}; 1984 1985&cpu_thermal { 1986 polling-delay = <500>; /* milliseconds */ 1987}; 1988 1989/include/ "dra7xx-clocks.dtsi" 1990