1/* 2 * Samsung's Exynos4415 SoC device tree source 3 * 4 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 5 * 6 * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415 7 * based board files can include this file and provide values for board 8 * specific bindings. 9 * 10 * Note: This file does not include device nodes for all the controllers in 11 * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional 12 * nodes can be added to this file. 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 */ 18 19#include <dt-bindings/clock/exynos4415.h> 20#include <dt-bindings/clock/exynos-audss-clk.h> 21 22/ { 23 compatible = "samsung,exynos4415"; 24 interrupt-parent = <&gic>; 25 #address-cells = <1>; 26 #size-cells = <1>; 27 28 aliases { 29 pinctrl0 = &pinctrl_0; 30 pinctrl1 = &pinctrl_1; 31 pinctrl2 = &pinctrl_2; 32 mshc0 = &mshc_0; 33 mshc1 = &mshc_1; 34 mshc2 = &mshc_2; 35 spi0 = &spi_0; 36 spi1 = &spi_1; 37 spi2 = &spi_2; 38 i2c0 = &i2c_0; 39 i2c1 = &i2c_1; 40 i2c2 = &i2c_2; 41 i2c3 = &i2c_3; 42 i2c4 = &i2c_4; 43 i2c5 = &i2c_5; 44 i2c6 = &i2c_6; 45 i2c7 = &i2c_7; 46 }; 47 48 cpus { 49 #address-cells = <1>; 50 #size-cells = <0>; 51 52 cpu0: cpu@a00 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a9"; 55 reg = <0xa00>; 56 clock-frequency = <1600000000>; 57 }; 58 59 cpu1: cpu@a01 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a9"; 62 reg = <0xa01>; 63 clock-frequency = <1600000000>; 64 }; 65 66 cpu2: cpu@a02 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a9"; 69 reg = <0xa02>; 70 clock-frequency = <1600000000>; 71 }; 72 73 cpu3: cpu@a03 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a9"; 76 reg = <0xa03>; 77 clock-frequency = <1600000000>; 78 }; 79 }; 80 81 soc: soc { 82 compatible = "simple-bus"; 83 #address-cells = <1>; 84 #size-cells = <1>; 85 ranges; 86 87 sysram@02020000 { 88 compatible = "mmio-sram"; 89 reg = <0x02020000 0x50000>; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 ranges = <0 0x02020000 0x50000>; 93 94 smp-sysram@0 { 95 compatible = "samsung,exynos4210-sysram"; 96 reg = <0x0 0x1000>; 97 }; 98 99 smp-sysram@4f000 { 100 compatible = "samsung,exynos4210-sysram-ns"; 101 reg = <0x4f000 0x1000>; 102 }; 103 }; 104 105 pinctrl_2: pinctrl@03860000 { 106 compatible = "samsung,exynos4415-pinctrl"; 107 reg = <0x03860000 0x1000>; 108 interrupts = <0 242 0>; 109 }; 110 111 chipid@10000000 { 112 compatible = "samsung,exynos4210-chipid"; 113 reg = <0x10000000 0x100>; 114 }; 115 116 sysreg_system_controller: syscon@10010000 { 117 compatible = "samsung,exynos4-sysreg", "syscon"; 118 reg = <0x10010000 0x400>; 119 }; 120 121 pmu_system_controller: system-controller@10020000 { 122 compatible = "samsung,exynos4415-pmu", "syscon"; 123 reg = <0x10020000 0x4000>; 124 }; 125 126 mipi_phy: video-phy@10020710 { 127 compatible = "samsung,s5pv210-mipi-video-phy"; 128 #phy-cells = <1>; 129 syscon = <&pmu_system_controller>; 130 }; 131 132 pd_cam: cam-power-domain@10024000 { 133 compatible = "samsung,exynos4210-pd"; 134 reg = <0x10024000 0x20>; 135 #power-domain-cells = <0>; 136 }; 137 138 pd_tv: tv-power-domain@10024020 { 139 compatible = "samsung,exynos4210-pd"; 140 reg = <0x10024020 0x20>; 141 #power-domain-cells = <0>; 142 }; 143 144 pd_mfc: mfc-power-domain@10024040 { 145 compatible = "samsung,exynos4210-pd"; 146 reg = <0x10024040 0x20>; 147 #power-domain-cells = <0>; 148 }; 149 150 pd_g3d: g3d-power-domain@10024060 { 151 compatible = "samsung,exynos4210-pd"; 152 reg = <0x10024060 0x20>; 153 #power-domain-cells = <0>; 154 }; 155 156 pd_lcd0: lcd0-power-domain@10024080 { 157 compatible = "samsung,exynos4210-pd"; 158 reg = <0x10024080 0x20>; 159 #power-domain-cells = <0>; 160 }; 161 162 pd_isp0: isp0-power-domain@100240A0 { 163 compatible = "samsung,exynos4210-pd"; 164 reg = <0x100240A0 0x20>; 165 #power-domain-cells = <0>; 166 }; 167 168 pd_isp1: isp1-power-domain@100240E0 { 169 compatible = "samsung,exynos4210-pd"; 170 reg = <0x100240E0 0x20>; 171 #power-domain-cells = <0>; 172 }; 173 174 cmu: clock-controller@10030000 { 175 compatible = "samsung,exynos4415-cmu"; 176 reg = <0x10030000 0x18000>; 177 #clock-cells = <1>; 178 }; 179 180 rtc: rtc@10070000 { 181 compatible = "samsung,s3c6410-rtc"; 182 reg = <0x10070000 0x100>; 183 interrupts = <0 73 0>, <0 74 0>; 184 status = "disabled"; 185 }; 186 187 mct@10050000 { 188 compatible = "samsung,exynos4210-mct"; 189 reg = <0x10050000 0x800>; 190 interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>, 191 <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>; 192 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; 193 clock-names = "fin_pll", "mct"; 194 }; 195 196 gic: interrupt-controller@10481000 { 197 compatible = "arm,cortex-a9-gic"; 198 #interrupt-cells = <3>; 199 interrupt-controller; 200 reg = <0x10481000 0x1000>, 201 <0x10482000 0x1000>, 202 <0x10484000 0x2000>, 203 <0x10486000 0x2000>; 204 interrupts = <1 9 0xf04>; 205 }; 206 207 l2c: l2-cache-controller@10502000 { 208 compatible = "arm,pl310-cache"; 209 reg = <0x10502000 0x1000>; 210 cache-unified; 211 cache-level = <2>; 212 arm,tag-latency = <2 2 1>; 213 arm,data-latency = <3 2 1>; 214 arm,double-linefill = <1>; 215 arm,double-linefill-incr = <0>; 216 arm,double-linefill-wrap = <1>; 217 arm,prefetch-drop = <1>; 218 arm,prefetch-offset = <7>; 219 }; 220 221 cmu_dmc: clock-controller@105C0000 { 222 compatible = "samsung,exynos4415-cmu-dmc"; 223 reg = <0x105C0000 0x3000>; 224 #clock-cells = <1>; 225 }; 226 227 pinctrl_1: pinctrl@11000000 { 228 compatible = "samsung,exynos4415-pinctrl"; 229 reg = <0x11000000 0x1000>; 230 interrupts = <0 225 0>; 231 232 wakeup-interrupt-controller { 233 compatible = "samsung,exynos4210-wakeup-eint"; 234 interrupt-parent = <&gic>; 235 interrupts = <0 48 0>; 236 }; 237 }; 238 239 pinctrl_0: pinctrl@11400000 { 240 compatible = "samsung,exynos4415-pinctrl"; 241 reg = <0x11400000 0x1000>; 242 interrupts = <0 240 0>; 243 }; 244 245 fimd: fimd@11C00000 { 246 compatible = "samsung,exynos4415-fimd"; 247 reg = <0x11C00000 0x30000>; 248 interrupt-names = "fifo", "vsync", "lcd_sys"; 249 interrupts = <0 84 0>, <0 85 0>, <0 86 0>; 250 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; 251 clock-names = "sclk_fimd", "fimd"; 252 samsung,power-domain = <&pd_lcd0>; 253 iommus = <&sysmmu_fimd0>; 254 samsung,sysreg = <&sysreg_system_controller>; 255 status = "disabled"; 256 }; 257 258 dsi_0: dsi@11C80000 { 259 compatible = "samsung,exynos4415-mipi-dsi"; 260 reg = <0x11C80000 0x10000>; 261 interrupts = <0 83 0>; 262 samsung,phy-type = <0>; 263 samsung,power-domain = <&pd_lcd0>; 264 phys = <&mipi_phy 1>; 265 phy-names = "dsim"; 266 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; 267 clock-names = "bus_clk", "pll_clk"; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 status = "disabled"; 271 }; 272 273 sysmmu_fimd0: sysmmu@11E20000 { 274 compatible = "samsung,exynos-sysmmu"; 275 reg = <0x11e20000 0x1000>; 276 interrupts = <0 80 0>, <0 81 0>; 277 clock-names = "sysmmu", "master"; 278 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; 279 power-domains = <&pd_lcd0>; 280 #iommu-cells = <0>; 281 }; 282 283 hsotg: hsotg@12480000 { 284 compatible = "samsung,s3c6400-hsotg"; 285 reg = <0x12480000 0x20000>; 286 interrupts = <0 141 0>; 287 clocks = <&cmu CLK_USBDEVICE>; 288 clock-names = "otg"; 289 phys = <&exynos_usbphy 0>; 290 phy-names = "usb2-phy"; 291 status = "disabled"; 292 }; 293 294 mshc_0: mshc@12510000 { 295 compatible = "samsung,exynos5250-dw-mshc"; 296 reg = <0x12510000 0x1000>; 297 interrupts = <0 142 0>; 298 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; 299 clock-names = "biu", "ciu"; 300 fifo-depth = <0x80>; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 status = "disabled"; 304 }; 305 306 mshc_1: mshc@12520000 { 307 compatible = "samsung,exynos5250-dw-mshc"; 308 reg = <0x12520000 0x1000>; 309 interrupts = <0 143 0>; 310 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; 311 clock-names = "biu", "ciu"; 312 fifo-depth = <0x80>; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 status = "disabled"; 316 }; 317 318 mshc_2: mshc@12530000 { 319 compatible = "samsung,exynos5250-dw-mshc"; 320 reg = <0x12530000 0x1000>; 321 interrupts = <0 144 0>; 322 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; 323 clock-names = "biu", "ciu"; 324 fifo-depth = <0x80>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 status = "disabled"; 328 }; 329 330 ehci: ehci@12580000 { 331 compatible = "samsung,exynos4210-ehci"; 332 reg = <0x12580000 0x100>; 333 interrupts = <0 140 0>; 334 clocks = <&cmu CLK_USBHOST>; 335 clock-names = "usbhost"; 336 status = "disabled"; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 port@0 { 340 reg = <0>; 341 phys = <&exynos_usbphy 1>; 342 status = "disabled"; 343 }; 344 port@1 { 345 reg = <1>; 346 phys = <&exynos_usbphy 2>; 347 status = "disabled"; 348 }; 349 port@2 { 350 reg = <2>; 351 phys = <&exynos_usbphy 3>; 352 status = "disabled"; 353 }; 354 }; 355 356 ohci: ohci@12590000 { 357 compatible = "samsung,exynos4210-ohci"; 358 reg = <0x12590000 0x100>; 359 interrupts = <0 140 0>; 360 clocks = <&cmu CLK_USBHOST>; 361 clock-names = "usbhost"; 362 status = "disabled"; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 port@0 { 366 reg = <0>; 367 phys = <&exynos_usbphy 1>; 368 status = "disabled"; 369 }; 370 }; 371 372 exynos_usbphy: exynos-usbphy@125B0000 { 373 compatible = "samsung,exynos4x12-usb2-phy"; 374 reg = <0x125B0000 0x100>; 375 samsung,pmureg-phandle = <&pmu_system_controller>; 376 samsung,sysreg-phandle = <&sysreg_system_controller>; 377 clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>; 378 clock-names = "phy", "ref"; 379 #phy-cells = <1>; 380 status = "disabled"; 381 }; 382 383 amba { 384 compatible = "simple-bus"; 385 #address-cells = <1>; 386 #size-cells = <1>; 387 interrupt-parent = <&gic>; 388 ranges; 389 390 pdma0: pdma@12680000 { 391 compatible = "arm,pl330", "arm,primecell"; 392 reg = <0x12680000 0x1000>; 393 interrupts = <0 138 0>; 394 clocks = <&cmu CLK_PDMA0>; 395 clock-names = "apb_pclk"; 396 #dma-cells = <1>; 397 #dma-channels = <8>; 398 #dma-requests = <32>; 399 }; 400 401 pdma1: pdma@12690000 { 402 compatible = "arm,pl330", "arm,primecell"; 403 reg = <0x12690000 0x1000>; 404 interrupts = <0 139 0>; 405 clocks = <&cmu CLK_PDMA1>; 406 clock-names = "apb_pclk"; 407 #dma-cells = <1>; 408 #dma-channels = <8>; 409 #dma-requests = <32>; 410 }; 411 }; 412 413 adc: adc@126C0000 { 414 compatible = "samsung,exynos3250-adc", 415 "samsung,exynos-adc-v2"; 416 reg = <0x126C0000 0x100>, <0x10020718 0x4>; 417 interrupts = <0 137 0>; 418 clock-names = "adc", "sclk"; 419 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; 420 #io-channel-cells = <1>; 421 io-channel-ranges; 422 status = "disabled"; 423 }; 424 425 serial_0: serial@13800000 { 426 compatible = "samsung,exynos4210-uart"; 427 reg = <0x13800000 0x100>; 428 interrupts = <0 109 0>; 429 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; 430 clock-names = "uart", "clk_uart_baud0"; 431 status = "disabled"; 432 }; 433 434 serial_1: serial@13810000 { 435 compatible = "samsung,exynos4210-uart"; 436 reg = <0x13810000 0x100>; 437 interrupts = <0 110 0>; 438 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; 439 clock-names = "uart", "clk_uart_baud0"; 440 status = "disabled"; 441 }; 442 443 serial_2: serial@13820000 { 444 compatible = "samsung,exynos4210-uart"; 445 reg = <0x13820000 0x100>; 446 interrupts = <0 111 0>; 447 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; 448 clock-names = "uart", "clk_uart_baud0"; 449 status = "disabled"; 450 }; 451 452 serial_3: serial@13830000 { 453 compatible = "samsung,exynos4210-uart"; 454 reg = <0x13830000 0x100>; 455 interrupts = <0 112 0>; 456 clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>; 457 clock-names = "uart", "clk_uart_baud0"; 458 status = "disabled"; 459 }; 460 461 i2c_0: i2c@13860000 { 462 #address-cells = <1>; 463 #size-cells = <0>; 464 compatible = "samsung,s3c2440-i2c"; 465 reg = <0x13860000 0x100>; 466 interrupts = <0 113 0>; 467 clocks = <&cmu CLK_I2C0>; 468 clock-names = "i2c"; 469 pinctrl-names = "default"; 470 pinctrl-0 = <&i2c0_bus>; 471 status = "disabled"; 472 }; 473 474 i2c_1: i2c@13870000 { 475 #address-cells = <1>; 476 #size-cells = <0>; 477 compatible = "samsung,s3c2440-i2c"; 478 reg = <0x13870000 0x100>; 479 interrupts = <0 114 0>; 480 clocks = <&cmu CLK_I2C1>; 481 clock-names = "i2c"; 482 pinctrl-names = "default"; 483 pinctrl-0 = <&i2c1_bus>; 484 status = "disabled"; 485 }; 486 487 i2c_2: i2c@13880000 { 488 #address-cells = <1>; 489 #size-cells = <0>; 490 compatible = "samsung,s3c2440-i2c"; 491 reg = <0x13880000 0x100>; 492 interrupts = <0 115 0>; 493 clocks = <&cmu CLK_I2C2>; 494 clock-names = "i2c"; 495 pinctrl-names = "default"; 496 pinctrl-0 = <&i2c2_bus>; 497 status = "disabled"; 498 }; 499 500 i2c_3: i2c@13890000 { 501 #address-cells = <1>; 502 #size-cells = <0>; 503 compatible = "samsung,s3c2440-i2c"; 504 reg = <0x13890000 0x100>; 505 interrupts = <0 116 0>; 506 clocks = <&cmu CLK_I2C3>; 507 clock-names = "i2c"; 508 pinctrl-names = "default"; 509 pinctrl-0 = <&i2c3_bus>; 510 status = "disabled"; 511 }; 512 513 i2c_4: i2c@138A0000 { 514 #address-cells = <1>; 515 #size-cells = <0>; 516 compatible = "samsung,s3c2440-i2c"; 517 reg = <0x138A0000 0x100>; 518 interrupts = <0 117 0>; 519 clocks = <&cmu CLK_I2C4>; 520 clock-names = "i2c"; 521 pinctrl-names = "default"; 522 pinctrl-0 = <&i2c4_bus>; 523 status = "disabled"; 524 }; 525 526 i2c_5: i2c@138B0000 { 527 #address-cells = <1>; 528 #size-cells = <0>; 529 compatible = "samsung,s3c2440-i2c"; 530 reg = <0x138B0000 0x100>; 531 interrupts = <0 118 0>; 532 clocks = <&cmu CLK_I2C5>; 533 clock-names = "i2c"; 534 pinctrl-names = "default"; 535 pinctrl-0 = <&i2c5_bus>; 536 status = "disabled"; 537 }; 538 539 i2c_6: i2c@138C0000 { 540 #address-cells = <1>; 541 #size-cells = <0>; 542 compatible = "samsung,s3c2440-i2c"; 543 reg = <0x138C0000 0x100>; 544 interrupts = <0 119 0>; 545 clocks = <&cmu CLK_I2C6>; 546 clock-names = "i2c"; 547 pinctrl-names = "default"; 548 pinctrl-0 = <&i2c6_bus>; 549 status = "disabled"; 550 }; 551 552 i2c_7: i2c@138D0000 { 553 #address-cells = <1>; 554 #size-cells = <0>; 555 compatible = "samsung,s3c2440-i2c"; 556 reg = <0x138D0000 0x100>; 557 interrupts = <0 120 0>; 558 clocks = <&cmu CLK_I2C7>; 559 clock-names = "i2c"; 560 pinctrl-names = "default"; 561 pinctrl-0 = <&i2c7_bus>; 562 status = "disabled"; 563 }; 564 565 spi_0: spi@13920000 { 566 compatible = "samsung,exynos4210-spi"; 567 reg = <0x13920000 0x100>; 568 interrupts = <0 121 0>; 569 dmas = <&pdma0 7>, <&pdma0 6>; 570 dma-names = "tx", "rx"; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; 574 clock-names = "spi", "spi_busclk0"; 575 samsung,spi-src-clk = <0>; 576 pinctrl-names = "default"; 577 pinctrl-0 = <&spi0_bus>; 578 status = "disabled"; 579 }; 580 581 spi_1: spi@13930000 { 582 compatible = "samsung,exynos4210-spi"; 583 reg = <0x13930000 0x100>; 584 interrupts = <0 122 0>; 585 dmas = <&pdma1 7>, <&pdma1 6>; 586 dma-names = "tx", "rx"; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; 590 clock-names = "spi", "spi_busclk0"; 591 samsung,spi-src-clk = <0>; 592 pinctrl-names = "default"; 593 pinctrl-0 = <&spi1_bus>; 594 status = "disabled"; 595 }; 596 597 spi_2: spi@13940000 { 598 compatible = "samsung,exynos4210-spi"; 599 reg = <0x13940000 0x100>; 600 interrupts = <0 123 0>; 601 dmas = <&pdma0 9>, <&pdma0 8>; 602 dma-names = "tx", "rx"; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>; 606 clock-names = "spi", "spi_busclk0"; 607 samsung,spi-src-clk = <0>; 608 pinctrl-names = "default"; 609 pinctrl-0 = <&spi2_bus>; 610 status = "disabled"; 611 }; 612 613 clock_audss: clock-controller@03810000 { 614 compatible = "samsung,exynos4210-audss-clock"; 615 reg = <0x03810000 0x0C>; 616 #clock-cells = <1>; 617 }; 618 619 i2s0: i2s@3830000 { 620 compatible = "samsung,s5pv210-i2s"; 621 reg = <0x03830000 0x100>; 622 interrupts = <0 124 0>; 623 clocks = <&clock_audss EXYNOS_I2S_BUS>, 624 <&clock_audss EXYNOS_SCLK_I2S>; 625 clock-names = "iis", "i2s_opclk0"; 626 dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>; 627 dma-names = "tx", "rx", "tx-sec"; 628 pinctrl-names = "default"; 629 pinctrl-0 = <&i2s0_bus>; 630 samsung,idma-addr = <0x03000000>; 631 status = "disabled"; 632 }; 633 634 pwm: pwm@139D0000 { 635 compatible = "samsung,exynos4210-pwm"; 636 reg = <0x139D0000 0x1000>; 637 interrupts = <0 104 0>, <0 105 0>, <0 106 0>, 638 <0 107 0>, <0 108 0>; 639 #pwm-cells = <3>; 640 status = "disabled"; 641 }; 642 643 pmu { 644 compatible = "arm,cortex-a9-pmu"; 645 interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>; 646 }; 647 }; 648}; 649 650#include "exynos4415-pinctrl.dtsi" 651