1/* 2 * Samsung's Exynos4x12 SoCs device tree source 3 * 4 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * 7 * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12 8 * based board files can include this file and provide values for board specfic 9 * bindings. 10 * 11 * Note: This file does not include device nodes for all the controllers in 12 * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional 13 * nodes can be added to this file. 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License version 2 as 17 * published by the Free Software Foundation. 18*/ 19 20#include "exynos4.dtsi" 21#include "exynos4x12-pinctrl.dtsi" 22#include "exynos4-cpu-thermal.dtsi" 23 24/ { 25 aliases { 26 pinctrl0 = &pinctrl_0; 27 pinctrl1 = &pinctrl_1; 28 pinctrl2 = &pinctrl_2; 29 pinctrl3 = &pinctrl_3; 30 fimc-lite0 = &fimc_lite_0; 31 fimc-lite1 = &fimc_lite_1; 32 mshc0 = &mshc_0; 33 }; 34 35 sysram@02020000 { 36 compatible = "mmio-sram"; 37 reg = <0x02020000 0x40000>; 38 #address-cells = <1>; 39 #size-cells = <1>; 40 ranges = <0 0x02020000 0x40000>; 41 42 smp-sysram@0 { 43 compatible = "samsung,exynos4210-sysram"; 44 reg = <0x0 0x1000>; 45 }; 46 47 smp-sysram@2f000 { 48 compatible = "samsung,exynos4210-sysram-ns"; 49 reg = <0x2f000 0x1000>; 50 }; 51 }; 52 53 pd_isp: isp-power-domain@10023CA0 { 54 compatible = "samsung,exynos4210-pd"; 55 reg = <0x10023CA0 0x20>; 56 #power-domain-cells = <0>; 57 }; 58 59 l2c: l2-cache-controller@10502000 { 60 compatible = "arm,pl310-cache"; 61 reg = <0x10502000 0x1000>; 62 cache-unified; 63 cache-level = <2>; 64 arm,tag-latency = <2 2 1>; 65 arm,data-latency = <3 2 1>; 66 arm,double-linefill = <1>; 67 arm,double-linefill-incr = <0>; 68 arm,double-linefill-wrap = <1>; 69 arm,prefetch-drop = <1>; 70 arm,prefetch-offset = <7>; 71 }; 72 73 clock: clock-controller@10030000 { 74 compatible = "samsung,exynos4412-clock"; 75 reg = <0x10030000 0x20000>; 76 #clock-cells = <1>; 77 }; 78 79 mct@10050000 { 80 compatible = "samsung,exynos4412-mct"; 81 reg = <0x10050000 0x800>; 82 interrupt-parent = <&mct_map>; 83 interrupts = <0>, <1>, <2>, <3>, <4>; 84 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; 85 clock-names = "fin_pll", "mct"; 86 87 mct_map: mct-map { 88 #interrupt-cells = <1>; 89 #address-cells = <0>; 90 #size-cells = <0>; 91 interrupt-map = <0 &gic 0 57 0>, 92 <1 &combiner 12 5>, 93 <2 &combiner 12 6>, 94 <3 &combiner 12 7>, 95 <4 &gic 1 12 0>; 96 }; 97 }; 98 99 adc: adc@126C0000 { 100 compatible = "samsung,exynos-adc-v1"; 101 reg = <0x126C0000 0x100>; 102 interrupt-parent = <&combiner>; 103 interrupts = <10 3>; 104 clocks = <&clock CLK_TSADC>; 105 clock-names = "adc"; 106 #io-channel-cells = <1>; 107 io-channel-ranges; 108 samsung,syscon-phandle = <&pmu_system_controller>; 109 status = "disabled"; 110 }; 111 112 g2d: g2d@10800000 { 113 compatible = "samsung,exynos4212-g2d"; 114 reg = <0x10800000 0x1000>; 115 interrupts = <0 89 0>; 116 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; 117 clock-names = "sclk_fimg2d", "fimg2d"; 118 iommus = <&sysmmu_g2d>; 119 }; 120 121 camera { 122 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, 123 <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; 124 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; 125 126 /* fimc_[0-3] are configured outside, under phandles */ 127 fimc_lite_0: fimc-lite@12390000 { 128 compatible = "samsung,exynos4212-fimc-lite"; 129 reg = <0x12390000 0x1000>; 130 interrupts = <0 105 0>; 131 power-domains = <&pd_isp>; 132 clocks = <&clock CLK_FIMC_LITE0>; 133 clock-names = "flite"; 134 iommus = <&sysmmu_fimc_lite0>; 135 status = "disabled"; 136 }; 137 138 fimc_lite_1: fimc-lite@123A0000 { 139 compatible = "samsung,exynos4212-fimc-lite"; 140 reg = <0x123A0000 0x1000>; 141 interrupts = <0 106 0>; 142 power-domains = <&pd_isp>; 143 clocks = <&clock CLK_FIMC_LITE1>; 144 clock-names = "flite"; 145 iommus = <&sysmmu_fimc_lite1>; 146 status = "disabled"; 147 }; 148 149 fimc_is: fimc-is@12000000 { 150 compatible = "samsung,exynos4212-fimc-is", "simple-bus"; 151 reg = <0x12000000 0x260000>; 152 interrupts = <0 90 0>, <0 95 0>; 153 power-domains = <&pd_isp>; 154 clocks = <&clock CLK_FIMC_LITE0>, 155 <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>, 156 <&clock CLK_PPMUISPMX>, 157 <&clock CLK_MOUT_MPLL_USER_T>, 158 <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>, 159 <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>, 160 <&clock CLK_GICISP>, <&clock CLK_MCUCTL_ISP>, 161 <&clock CLK_PWM_ISP>, 162 <&clock CLK_DIV_ISP0>, <&clock CLK_DIV_ISP1>, 163 <&clock CLK_DIV_MCUISP0>, 164 <&clock CLK_DIV_MCUISP1>, 165 <&clock CLK_UART_ISP_SCLK>, 166 <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>, 167 <&clock CLK_ACLK400_MCUISP>, 168 <&clock CLK_DIV_ACLK400_MCUISP>; 169 clock-names = "lite0", "lite1", "ppmuispx", 170 "ppmuispmx", "mpll", "isp", 171 "drc", "fd", "mcuisp", 172 "gicisp", "mcuctl_isp", "pwm_isp", 173 "ispdiv0", "ispdiv1", "mcuispdiv0", 174 "mcuispdiv1", "uart", "aclk200", 175 "div_aclk200", "aclk400mcuisp", 176 "div_aclk400mcuisp"; 177 iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, 178 <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; 179 iommu-names = "isp", "drc", "fd", "mcuctl"; 180 #address-cells = <1>; 181 #size-cells = <1>; 182 ranges; 183 status = "disabled"; 184 185 pmu@10020000 { 186 reg = <0x10020000 0x3000>; 187 }; 188 189 i2c1_isp: i2c-isp@12140000 { 190 compatible = "samsung,exynos4212-i2c-isp"; 191 reg = <0x12140000 0x100>; 192 clocks = <&clock CLK_I2C1_ISP>; 193 clock-names = "i2c_isp"; 194 #address-cells = <1>; 195 #size-cells = <0>; 196 }; 197 }; 198 }; 199 200 mshc_0: mmc@12550000 { 201 compatible = "samsung,exynos4412-dw-mshc"; 202 reg = <0x12550000 0x1000>; 203 interrupts = <0 77 0>; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 fifo-depth = <0x80>; 207 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; 208 clock-names = "biu", "ciu"; 209 status = "disabled"; 210 }; 211 212 sysmmu_g2d: sysmmu@10A40000{ 213 compatible = "samsung,exynos-sysmmu"; 214 reg = <0x10A40000 0x1000>; 215 interrupt-parent = <&combiner>; 216 interrupts = <4 7>; 217 clock-names = "sysmmu", "master"; 218 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; 219 #iommu-cells = <0>; 220 }; 221 222 sysmmu_fimc_isp: sysmmu@12260000 { 223 compatible = "samsung,exynos-sysmmu"; 224 reg = <0x12260000 0x1000>; 225 interrupt-parent = <&combiner>; 226 interrupts = <16 2>; 227 power-domains = <&pd_isp>; 228 clock-names = "sysmmu"; 229 clocks = <&clock CLK_SMMU_ISP>; 230 #iommu-cells = <0>; 231 }; 232 233 sysmmu_fimc_drc: sysmmu@12270000 { 234 compatible = "samsung,exynos-sysmmu"; 235 reg = <0x12270000 0x1000>; 236 interrupt-parent = <&combiner>; 237 interrupts = <16 3>; 238 power-domains = <&pd_isp>; 239 clock-names = "sysmmu"; 240 clocks = <&clock CLK_SMMU_DRC>; 241 #iommu-cells = <0>; 242 }; 243 244 sysmmu_fimc_fd: sysmmu@122A0000 { 245 compatible = "samsung,exynos-sysmmu"; 246 reg = <0x122A0000 0x1000>; 247 interrupt-parent = <&combiner>; 248 interrupts = <16 4>; 249 power-domains = <&pd_isp>; 250 clock-names = "sysmmu"; 251 clocks = <&clock CLK_SMMU_FD>; 252 #iommu-cells = <0>; 253 }; 254 255 sysmmu_fimc_mcuctl: sysmmu@122B0000 { 256 compatible = "samsung,exynos-sysmmu"; 257 reg = <0x122B0000 0x1000>; 258 interrupt-parent = <&combiner>; 259 interrupts = <16 5>; 260 power-domains = <&pd_isp>; 261 clock-names = "sysmmu"; 262 clocks = <&clock CLK_SMMU_ISPCX>; 263 #iommu-cells = <0>; 264 }; 265 266 sysmmu_fimc_lite0: sysmmu@123B0000 { 267 compatible = "samsung,exynos-sysmmu"; 268 reg = <0x123B0000 0x1000>; 269 interrupt-parent = <&combiner>; 270 interrupts = <16 0>; 271 power-domains = <&pd_isp>; 272 clock-names = "sysmmu", "master"; 273 clocks = <&clock CLK_SMMU_LITE0>, <&clock CLK_FIMC_LITE0>; 274 #iommu-cells = <0>; 275 }; 276 277 sysmmu_fimc_lite1: sysmmu@123C0000 { 278 compatible = "samsung,exynos-sysmmu"; 279 reg = <0x123C0000 0x1000>; 280 interrupt-parent = <&combiner>; 281 interrupts = <16 1>; 282 power-domains = <&pd_isp>; 283 clock-names = "sysmmu", "master"; 284 clocks = <&clock CLK_SMMU_LITE1>, <&clock CLK_FIMC_LITE1>; 285 #iommu-cells = <0>; 286 }; 287 288 bus_dmc: bus_dmc { 289 compatible = "samsung,exynos-bus"; 290 clocks = <&clock CLK_DIV_DMC>; 291 clock-names = "bus"; 292 operating-points-v2 = <&bus_dmc_opp_table>; 293 status = "disabled"; 294 }; 295 296 bus_acp: bus_acp { 297 compatible = "samsung,exynos-bus"; 298 clocks = <&clock CLK_DIV_ACP>; 299 clock-names = "bus"; 300 operating-points-v2 = <&bus_acp_opp_table>; 301 status = "disabled"; 302 }; 303 304 bus_c2c: bus_c2c { 305 compatible = "samsung,exynos-bus"; 306 clocks = <&clock CLK_DIV_C2C>; 307 clock-names = "bus"; 308 operating-points-v2 = <&bus_dmc_opp_table>; 309 status = "disabled"; 310 }; 311 312 bus_dmc_opp_table: opp_table1 { 313 compatible = "operating-points-v2"; 314 opp-shared; 315 316 opp@100000000 { 317 opp-hz = /bits/ 64 <100000000>; 318 opp-microvolt = <900000>; 319 }; 320 opp@134000000 { 321 opp-hz = /bits/ 64 <134000000>; 322 opp-microvolt = <900000>; 323 }; 324 opp@160000000 { 325 opp-hz = /bits/ 64 <160000000>; 326 opp-microvolt = <900000>; 327 }; 328 opp@267000000 { 329 opp-hz = /bits/ 64 <267000000>; 330 opp-microvolt = <950000>; 331 }; 332 opp@400000000 { 333 opp-hz = /bits/ 64 <400000000>; 334 opp-microvolt = <1050000>; 335 }; 336 }; 337 338 bus_acp_opp_table: opp_table2 { 339 compatible = "operating-points-v2"; 340 opp-shared; 341 342 opp@100000000 { 343 opp-hz = /bits/ 64 <100000000>; 344 }; 345 opp@134000000 { 346 opp-hz = /bits/ 64 <134000000>; 347 }; 348 opp@160000000 { 349 opp-hz = /bits/ 64 <160000000>; 350 }; 351 opp@267000000 { 352 opp-hz = /bits/ 64 <267000000>; 353 }; 354 }; 355 356 bus_leftbus: bus_leftbus { 357 compatible = "samsung,exynos-bus"; 358 clocks = <&clock CLK_DIV_GDL>; 359 clock-names = "bus"; 360 operating-points-v2 = <&bus_leftbus_opp_table>; 361 status = "disabled"; 362 }; 363 364 bus_rightbus: bus_rightbus { 365 compatible = "samsung,exynos-bus"; 366 clocks = <&clock CLK_DIV_GDR>; 367 clock-names = "bus"; 368 operating-points-v2 = <&bus_leftbus_opp_table>; 369 status = "disabled"; 370 }; 371 372 bus_display: bus_display { 373 compatible = "samsung,exynos-bus"; 374 clocks = <&clock CLK_ACLK160>; 375 clock-names = "bus"; 376 operating-points-v2 = <&bus_display_opp_table>; 377 status = "disabled"; 378 }; 379 380 bus_fsys: bus_fsys { 381 compatible = "samsung,exynos-bus"; 382 clocks = <&clock CLK_ACLK133>; 383 clock-names = "bus"; 384 operating-points-v2 = <&bus_fsys_opp_table>; 385 status = "disabled"; 386 }; 387 388 bus_peri: bus_peri { 389 compatible = "samsung,exynos-bus"; 390 clocks = <&clock CLK_ACLK100>; 391 clock-names = "bus"; 392 operating-points-v2 = <&bus_peri_opp_table>; 393 status = "disabled"; 394 }; 395 396 bus_mfc: bus_mfc { 397 compatible = "samsung,exynos-bus"; 398 clocks = <&clock CLK_SCLK_MFC>; 399 clock-names = "bus"; 400 operating-points-v2 = <&bus_leftbus_opp_table>; 401 status = "disabled"; 402 }; 403 404 bus_leftbus_opp_table: opp_table3 { 405 compatible = "operating-points-v2"; 406 opp-shared; 407 408 opp@100000000 { 409 opp-hz = /bits/ 64 <100000000>; 410 opp-microvolt = <900000>; 411 }; 412 opp@134000000 { 413 opp-hz = /bits/ 64 <134000000>; 414 opp-microvolt = <925000>; 415 }; 416 opp@160000000 { 417 opp-hz = /bits/ 64 <160000000>; 418 opp-microvolt = <950000>; 419 }; 420 opp@200000000 { 421 opp-hz = /bits/ 64 <200000000>; 422 opp-microvolt = <1000000>; 423 }; 424 }; 425 426 bus_display_opp_table: opp_table4 { 427 compatible = "operating-points-v2"; 428 opp-shared; 429 430 opp@160000000 { 431 opp-hz = /bits/ 64 <160000000>; 432 }; 433 opp@200000000 { 434 opp-hz = /bits/ 64 <200000000>; 435 }; 436 }; 437 438 bus_fsys_opp_table: opp_table5 { 439 compatible = "operating-points-v2"; 440 opp-shared; 441 442 opp@100000000 { 443 opp-hz = /bits/ 64 <100000000>; 444 }; 445 opp@134000000 { 446 opp-hz = /bits/ 64 <134000000>; 447 }; 448 }; 449 450 bus_peri_opp_table: opp_table6 { 451 compatible = "operating-points-v2"; 452 opp-shared; 453 454 opp@50000000 { 455 opp-hz = /bits/ 64 <50000000>; 456 }; 457 opp@100000000 { 458 opp-hz = /bits/ 64 <100000000>; 459 }; 460 }; 461}; 462 463&combiner { 464 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, 465 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, 466 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, 467 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, 468 <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>; 469}; 470 471&exynos_usbphy { 472 compatible = "samsung,exynos4x12-usb2-phy"; 473 samsung,sysreg-phandle = <&sys_reg>; 474}; 475 476&fimc_0 { 477 compatible = "samsung,exynos4212-fimc"; 478 samsung,pix-limits = <4224 8192 1920 4224>; 479 samsung,mainscaler-ext; 480 samsung,isp-wb; 481 samsung,cam-if; 482}; 483 484&fimc_1 { 485 compatible = "samsung,exynos4212-fimc"; 486 samsung,pix-limits = <4224 8192 1920 4224>; 487 samsung,mainscaler-ext; 488 samsung,isp-wb; 489 samsung,cam-if; 490}; 491 492&fimc_2 { 493 compatible = "samsung,exynos4212-fimc"; 494 samsung,pix-limits = <4224 8192 1920 4224>; 495 samsung,mainscaler-ext; 496 samsung,isp-wb; 497 samsung,lcd-wb; 498 samsung,cam-if; 499}; 500 501&fimc_3 { 502 compatible = "samsung,exynos4212-fimc"; 503 samsung,pix-limits = <1920 8192 1366 1920>; 504 samsung,rotators = <0>; 505 samsung,mainscaler-ext; 506 samsung,isp-wb; 507 samsung,lcd-wb; 508}; 509 510&hdmi { 511 compatible = "samsung,exynos4212-hdmi"; 512}; 513 514&jpeg_codec { 515 compatible = "samsung,exynos4212-jpeg"; 516}; 517 518&rotator { 519 compatible = "samsung,exynos4212-rotator"; 520}; 521 522&mixer { 523 compatible = "samsung,exynos4212-mixer"; 524 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp"; 525 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, 526 <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; 527}; 528 529&pinctrl_0 { 530 compatible = "samsung,exynos4x12-pinctrl"; 531 reg = <0x11400000 0x1000>; 532 interrupts = <0 47 0>; 533}; 534 535&pinctrl_1 { 536 compatible = "samsung,exynos4x12-pinctrl"; 537 reg = <0x11000000 0x1000>; 538 interrupts = <0 46 0>; 539 540 wakup_eint: wakeup-interrupt-controller { 541 compatible = "samsung,exynos4210-wakeup-eint"; 542 interrupt-parent = <&gic>; 543 interrupts = <0 32 0>; 544 }; 545}; 546 547&pinctrl_2 { 548 compatible = "samsung,exynos4x12-pinctrl"; 549 reg = <0x03860000 0x1000>; 550 interrupt-parent = <&combiner>; 551 interrupts = <10 0>; 552}; 553 554&pinctrl_3 { 555 compatible = "samsung,exynos4x12-pinctrl"; 556 reg = <0x106E0000 0x1000>; 557 interrupts = <0 72 0>; 558}; 559 560&pmu_system_controller { 561 compatible = "samsung,exynos4212-pmu", "syscon"; 562 clock-names = "clkout0", "clkout1", "clkout2", "clkout3", 563 "clkout4", "clkout8", "clkout9"; 564 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, 565 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, 566 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; 567 #clock-cells = <1>; 568}; 569 570&tmu { 571 compatible = "samsung,exynos4412-tmu"; 572 interrupt-parent = <&combiner>; 573 interrupts = <2 4>; 574 reg = <0x100C0000 0x100>; 575 clocks = <&clock 383>; 576 clock-names = "tmu_apbif"; 577 status = "disabled"; 578}; 579