1/* 2 * Copyright 2014-2016 Toradex AG 3 * Copyright 2012 Freescale Semiconductor, Inc. 4 * Copyright 2011 Linaro Ltd. 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License 13 * version 2 as published by the Free Software Foundation. 14 * 15 * This file is distributed in the hope that it will be useful 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * Or, alternatively 21 * 22 * b) Permission is hereby granted, free of charge, to any person 23 * obtaining a copy of this software and associated documentation 24 * files (the "Software"), to deal in the Software without 25 * restriction, including without limitation the rights to use 26 * copy, modify, merge, publish, distribute, sublicense, and/or 27 * sell copies of the Software, and to permit persons to whom the 28 * Software is furnished to do so, subject to the following 29 * conditions: 30 * 31 * The above copyright notice and this permission notice shall be 32 * included in all copies or substantial portions of the Software. 33 * 34 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41 * OTHER DEALINGS IN THE SOFTWARE. 42 */ 43 44#include <dt-bindings/gpio/gpio.h> 45 46/ { 47 model = "Toradex Apalis iMX6Q/D Module"; 48 compatible = "toradex,apalis_imx6q", "fsl,imx6q"; 49 50 backlight: backlight { 51 compatible = "pwm-backlight"; 52 pwms = <&pwm4 0 5000000>; 53 status = "disabled"; 54 }; 55 56 /* DDC_I2C: I2C2_SDA/SCL on MXM3 205/207 */ 57 i2cddc: i2c@0 { 58 compatible = "i2c-gpio"; 59 pinctrl-names = "default"; 60 pinctrl-0 = <&pinctrl_i2c_ddc>; 61 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH /* sda */ 62 &gpio2 30 GPIO_ACTIVE_HIGH /* scl */ 63 >; 64 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 65 status = "disabled"; 66 }; 67 68 reg_1p8v: regulator-1p8v { 69 compatible = "regulator-fixed"; 70 regulator-name = "1P8V"; 71 regulator-min-microvolt = <1800000>; 72 regulator-max-microvolt = <1800000>; 73 regulator-always-on; 74 }; 75 76 reg_2p5v: regulator-2p5v { 77 compatible = "regulator-fixed"; 78 regulator-name = "2P5V"; 79 regulator-min-microvolt = <2500000>; 80 regulator-max-microvolt = <2500000>; 81 regulator-always-on; 82 }; 83 84 reg_3p3v: regulator-3p3v { 85 compatible = "regulator-fixed"; 86 regulator-name = "3P3V"; 87 regulator-min-microvolt = <3300000>; 88 regulator-max-microvolt = <3300000>; 89 regulator-always-on; 90 }; 91 92 reg_usb_otg_vbus: regulator-usb-otg-vbus { 93 compatible = "regulator-fixed"; 94 pinctrl-names = "default"; 95 pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>; 96 regulator-name = "usb_otg_vbus"; 97 regulator-min-microvolt = <5000000>; 98 regulator-max-microvolt = <5000000>; 99 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 100 enable-active-high; 101 status = "disabled"; 102 }; 103 104 /* on module USB hub */ 105 reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub { 106 compatible = "regulator-fixed"; 107 pinctrl-names = "default"; 108 pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>; 109 regulator-name = "usb_host_vbus_hub"; 110 regulator-min-microvolt = <5000000>; 111 regulator-max-microvolt = <5000000>; 112 gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; 113 startup-delay-us = <2000>; 114 enable-active-high; 115 status = "okay"; 116 }; 117 118 reg_usb_host_vbus: regulator-usb-host-vbus { 119 compatible = "regulator-fixed"; 120 pinctrl-names = "default"; 121 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; 122 regulator-name = "usb_host_vbus"; 123 regulator-min-microvolt = <5000000>; 124 regulator-max-microvolt = <5000000>; 125 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; 126 enable-active-high; 127 vin-supply = <®_usb_host_vbus_hub>; 128 status = "disabled"; 129 }; 130 131 sound { 132 compatible = "fsl,imx-audio-sgtl5000"; 133 model = "imx6q-apalis-sgtl5000"; 134 ssi-controller = <&ssi1>; 135 audio-codec = <&codec>; 136 audio-routing = 137 "LINE_IN", "Line In Jack", 138 "MIC_IN", "Mic Jack", 139 "Mic Jack", "Mic Bias", 140 "Headphone Jack", "HP_OUT"; 141 mux-int-port = <1>; 142 mux-ext-port = <4>; 143 }; 144 145 sound_spdif: sound-spdif { 146 compatible = "fsl,imx-audio-spdif"; 147 model = "imx-spdif"; 148 spdif-controller = <&spdif>; 149 spdif-in; 150 spdif-out; 151 status = "disabled"; 152 }; 153}; 154 155&audmux { 156 pinctrl-names = "default"; 157 pinctrl-0 = <&pinctrl_audmux>; 158 status = "okay"; 159}; 160 161&can1 { 162 pinctrl-names = "default"; 163 pinctrl-0 = <&pinctrl_flexcan1>; 164 status = "disabled"; 165}; 166 167&can2 { 168 pinctrl-names = "default"; 169 pinctrl-0 = <&pinctrl_flexcan2>; 170 status = "disabled"; 171}; 172 173/* Apalis SPI1 */ 174&ecspi1 { 175 fsl,spi-num-chipselects = <1>; 176 cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_ecspi1>; 179 status = "disabled"; 180}; 181 182/* Apalis SPI2 */ 183&ecspi2 { 184 fsl,spi-num-chipselects = <1>; 185 cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; 186 pinctrl-names = "default"; 187 pinctrl-0 = <&pinctrl_ecspi2>; 188 status = "disabled"; 189}; 190 191&fec { 192 pinctrl-names = "default"; 193 pinctrl-0 = <&pinctrl_enet>; 194 phy-mode = "rgmii"; 195 phy-handle = <ðphy>; 196 phy-reset-duration = <10>; 197 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 198 status = "okay"; 199 200 mdio { 201 #address-cells = <1>; 202 #size-cells = <0>; 203 204 ethphy: ethernet-phy@7 { 205 interrupt-parent = <&gpio1>; 206 interrupts = <30 IRQ_TYPE_LEVEL_LOW>; 207 reg = <7>; 208 }; 209 }; 210}; 211 212/* 213 * GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier 214 * board) 215 */ 216&i2c1 { 217 clock-frequency = <100000>; 218 pinctrl-names = "default"; 219 pinctrl-0 = <&pinctrl_i2c1>; 220 status = "disabled"; 221}; 222 223/* 224 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 225 * touch screen controller 226 */ 227&i2c2 { 228 clock-frequency = <100000>; 229 pinctrl-names = "default"; 230 pinctrl-0 = <&pinctrl_i2c2>; 231 status = "okay"; 232 233 pmic: pfuze100@08 { 234 compatible = "fsl,pfuze100"; 235 reg = <0x08>; 236 237 regulators { 238 sw1a_reg: sw1ab { 239 regulator-min-microvolt = <300000>; 240 regulator-max-microvolt = <1875000>; 241 regulator-boot-on; 242 regulator-always-on; 243 regulator-ramp-delay = <6250>; 244 }; 245 246 sw1c_reg: sw1c { 247 regulator-min-microvolt = <300000>; 248 regulator-max-microvolt = <1875000>; 249 regulator-boot-on; 250 regulator-always-on; 251 regulator-ramp-delay = <6250>; 252 }; 253 254 sw3a_reg: sw3a { 255 regulator-min-microvolt = <400000>; 256 regulator-max-microvolt = <1975000>; 257 regulator-boot-on; 258 regulator-always-on; 259 }; 260 261 swbst_reg: swbst { 262 regulator-min-microvolt = <5000000>; 263 regulator-max-microvolt = <5150000>; 264 regulator-boot-on; 265 regulator-always-on; 266 }; 267 268 snvs_reg: vsnvs { 269 regulator-min-microvolt = <1000000>; 270 regulator-max-microvolt = <3000000>; 271 regulator-boot-on; 272 regulator-always-on; 273 }; 274 275 vref_reg: vrefddr { 276 regulator-boot-on; 277 regulator-always-on; 278 }; 279 280 vgen1_reg: vgen1 { 281 regulator-min-microvolt = <800000>; 282 regulator-max-microvolt = <1550000>; 283 regulator-boot-on; 284 regulator-always-on; 285 }; 286 287 vgen2_reg: vgen2 { 288 regulator-min-microvolt = <800000>; 289 regulator-max-microvolt = <1550000>; 290 regulator-boot-on; 291 regulator-always-on; 292 }; 293 294 vgen3_reg: vgen3 { 295 regulator-min-microvolt = <1800000>; 296 regulator-max-microvolt = <3300000>; 297 regulator-boot-on; 298 regulator-always-on; 299 }; 300 301 vgen4_reg: vgen4 { 302 regulator-min-microvolt = <1800000>; 303 regulator-max-microvolt = <3300000>; 304 regulator-boot-on; 305 regulator-always-on; 306 }; 307 308 vgen5_reg: vgen5 { 309 regulator-min-microvolt = <1800000>; 310 regulator-max-microvolt = <3300000>; 311 regulator-boot-on; 312 regulator-always-on; 313 }; 314 315 vgen6_reg: vgen6 { 316 regulator-min-microvolt = <1800000>; 317 regulator-max-microvolt = <3300000>; 318 regulator-boot-on; 319 regulator-always-on; 320 }; 321 }; 322 }; 323 324 codec: sgtl5000@0a { 325 compatible = "fsl,sgtl5000"; 326 reg = <0x0a>; 327 clocks = <&clks IMX6QDL_CLK_CKO>; 328 VDDA-supply = <®_2p5v>; 329 VDDIO-supply = <®_3p3v>; 330 }; 331 332 /* STMPE811 touch screen controller */ 333 stmpe811@41 { 334 compatible = "st,stmpe811"; 335 pinctrl-names = "default"; 336 pinctrl-0 = <&pinctrl_touch_int>; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 reg = <0x41>; 340 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 341 interrupt-parent = <&gpio4>; 342 interrupt-controller; 343 id = <0>; 344 blocks = <0x5>; 345 irq-trigger = <0x1>; 346 347 stmpe_touchscreen { 348 compatible = "st,stmpe-ts"; 349 reg = <0>; 350 /* 3.25 MHz ADC clock speed */ 351 st,adc-freq = <1>; 352 /* 8 sample average control */ 353 st,ave-ctrl = <3>; 354 /* 7 length fractional part in z */ 355 st,fraction-z = <7>; 356 /* 357 * 50 mA typical 80 mA max touchscreen drivers 358 * current limit value 359 */ 360 st,i-drive = <1>; 361 /* 12-bit ADC */ 362 st,mod-12b = <1>; 363 /* internal ADC reference */ 364 st,ref-sel = <0>; 365 /* ADC converstion time: 80 clocks */ 366 st,sample-time = <4>; 367 /* 1 ms panel driver settling time */ 368 st,settling = <3>; 369 /* 5 ms touch detect interrupt delay */ 370 st,touch-det-delay = <5>; 371 }; 372 }; 373}; 374 375/* 376 * GEN2_I2C, CAM: I2C3_SDA/SCL on MXM3 201/203 (unused) 377 */ 378&i2c3 { 379 clock-frequency = <100000>; 380 pinctrl-names = "default", "recovery"; 381 pinctrl-0 = <&pinctrl_i2c3>; 382 pinctrl-1 = <&pinctrl_i2c3_recovery>; 383 scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; 384 sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; 385 status = "disabled"; 386}; 387 388&pwm1 { 389 pinctrl-names = "default"; 390 pinctrl-0 = <&pinctrl_pwm1>; 391 status = "disabled"; 392}; 393 394&pwm2 { 395 pinctrl-names = "default"; 396 pinctrl-0 = <&pinctrl_pwm2>; 397 status = "disabled"; 398}; 399 400&pwm3 { 401 pinctrl-names = "default"; 402 pinctrl-0 = <&pinctrl_pwm3>; 403 status = "disabled"; 404}; 405 406&pwm4 { 407 pinctrl-names = "default"; 408 pinctrl-0 = <&pinctrl_pwm4>; 409 status = "disabled"; 410}; 411 412&spdif { 413 pinctrl-names = "default"; 414 pinctrl-0 = <&pinctrl_spdif>; 415 status = "disabled"; 416}; 417 418&ssi1 { 419 status = "okay"; 420}; 421 422&uart1 { 423 pinctrl-names = "default"; 424 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; 425 fsl,dte-mode; 426 uart-has-rtscts; 427 status = "disabled"; 428}; 429 430&uart2 { 431 pinctrl-names = "default"; 432 pinctrl-0 = <&pinctrl_uart2_dte>; 433 fsl,dte-mode; 434 uart-has-rtscts; 435 status = "disabled"; 436}; 437 438&uart4 { 439 pinctrl-names = "default"; 440 pinctrl-0 = <&pinctrl_uart4_dte>; 441 fsl,dte-mode; 442 status = "disabled"; 443}; 444 445&uart5 { 446 pinctrl-names = "default"; 447 pinctrl-0 = <&pinctrl_uart5_dte>; 448 fsl,dte-mode; 449 status = "disabled"; 450}; 451 452&usbotg { 453 pinctrl-names = "default"; 454 pinctrl-0 = <&pinctrl_usbotg>; 455 disable-over-current; 456 status = "disabled"; 457}; 458 459/* MMC1 */ 460&usdhc1 { 461 pinctrl-names = "default"; 462 pinctrl-0 = <&pinctrl_usdhc1>; 463 vqmmc-supply = <®_3p3v>; 464 bus-width = <8>; 465 voltage-ranges = <3300 3300>; 466 status = "disabled"; 467}; 468 469/* SD1 */ 470&usdhc2 { 471 pinctrl-names = "default"; 472 pinctrl-0 = <&pinctrl_usdhc2>; 473 vqmmc-supply = <®_3p3v>; 474 bus-width = <4>; 475 voltage-ranges = <3300 3300>; 476 status = "disabled"; 477}; 478 479/* eMMC */ 480&usdhc3 { 481 pinctrl-names = "default"; 482 pinctrl-0 = <&pinctrl_usdhc3>; 483 vqmmc-supply = <®_3p3v>; 484 bus-width = <8>; 485 voltage-ranges = <3300 3300>; 486 non-removable; 487 status = "okay"; 488}; 489 490&weim { 491 status = "disabled"; 492}; 493 494&iomuxc { 495 /* pins used on module */ 496 pinctrl-names = "default"; 497 pinctrl-0 = <&pinctrl_reset_moci>; 498 499 pinctrl_apalis_gpio1: gpio2io04grp { 500 fsl,pins = < 501 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0 502 >; 503 }; 504 505 pinctrl_apalis_gpio2: gpio2io05grp { 506 fsl,pins = < 507 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0 508 >; 509 }; 510 511 pinctrl_apalis_gpio3: gpio2io06grp { 512 fsl,pins = < 513 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0 514 >; 515 }; 516 517 pinctrl_apalis_gpio4: gpio2io07grp { 518 fsl,pins = < 519 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0 520 >; 521 }; 522 523 pinctrl_apalis_gpio5: gpio6io10grp { 524 fsl,pins = < 525 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0 526 >; 527 }; 528 529 pinctrl_apalis_gpio6: gpio6io09grp { 530 fsl,pins = < 531 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0 532 >; 533 }; 534 535 pinctrl_apalis_gpio7: gpio1io02grp { 536 fsl,pins = < 537 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0 538 >; 539 }; 540 541 pinctrl_apalis_gpio8: gpio1io06grp { 542 fsl,pins = < 543 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0 544 >; 545 }; 546 547 pinctrl_audmux: audmuxgrp { 548 fsl,pins = < 549 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 550 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 551 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 552 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 553 /* SGTL5000 sys_mclk */ 554 MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 555 >; 556 }; 557 558 pinctrl_cam_mclk: cammclkgrp { 559 fsl,pins = < 560 /* CAM sys_mclk */ 561 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 562 >; 563 }; 564 565 pinctrl_ecspi1: ecspi1grp { 566 fsl,pins = < 567 MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1 568 MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1 569 MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1 570 /* SPI1 cs */ 571 MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1 572 >; 573 }; 574 575 pinctrl_ecspi2: ecspi2grp { 576 fsl,pins = < 577 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 578 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 579 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 580 /* SPI2 cs */ 581 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 582 >; 583 }; 584 585 pinctrl_enet: enetgrp { 586 fsl,pins = < 587 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 588 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 589 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 590 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 591 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 592 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 593 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 594 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 595 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 596 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 597 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 598 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 599 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 600 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 601 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 602 /* Ethernet PHY reset */ 603 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 604 /* Ethernet PHY interrupt */ 605 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1 606 >; 607 }; 608 609 pinctrl_flexcan1: flexcan1grp { 610 fsl,pins = < 611 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 612 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 613 >; 614 }; 615 616 pinctrl_flexcan2: flexcan2grp { 617 fsl,pins = < 618 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 619 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 620 >; 621 }; 622 623 pinctrl_gpio_keys: gpio1io04grp { 624 fsl,pins = < 625 /* Power button */ 626 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 627 >; 628 }; 629 630 pinctrl_hdmi_cec: hdmicecgrp { 631 fsl,pins = < 632 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 633 >; 634 }; 635 636 pinctrl_i2c_ddc: gpioi2cddcgrp { 637 fsl,pins = < 638 /* DDC bitbang */ 639 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 640 MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 641 >; 642 }; 643 644 pinctrl_i2c1: i2c1grp { 645 fsl,pins = < 646 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 647 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 648 >; 649 }; 650 651 pinctrl_i2c2: i2c2grp { 652 fsl,pins = < 653 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 654 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 655 >; 656 }; 657 658 pinctrl_i2c3: i2c3grp { 659 fsl,pins = < 660 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 661 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 662 >; 663 }; 664 665 pinctrl_i2c3_recovery: i2c3recoverygrp { 666 fsl,pins = < 667 MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1 668 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1 669 >; 670 }; 671 672 pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */ 673 fsl,pins = < 674 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1 675 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1 676 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1 677 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1 678 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1 679 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1 680 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1 681 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1 682 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 683 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1 684 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1 685 >; 686 }; 687 688 pinctrl_ipu1_lcdif: ipu1lcdifgrp { 689 fsl,pins = < 690 MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61 691 /* DE */ 692 MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61 693 /* HSync */ 694 MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61 695 /* VSync */ 696 MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61 697 MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61 698 MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61 699 MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61 700 MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61 701 MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61 702 MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61 703 MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61 704 MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61 705 MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61 706 MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61 707 MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61 708 MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61 709 MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61 710 MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61 711 MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61 712 MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61 713 MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61 714 MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61 715 MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61 716 MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61 717 MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61 718 MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61 719 MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61 720 MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61 721 >; 722 }; 723 724 pinctrl_ipu2_vdac: ipu2vdacgrp { 725 fsl,pins = < 726 MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1 727 MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1 728 MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1 729 MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1 730 MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9 731 MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9 732 MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9 733 MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9 734 MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9 735 MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9 736 MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9 737 MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9 738 MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9 739 MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9 740 MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9 741 MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9 742 MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9 743 MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9 744 MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9 745 MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9 746 >; 747 }; 748 749 pinctrl_mmc_cd: gpiommccdgrp { 750 fsl,pins = < 751 /* MMC1 CD */ 752 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0 753 >; 754 }; 755 756 pinctrl_pwm1: pwm1grp { 757 fsl,pins = < 758 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 759 >; 760 }; 761 762 pinctrl_pwm2: pwm2grp { 763 fsl,pins = < 764 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 765 >; 766 }; 767 768 pinctrl_pwm3: pwm3grp { 769 fsl,pins = < 770 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 771 >; 772 }; 773 774 pinctrl_pwm4: pwm4grp { 775 fsl,pins = < 776 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 777 >; 778 }; 779 780 pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp { 781 fsl,pins = < 782 /* USBH_EN */ 783 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058 784 >; 785 }; 786 787 pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp { 788 fsl,pins = < 789 /* USBH_HUB_EN */ 790 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058 791 >; 792 }; 793 794 pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp { 795 fsl,pins = < 796 /* USBO1 power en */ 797 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058 798 >; 799 }; 800 801 pinctrl_reset_moci: gpioresetmocigrp { 802 fsl,pins = < 803 /* RESET_MOCI control */ 804 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058 805 >; 806 }; 807 808 pinctrl_sd_cd: gpiosdcdgrp { 809 fsl,pins = < 810 /* SD1 CD */ 811 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0 812 >; 813 }; 814 815 pinctrl_spdif: spdifgrp { 816 fsl,pins = < 817 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 818 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 819 >; 820 }; 821 822 pinctrl_touch_int: gpiotouchintgrp { 823 fsl,pins = < 824 /* STMPE811 interrupt */ 825 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 826 >; 827 }; 828 829 pinctrl_uart1_dce: uart1dcegrp { 830 fsl,pins = < 831 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 832 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 833 >; 834 }; 835 836 /* DTE mode */ 837 pinctrl_uart1_dte: uart1dtegrp { 838 fsl,pins = < 839 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 840 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 841 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 842 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 843 >; 844 }; 845 846 /* Additional DTR, DSR, DCD */ 847 pinctrl_uart1_ctrl: uart1ctrlgrp { 848 fsl,pins = < 849 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 850 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 851 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 852 >; 853 }; 854 855 pinctrl_uart2_dce: uart2dcegrp { 856 fsl,pins = < 857 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 858 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 859 >; 860 }; 861 862 /* DTE mode */ 863 pinctrl_uart2_dte: uart2dtegrp { 864 fsl,pins = < 865 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 866 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 867 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 868 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 869 >; 870 }; 871 872 pinctrl_uart4_dce: uart4dcegrp { 873 fsl,pins = < 874 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 875 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 876 >; 877 }; 878 879 /* DTE mode */ 880 pinctrl_uart4_dte: uart4dtegrp { 881 fsl,pins = < 882 MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1 883 MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1 884 >; 885 }; 886 887 pinctrl_uart5_dce: uart5dcegrp { 888 fsl,pins = < 889 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 890 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 891 >; 892 }; 893 894 /* DTE mode */ 895 pinctrl_uart5_dte: uart5dtegrp { 896 fsl,pins = < 897 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 898 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 899 >; 900 }; 901 902 pinctrl_usbotg: usbotggrp { 903 fsl,pins = < 904 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 905 >; 906 }; 907 908 pinctrl_usdhc1: usdhc1grp { 909 fsl,pins = < 910 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 911 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 912 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 913 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 914 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 915 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 916 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 917 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 918 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071 919 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071 920 >; 921 }; 922 923 pinctrl_usdhc2: usdhc2grp { 924 fsl,pins = < 925 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 926 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 927 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 928 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 929 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 930 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 931 >; 932 }; 933 934 pinctrl_usdhc3: usdhc3grp { 935 fsl,pins = < 936 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 937 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 938 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 939 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 940 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 941 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 942 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 943 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 944 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 945 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 946 /* eMMC reset */ 947 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 948 >; 949 }; 950 951 pinctrl_usdhc3_100mhz: usdhc3100mhzgrp { 952 fsl,pins = < 953 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 954 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 955 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 956 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 957 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 958 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 959 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 960 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 961 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 962 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 963 /* eMMC reset */ 964 MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9 965 >; 966 }; 967 968 pinctrl_usdhc3_200mhz: usdhc3200mhzgrp { 969 fsl,pins = < 970 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 971 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 972 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 973 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 974 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 975 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 976 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 977 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 978 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 979 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 980 /* eMMC reset */ 981 MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9 982 >; 983 }; 984}; 985