1/* 2 * Copyright 2013 Texas Instruments, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/gpio/gpio.h> 11 12#include "skeleton.dtsi" 13 14/ { 15 compatible = "ti,keystone"; 16 model = "Texas Instruments Keystone 2 SoC"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 interrupt-parent = <&gic>; 20 21 aliases { 22 serial0 = &uart0; 23 spi0 = &spi0; 24 spi1 = &spi1; 25 spi2 = &spi2; 26 }; 27 28 memory { 29 reg = <0x00000000 0x80000000 0x00000000 0x40000000>; 30 }; 31 32 gic: interrupt-controller { 33 compatible = "arm,cortex-a15-gic"; 34 #interrupt-cells = <3>; 35 interrupt-controller; 36 reg = <0x0 0x02561000 0x0 0x1000>, 37 <0x0 0x02562000 0x0 0x2000>, 38 <0x0 0x02564000 0x0 0x1000>, 39 <0x0 0x02566000 0x0 0x2000>; 40 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 41 IRQ_TYPE_LEVEL_HIGH)>; 42 }; 43 44 timer { 45 compatible = "arm,armv7-timer"; 46 interrupts = 47 <GIC_PPI 13 48 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 49 <GIC_PPI 14 50 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 11 52 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 53 <GIC_PPI 10 54 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 55 }; 56 57 pmu { 58 compatible = "arm,cortex-a15-pmu"; 59 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>, 60 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 61 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>, 62 <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; 63 }; 64 65 psci { 66 compatible = "arm,psci"; 67 method = "smc"; 68 cpu_suspend = <0x84000001>; 69 cpu_off = <0x84000002>; 70 cpu_on = <0x84000003>; 71 }; 72 73 soc { 74 #address-cells = <1>; 75 #size-cells = <1>; 76 compatible = "ti,keystone","simple-bus"; 77 interrupt-parent = <&gic>; 78 ranges = <0x0 0x0 0x0 0xc0000000>; 79 dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; 80 81 pllctrl: pll-controller@02310000 { 82 compatible = "ti,keystone-pllctrl", "syscon"; 83 reg = <0x02310000 0x200>; 84 }; 85 86 devctrl: device-state-control@02620000 { 87 compatible = "ti,keystone-devctrl", "syscon"; 88 reg = <0x02620000 0x1000>; 89 }; 90 91 rstctrl: reset-controller { 92 compatible = "ti,keystone-reset"; 93 ti,syscon-pll = <&pllctrl 0xe4>; 94 ti,syscon-dev = <&devctrl 0x328>; 95 ti,wdt-list = <0>; 96 }; 97 98 /include/ "keystone-clocks.dtsi" 99 100 uart0: serial@02530c00 { 101 compatible = "ns16550a"; 102 current-speed = <115200>; 103 reg-shift = <2>; 104 reg-io-width = <4>; 105 reg = <0x02530c00 0x100>; 106 clocks = <&clkuart0>; 107 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 108 }; 109 110 uart1: serial@02531000 { 111 compatible = "ns16550a"; 112 current-speed = <115200>; 113 reg-shift = <2>; 114 reg-io-width = <4>; 115 reg = <0x02531000 0x100>; 116 clocks = <&clkuart1>; 117 interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>; 118 }; 119 120 i2c0: i2c@2530000 { 121 compatible = "ti,davinci-i2c"; 122 reg = <0x02530000 0x400>; 123 clock-frequency = <100000>; 124 clocks = <&clki2c>; 125 interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>; 126 #address-cells = <1>; 127 #size-cells = <0>; 128 }; 129 130 i2c1: i2c@2530400 { 131 compatible = "ti,davinci-i2c"; 132 reg = <0x02530400 0x400>; 133 clock-frequency = <100000>; 134 clocks = <&clki2c>; 135 interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>; 136 #address-cells = <1>; 137 #size-cells = <0>; 138 }; 139 140 i2c2: i2c@2530800 { 141 compatible = "ti,davinci-i2c"; 142 reg = <0x02530800 0x400>; 143 clock-frequency = <100000>; 144 clocks = <&clki2c>; 145 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 }; 149 150 spi0: spi@21000400 { 151 compatible = "ti,keystone-spi", "ti,dm6441-spi"; 152 reg = <0x21000400 0x200>; 153 num-cs = <4>; 154 ti,davinci-spi-intr-line = <0>; 155 interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>; 156 clocks = <&clkspi>; 157 #address-cells = <1>; 158 #size-cells = <0>; 159 }; 160 161 spi1: spi@21000600 { 162 compatible = "ti,keystone-spi", "ti,dm6441-spi"; 163 reg = <0x21000600 0x200>; 164 num-cs = <4>; 165 ti,davinci-spi-intr-line = <0>; 166 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>; 167 clocks = <&clkspi>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 }; 171 172 spi2: spi@21000800 { 173 compatible = "ti,keystone-spi", "ti,dm6441-spi"; 174 reg = <0x21000800 0x200>; 175 num-cs = <4>; 176 ti,davinci-spi-intr-line = <0>; 177 interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>; 178 clocks = <&clkspi>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 }; 182 183 usb_phy: usb_phy@2620738 { 184 compatible = "ti,keystone-usbphy"; 185 #address-cells = <1>; 186 #size-cells = <1>; 187 reg = <0x2620738 24>; 188 status = "disabled"; 189 }; 190 191 keystone_usb0: usb@2680000 { 192 compatible = "ti,keystone-dwc3"; 193 #address-cells = <1>; 194 #size-cells = <1>; 195 reg = <0x2680000 0x10000>; 196 clocks = <&clkusb>; 197 clock-names = "usb"; 198 interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>; 199 ranges; 200 dma-coherent; 201 dma-ranges; 202 status = "disabled"; 203 204 usb0: dwc3@2690000 { 205 compatible = "synopsys,dwc3"; 206 reg = <0x2690000 0x70000>; 207 interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>; 208 usb-phy = <&usb_phy>, <&usb_phy>; 209 }; 210 }; 211 212 wdt: wdt@022f0080 { 213 compatible = "ti,keystone-wdt","ti,davinci-wdt"; 214 reg = <0x022f0080 0x80>; 215 clocks = <&clkwdtimer0>; 216 }; 217 218 clock_event: timer@22f0000 { 219 compatible = "ti,keystone-timer"; 220 reg = <0x022f0000 0x80>; 221 interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>; 222 clocks = <&clktimer15>; 223 }; 224 225 gpio0: gpio@260bf00 { 226 compatible = "ti,keystone-gpio"; 227 reg = <0x0260bf00 0x100>; 228 gpio-controller; 229 #gpio-cells = <2>; 230 /* HW Interrupts mapped to GPIO pins */ 231 interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>, 232 <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, 233 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 234 <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>, 235 <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, 236 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 237 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 238 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 239 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 240 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 241 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 242 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 243 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 244 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 245 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 246 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 247 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 248 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 249 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 250 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 251 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>, 252 <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 253 <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>, 254 <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>, 255 <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>, 256 <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, 257 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>, 258 <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>, 259 <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>, 260 <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 261 <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>, 262 <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; 263 clocks = <&clkgpio>; 264 clock-names = "gpio"; 265 ti,ngpio = <32>; 266 ti,davinci-gpio-unbanked = <32>; 267 }; 268 269 aemif: aemif@21000A00 { 270 compatible = "ti,keystone-aemif", "ti,davinci-aemif"; 271 #address-cells = <2>; 272 #size-cells = <1>; 273 clocks = <&clkaemif>; 274 clock-names = "aemif"; 275 clock-ranges; 276 277 reg = <0x21000A00 0x00000100>; 278 ranges = <0 0 0x30000000 0x10000000 279 1 0 0x21000A00 0x00000100>; 280 }; 281 282 kirq0: keystone_irq@26202a0 { 283 compatible = "ti,keystone-irq"; 284 interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; 285 interrupt-controller; 286 #interrupt-cells = <1>; 287 ti,syscon-dev = <&devctrl 0x2a0>; 288 }; 289 290 pcie0: pcie@21800000 { 291 compatible = "ti,keystone-pcie", "snps,dw-pcie"; 292 clocks = <&clkpcie>; 293 clock-names = "pcie"; 294 #address-cells = <3>; 295 #size-cells = <2>; 296 reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; 297 ranges = <0x82000000 0 0x50000000 0x50000000 298 0 0x10000000>; 299 300 status = "disabled"; 301 device_type = "pci"; 302 num-lanes = <2>; 303 bus-range = <0x00 0xff>; 304 305 /* error interrupt */ 306 interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>; 307 #interrupt-cells = <1>; 308 interrupt-map-mask = <0 0 0 7>; 309 interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */ 310 <0 0 0 2 &pcie_intc0 1>, /* INT B */ 311 <0 0 0 3 &pcie_intc0 2>, /* INT C */ 312 <0 0 0 4 &pcie_intc0 3>; /* INT D */ 313 314 pcie_msi_intc0: msi-interrupt-controller { 315 interrupt-controller; 316 #interrupt-cells = <1>; 317 interrupt-parent = <&gic>; 318 interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 319 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, 320 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 321 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 322 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 323 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 324 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 325 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>; 326 }; 327 328 pcie_intc0: legacy-interrupt-controller { 329 interrupt-controller; 330 #interrupt-cells = <1>; 331 interrupt-parent = <&gic>; 332 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, 333 <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, 334 <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, 335 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>; 336 }; 337 }; 338 }; 339}; 340