1/* 2 * kirkwood-pogoplug-series-4.dts - Device tree file for PogoPlug Series 4 3 * inspired by the board files made by Kevin Mihelich for ArchLinux, 4 * and their DTS file. 5 * 6 * Copyright (C) 2015 Linus Walleij <linus.walleij@linaro.org> 7 */ 8 9/dts-v1/; 10 11#include "kirkwood.dtsi" 12#include "kirkwood-6192.dtsi" 13#include <dt-bindings/input/linux-event-codes.h> 14 15/ { 16 model = "Cloud Engines PogoPlug Series 4"; 17 compatible = "cloudengines,pogoplugv4", "marvell,kirkwood-88f6192", 18 "marvell,kirkwood"; 19 20 memory { 21 device_type = "memory"; 22 reg = <0x00000000 0x08000000>; 23 }; 24 25 chosen { 26 stdout-path = "uart0:115200n8"; 27 }; 28 29 gpio_keys { 30 compatible = "gpio-keys"; 31 #address-cells = <1>; 32 #size-cells = <0>; 33 pinctrl-0 = <&pmx_button_eject>; 34 pinctrl-names = "default"; 35 36 eject { 37 debounce_interval = <50>; 38 wakeup-source; 39 linux,code = <KEY_EJECTCD>; 40 label = "Eject Button"; 41 gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; 42 }; 43 }; 44 45 gpio-leds { 46 compatible = "gpio-leds"; 47 pinctrl-0 = <&pmx_led_green &pmx_led_red>; 48 pinctrl-names = "default"; 49 50 health { 51 label = "pogoplugv4:green:health"; 52 gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; 53 default-state = "on"; 54 }; 55 fault { 56 label = "pogoplugv4:red:fault"; 57 gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; 58 }; 59 }; 60}; 61 62&pinctrl { 63 pmx_sata0: pmx-sata0 { 64 marvell,pins = "mpp21"; 65 marvell,function = "sata0"; 66 }; 67 68 pmx_sata1: pmx-sata1 { 69 marvell,pins = "mpp20"; 70 marvell,function = "sata1"; 71 }; 72 73 pmx_sdio_cd: pmx-sdio-cd { 74 marvell,pins = "mpp27"; 75 marvell,function = "gpio"; 76 }; 77 78 pmx_sdio_wp: pmx-sdio-wp { 79 marvell,pins = "mpp28"; 80 marvell,function = "gpio"; 81 }; 82 83 pmx_button_eject: pmx-button-eject { 84 marvell,pins = "mpp29"; 85 marvell,function = "gpio"; 86 }; 87 88 pmx_led_green: pmx-led-green { 89 marvell,pins = "mpp22"; 90 marvell,function = "gpio"; 91 }; 92 93 pmx_led_red: pmx-led-red { 94 marvell,pins = "mpp24"; 95 marvell,function = "gpio"; 96 }; 97}; 98 99&uart0 { 100 status = "okay"; 101}; 102 103/* 104 * This PCIE controller has a USB 3.0 XHCI controller at 1,0 105 */ 106&pciec { 107 status = "okay"; 108}; 109 110&pcie0 { 111 status = "okay"; 112}; 113 114&sata { 115 status = "okay"; 116 pinctrl-0 = <&pmx_sata0 &pmx_sata1>; 117 pinctrl-names = "default"; 118 nr-ports = <1>; 119}; 120 121&sdio { 122 status = "okay"; 123 pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>; 124 pinctrl-names = "default"; 125 cd-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; 126 wp-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; 127}; 128 129&nand { 130 /* 128 MiB of NAND flash */ 131 chip-delay = <40>; 132 status = "okay"; 133 partitions { 134 compatible = "fixed-partitions"; 135 #address-cells = <1>; 136 #size-cells = <1>; 137 138 partition@0 { 139 label = "u-boot"; 140 reg = <0x00000000 0x200000>; 141 read-only; 142 }; 143 144 partition@200000 { 145 label = "uImage"; 146 reg = <0x00200000 0x300000>; 147 }; 148 149 partition@500000 { 150 label = "uImage2"; 151 reg = <0x00500000 0x300000>; 152 }; 153 154 partition@800000 { 155 label = "failsafe"; 156 reg = <0x00800000 0x800000>; 157 }; 158 159 partition@1000000 { 160 label = "root"; 161 reg = <0x01000000 0x7000000>; 162 }; 163 }; 164}; 165 166&mdio { 167 status = "okay"; 168 169 ethphy0: ethernet-phy@0 { 170 reg = <0>; 171 }; 172}; 173 174ð0 { 175 status = "okay"; 176 ethernet0-port@0 { 177 phy-handle = <ðphy0>; 178 }; 179}; 180