1/* 2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/pinctrl/omap.h> 12 13/ { 14 compatible = "ti,omap4430", "ti,omap4"; 15 interrupt-parent = <&wakeupgen>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 chosen { }; 19 20 aliases { 21 i2c0 = &i2c1; 22 i2c1 = &i2c2; 23 i2c2 = &i2c3; 24 i2c3 = &i2c4; 25 serial0 = &uart1; 26 serial1 = &uart2; 27 serial2 = &uart3; 28 serial3 = &uart4; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 cpu@0 { 36 compatible = "arm,cortex-a9"; 37 device_type = "cpu"; 38 next-level-cache = <&L2>; 39 reg = <0x0>; 40 41 clocks = <&dpll_mpu_ck>; 42 clock-names = "cpu"; 43 44 clock-latency = <300000>; /* From omap-cpufreq driver */ 45 }; 46 cpu@1 { 47 compatible = "arm,cortex-a9"; 48 device_type = "cpu"; 49 next-level-cache = <&L2>; 50 reg = <0x1>; 51 }; 52 }; 53 54 gic: interrupt-controller@48241000 { 55 compatible = "arm,cortex-a9-gic"; 56 interrupt-controller; 57 #interrupt-cells = <3>; 58 reg = <0x48241000 0x1000>, 59 <0x48240100 0x0100>; 60 interrupt-parent = <&gic>; 61 }; 62 63 L2: l2-cache-controller@48242000 { 64 compatible = "arm,pl310-cache"; 65 reg = <0x48242000 0x1000>; 66 cache-unified; 67 cache-level = <2>; 68 }; 69 70 local-timer@48240600 { 71 compatible = "arm,cortex-a9-twd-timer"; 72 clocks = <&mpu_periphclk>; 73 reg = <0x48240600 0x20>; 74 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>; 75 interrupt-parent = <&gic>; 76 }; 77 78 wakeupgen: interrupt-controller@48281000 { 79 compatible = "ti,omap4-wugen-mpu"; 80 interrupt-controller; 81 #interrupt-cells = <3>; 82 reg = <0x48281000 0x1000>; 83 interrupt-parent = <&gic>; 84 }; 85 86 /* 87 * The soc node represents the soc top level view. It is used for IPs 88 * that are not memory mapped in the MPU view or for the MPU itself. 89 */ 90 soc { 91 compatible = "ti,omap-infra"; 92 mpu { 93 compatible = "ti,omap4-mpu"; 94 ti,hwmods = "mpu"; 95 sram = <&ocmcram>; 96 }; 97 98 dsp { 99 compatible = "ti,omap3-c64"; 100 ti,hwmods = "dsp"; 101 }; 102 103 iva { 104 compatible = "ti,ivahd"; 105 ti,hwmods = "iva"; 106 }; 107 }; 108 109 /* 110 * XXX: Use a flat representation of the OMAP4 interconnect. 111 * The real OMAP interconnect network is quite complex. 112 * Since it will not bring real advantage to represent that in DT for 113 * the moment, just use a fake OCP bus entry to represent the whole bus 114 * hierarchy. 115 */ 116 ocp { 117 compatible = "ti,omap4-l3-noc", "simple-bus"; 118 #address-cells = <1>; 119 #size-cells = <1>; 120 ranges; 121 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; 122 reg = <0x44000000 0x1000>, 123 <0x44800000 0x2000>, 124 <0x45000000 0x1000>; 125 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 127 128 l4_cfg: l4@4a000000 { 129 compatible = "ti,omap4-l4-cfg", "simple-bus"; 130 #address-cells = <1>; 131 #size-cells = <1>; 132 ranges = <0 0x4a000000 0x1000000>; 133 134 cm1: cm1@4000 { 135 compatible = "ti,omap4-cm1"; 136 reg = <0x4000 0x2000>; 137 138 cm1_clocks: clocks { 139 #address-cells = <1>; 140 #size-cells = <0>; 141 }; 142 143 cm1_clockdomains: clockdomains { 144 }; 145 }; 146 147 cm2: cm2@8000 { 148 compatible = "ti,omap4-cm2"; 149 reg = <0x8000 0x3000>; 150 151 cm2_clocks: clocks { 152 #address-cells = <1>; 153 #size-cells = <0>; 154 }; 155 156 cm2_clockdomains: clockdomains { 157 }; 158 }; 159 160 omap4_scm_core: scm@2000 { 161 compatible = "ti,omap4-scm-core", "simple-bus"; 162 reg = <0x2000 0x1000>; 163 #address-cells = <1>; 164 #size-cells = <1>; 165 ranges = <0 0x2000 0x1000>; 166 167 scm_conf: scm_conf@0 { 168 compatible = "syscon"; 169 reg = <0x0 0x800>; 170 #address-cells = <1>; 171 #size-cells = <1>; 172 }; 173 }; 174 175 omap4_padconf_core: scm@100000 { 176 compatible = "ti,omap4-scm-padconf-core", 177 "simple-bus"; 178 #address-cells = <1>; 179 #size-cells = <1>; 180 ranges = <0 0x100000 0x1000>; 181 182 omap4_pmx_core: pinmux@40 { 183 compatible = "ti,omap4-padconf", 184 "pinctrl-single"; 185 reg = <0x40 0x0196>; 186 #address-cells = <1>; 187 #size-cells = <0>; 188 #interrupt-cells = <1>; 189 interrupt-controller; 190 pinctrl-single,register-width = <16>; 191 pinctrl-single,function-mask = <0x7fff>; 192 }; 193 194 omap4_padconf_global: omap4_padconf_global@5a0 { 195 compatible = "syscon", 196 "simple-bus"; 197 reg = <0x5a0 0x170>; 198 #address-cells = <1>; 199 #size-cells = <1>; 200 ranges = <0 0x5a0 0x170>; 201 202 pbias_regulator: pbias_regulator@60 { 203 compatible = "ti,pbias-omap4", "ti,pbias-omap"; 204 reg = <0x60 0x4>; 205 syscon = <&omap4_padconf_global>; 206 pbias_mmc_reg: pbias_mmc_omap4 { 207 regulator-name = "pbias_mmc_omap4"; 208 regulator-min-microvolt = <1800000>; 209 regulator-max-microvolt = <3000000>; 210 }; 211 }; 212 }; 213 }; 214 215 l4_wkup: l4@300000 { 216 compatible = "ti,omap4-l4-wkup", "simple-bus"; 217 #address-cells = <1>; 218 #size-cells = <1>; 219 ranges = <0 0x300000 0x40000>; 220 221 counter32k: counter@4000 { 222 compatible = "ti,omap-counter32k"; 223 reg = <0x4000 0x20>; 224 ti,hwmods = "counter_32k"; 225 }; 226 227 prm: prm@6000 { 228 compatible = "ti,omap4-prm"; 229 reg = <0x6000 0x3000>; 230 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 231 232 prm_clocks: clocks { 233 #address-cells = <1>; 234 #size-cells = <0>; 235 }; 236 237 prm_clockdomains: clockdomains { 238 }; 239 }; 240 241 scrm: scrm@a000 { 242 compatible = "ti,omap4-scrm"; 243 reg = <0xa000 0x2000>; 244 245 scrm_clocks: clocks { 246 #address-cells = <1>; 247 #size-cells = <0>; 248 }; 249 250 scrm_clockdomains: clockdomains { 251 }; 252 }; 253 254 omap4_pmx_wkup: pinmux@1e040 { 255 compatible = "ti,omap4-padconf", 256 "pinctrl-single"; 257 reg = <0x1e040 0x0038>; 258 #address-cells = <1>; 259 #size-cells = <0>; 260 #interrupt-cells = <1>; 261 interrupt-controller; 262 pinctrl-single,register-width = <16>; 263 pinctrl-single,function-mask = <0x7fff>; 264 }; 265 }; 266 }; 267 268 ocmcram: ocmcram@40304000 { 269 compatible = "mmio-sram"; 270 reg = <0x40304000 0xa000>; /* 40k */ 271 }; 272 273 sdma: dma-controller@4a056000 { 274 compatible = "ti,omap4430-sdma"; 275 reg = <0x4a056000 0x1000>; 276 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 280 #dma-cells = <1>; 281 dma-channels = <32>; 282 dma-requests = <127>; 283 }; 284 285 gpio1: gpio@4a310000 { 286 compatible = "ti,omap4-gpio"; 287 reg = <0x4a310000 0x200>; 288 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 289 ti,hwmods = "gpio1"; 290 ti,gpio-always-on; 291 gpio-controller; 292 #gpio-cells = <2>; 293 interrupt-controller; 294 #interrupt-cells = <2>; 295 }; 296 297 gpio2: gpio@48055000 { 298 compatible = "ti,omap4-gpio"; 299 reg = <0x48055000 0x200>; 300 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 301 ti,hwmods = "gpio2"; 302 gpio-controller; 303 #gpio-cells = <2>; 304 interrupt-controller; 305 #interrupt-cells = <2>; 306 }; 307 308 gpio3: gpio@48057000 { 309 compatible = "ti,omap4-gpio"; 310 reg = <0x48057000 0x200>; 311 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 312 ti,hwmods = "gpio3"; 313 gpio-controller; 314 #gpio-cells = <2>; 315 interrupt-controller; 316 #interrupt-cells = <2>; 317 }; 318 319 gpio4: gpio@48059000 { 320 compatible = "ti,omap4-gpio"; 321 reg = <0x48059000 0x200>; 322 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 323 ti,hwmods = "gpio4"; 324 gpio-controller; 325 #gpio-cells = <2>; 326 interrupt-controller; 327 #interrupt-cells = <2>; 328 }; 329 330 gpio5: gpio@4805b000 { 331 compatible = "ti,omap4-gpio"; 332 reg = <0x4805b000 0x200>; 333 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 334 ti,hwmods = "gpio5"; 335 gpio-controller; 336 #gpio-cells = <2>; 337 interrupt-controller; 338 #interrupt-cells = <2>; 339 }; 340 341 gpio6: gpio@4805d000 { 342 compatible = "ti,omap4-gpio"; 343 reg = <0x4805d000 0x200>; 344 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 345 ti,hwmods = "gpio6"; 346 gpio-controller; 347 #gpio-cells = <2>; 348 interrupt-controller; 349 #interrupt-cells = <2>; 350 }; 351 352 elm: elm@48078000 { 353 compatible = "ti,am3352-elm"; 354 reg = <0x48078000 0x2000>; 355 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 356 ti,hwmods = "elm"; 357 status = "disabled"; 358 }; 359 360 gpmc: gpmc@50000000 { 361 compatible = "ti,omap4430-gpmc"; 362 reg = <0x50000000 0x1000>; 363 #address-cells = <2>; 364 #size-cells = <1>; 365 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 366 dmas = <&sdma 4>; 367 dma-names = "rxtx"; 368 gpmc,num-cs = <8>; 369 gpmc,num-waitpins = <4>; 370 ti,hwmods = "gpmc"; 371 ti,no-idle-on-init; 372 clocks = <&l3_div_ck>; 373 clock-names = "fck"; 374 interrupt-controller; 375 #interrupt-cells = <2>; 376 gpio-controller; 377 #gpio-cells = <2>; 378 }; 379 380 uart1: serial@4806a000 { 381 compatible = "ti,omap4-uart"; 382 reg = <0x4806a000 0x100>; 383 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 384 ti,hwmods = "uart1"; 385 clock-frequency = <48000000>; 386 }; 387 388 uart2: serial@4806c000 { 389 compatible = "ti,omap4-uart"; 390 reg = <0x4806c000 0x100>; 391 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 392 ti,hwmods = "uart2"; 393 clock-frequency = <48000000>; 394 }; 395 396 uart3: serial@48020000 { 397 compatible = "ti,omap4-uart"; 398 reg = <0x48020000 0x100>; 399 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 400 ti,hwmods = "uart3"; 401 clock-frequency = <48000000>; 402 }; 403 404 uart4: serial@4806e000 { 405 compatible = "ti,omap4-uart"; 406 reg = <0x4806e000 0x100>; 407 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 408 ti,hwmods = "uart4"; 409 clock-frequency = <48000000>; 410 }; 411 412 hwspinlock: spinlock@4a0f6000 { 413 compatible = "ti,omap4-hwspinlock"; 414 reg = <0x4a0f6000 0x1000>; 415 ti,hwmods = "spinlock"; 416 #hwlock-cells = <1>; 417 }; 418 419 i2c1: i2c@48070000 { 420 compatible = "ti,omap4-i2c"; 421 reg = <0x48070000 0x100>; 422 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 ti,hwmods = "i2c1"; 426 }; 427 428 i2c2: i2c@48072000 { 429 compatible = "ti,omap4-i2c"; 430 reg = <0x48072000 0x100>; 431 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 ti,hwmods = "i2c2"; 435 }; 436 437 i2c3: i2c@48060000 { 438 compatible = "ti,omap4-i2c"; 439 reg = <0x48060000 0x100>; 440 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 441 #address-cells = <1>; 442 #size-cells = <0>; 443 ti,hwmods = "i2c3"; 444 }; 445 446 i2c4: i2c@48350000 { 447 compatible = "ti,omap4-i2c"; 448 reg = <0x48350000 0x100>; 449 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 ti,hwmods = "i2c4"; 453 }; 454 455 mcspi1: spi@48098000 { 456 compatible = "ti,omap4-mcspi"; 457 reg = <0x48098000 0x200>; 458 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 ti,hwmods = "mcspi1"; 462 ti,spi-num-cs = <4>; 463 dmas = <&sdma 35>, 464 <&sdma 36>, 465 <&sdma 37>, 466 <&sdma 38>, 467 <&sdma 39>, 468 <&sdma 40>, 469 <&sdma 41>, 470 <&sdma 42>; 471 dma-names = "tx0", "rx0", "tx1", "rx1", 472 "tx2", "rx2", "tx3", "rx3"; 473 }; 474 475 mcspi2: spi@4809a000 { 476 compatible = "ti,omap4-mcspi"; 477 reg = <0x4809a000 0x200>; 478 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 ti,hwmods = "mcspi2"; 482 ti,spi-num-cs = <2>; 483 dmas = <&sdma 43>, 484 <&sdma 44>, 485 <&sdma 45>, 486 <&sdma 46>; 487 dma-names = "tx0", "rx0", "tx1", "rx1"; 488 }; 489 490 mcspi3: spi@480b8000 { 491 compatible = "ti,omap4-mcspi"; 492 reg = <0x480b8000 0x200>; 493 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 ti,hwmods = "mcspi3"; 497 ti,spi-num-cs = <2>; 498 dmas = <&sdma 15>, <&sdma 16>; 499 dma-names = "tx0", "rx0"; 500 }; 501 502 mcspi4: spi@480ba000 { 503 compatible = "ti,omap4-mcspi"; 504 reg = <0x480ba000 0x200>; 505 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 ti,hwmods = "mcspi4"; 509 ti,spi-num-cs = <1>; 510 dmas = <&sdma 70>, <&sdma 71>; 511 dma-names = "tx0", "rx0"; 512 }; 513 514 mmc1: mmc@4809c000 { 515 compatible = "ti,omap4-hsmmc"; 516 reg = <0x4809c000 0x400>; 517 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 518 ti,hwmods = "mmc1"; 519 ti,dual-volt; 520 ti,needs-special-reset; 521 dmas = <&sdma 61>, <&sdma 62>; 522 dma-names = "tx", "rx"; 523 pbias-supply = <&pbias_mmc_reg>; 524 }; 525 526 mmc2: mmc@480b4000 { 527 compatible = "ti,omap4-hsmmc"; 528 reg = <0x480b4000 0x400>; 529 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 530 ti,hwmods = "mmc2"; 531 ti,needs-special-reset; 532 dmas = <&sdma 47>, <&sdma 48>; 533 dma-names = "tx", "rx"; 534 }; 535 536 mmc3: mmc@480ad000 { 537 compatible = "ti,omap4-hsmmc"; 538 reg = <0x480ad000 0x400>; 539 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 540 ti,hwmods = "mmc3"; 541 ti,needs-special-reset; 542 dmas = <&sdma 77>, <&sdma 78>; 543 dma-names = "tx", "rx"; 544 }; 545 546 mmc4: mmc@480d1000 { 547 compatible = "ti,omap4-hsmmc"; 548 reg = <0x480d1000 0x400>; 549 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 550 ti,hwmods = "mmc4"; 551 ti,needs-special-reset; 552 dmas = <&sdma 57>, <&sdma 58>; 553 dma-names = "tx", "rx"; 554 }; 555 556 mmc5: mmc@480d5000 { 557 compatible = "ti,omap4-hsmmc"; 558 reg = <0x480d5000 0x400>; 559 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 560 ti,hwmods = "mmc5"; 561 ti,needs-special-reset; 562 dmas = <&sdma 59>, <&sdma 60>; 563 dma-names = "tx", "rx"; 564 }; 565 566 mmu_dsp: mmu@4a066000 { 567 compatible = "ti,omap4-iommu"; 568 reg = <0x4a066000 0x100>; 569 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 570 ti,hwmods = "mmu_dsp"; 571 #iommu-cells = <0>; 572 }; 573 574 mmu_ipu: mmu@55082000 { 575 compatible = "ti,omap4-iommu"; 576 reg = <0x55082000 0x100>; 577 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 578 ti,hwmods = "mmu_ipu"; 579 #iommu-cells = <0>; 580 ti,iommu-bus-err-back; 581 }; 582 583 wdt2: wdt@4a314000 { 584 compatible = "ti,omap4-wdt", "ti,omap3-wdt"; 585 reg = <0x4a314000 0x80>; 586 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 587 ti,hwmods = "wd_timer2"; 588 }; 589 590 mcpdm: mcpdm@40132000 { 591 compatible = "ti,omap4-mcpdm"; 592 reg = <0x40132000 0x7f>, /* MPU private access */ 593 <0x49032000 0x7f>; /* L3 Interconnect */ 594 reg-names = "mpu", "dma"; 595 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 596 ti,hwmods = "mcpdm"; 597 dmas = <&sdma 65>, 598 <&sdma 66>; 599 dma-names = "up_link", "dn_link"; 600 status = "disabled"; 601 }; 602 603 dmic: dmic@4012e000 { 604 compatible = "ti,omap4-dmic"; 605 reg = <0x4012e000 0x7f>, /* MPU private access */ 606 <0x4902e000 0x7f>; /* L3 Interconnect */ 607 reg-names = "mpu", "dma"; 608 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 609 ti,hwmods = "dmic"; 610 dmas = <&sdma 67>; 611 dma-names = "up_link"; 612 status = "disabled"; 613 }; 614 615 mcbsp1: mcbsp@40122000 { 616 compatible = "ti,omap4-mcbsp"; 617 reg = <0x40122000 0xff>, /* MPU private access */ 618 <0x49022000 0xff>; /* L3 Interconnect */ 619 reg-names = "mpu", "dma"; 620 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 621 interrupt-names = "common"; 622 ti,buffer-size = <128>; 623 ti,hwmods = "mcbsp1"; 624 dmas = <&sdma 33>, 625 <&sdma 34>; 626 dma-names = "tx", "rx"; 627 status = "disabled"; 628 }; 629 630 mcbsp2: mcbsp@40124000 { 631 compatible = "ti,omap4-mcbsp"; 632 reg = <0x40124000 0xff>, /* MPU private access */ 633 <0x49024000 0xff>; /* L3 Interconnect */ 634 reg-names = "mpu", "dma"; 635 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 636 interrupt-names = "common"; 637 ti,buffer-size = <128>; 638 ti,hwmods = "mcbsp2"; 639 dmas = <&sdma 17>, 640 <&sdma 18>; 641 dma-names = "tx", "rx"; 642 status = "disabled"; 643 }; 644 645 mcbsp3: mcbsp@40126000 { 646 compatible = "ti,omap4-mcbsp"; 647 reg = <0x40126000 0xff>, /* MPU private access */ 648 <0x49026000 0xff>; /* L3 Interconnect */ 649 reg-names = "mpu", "dma"; 650 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 651 interrupt-names = "common"; 652 ti,buffer-size = <128>; 653 ti,hwmods = "mcbsp3"; 654 dmas = <&sdma 19>, 655 <&sdma 20>; 656 dma-names = "tx", "rx"; 657 status = "disabled"; 658 }; 659 660 mcbsp4: mcbsp@48096000 { 661 compatible = "ti,omap4-mcbsp"; 662 reg = <0x48096000 0xff>; /* L4 Interconnect */ 663 reg-names = "mpu"; 664 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 665 interrupt-names = "common"; 666 ti,buffer-size = <128>; 667 ti,hwmods = "mcbsp4"; 668 dmas = <&sdma 31>, 669 <&sdma 32>; 670 dma-names = "tx", "rx"; 671 status = "disabled"; 672 }; 673 674 keypad: keypad@4a31c000 { 675 compatible = "ti,omap4-keypad"; 676 reg = <0x4a31c000 0x80>; 677 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 678 reg-names = "mpu"; 679 ti,hwmods = "kbd"; 680 }; 681 682 dmm@4e000000 { 683 compatible = "ti,omap4-dmm"; 684 reg = <0x4e000000 0x800>; 685 interrupts = <0 113 0x4>; 686 ti,hwmods = "dmm"; 687 }; 688 689 emif1: emif@4c000000 { 690 compatible = "ti,emif-4d"; 691 reg = <0x4c000000 0x100>; 692 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 693 ti,hwmods = "emif1"; 694 ti,no-idle-on-init; 695 phy-type = <1>; 696 hw-caps-read-idle-ctrl; 697 hw-caps-ll-interface; 698 hw-caps-temp-alert; 699 }; 700 701 emif2: emif@4d000000 { 702 compatible = "ti,emif-4d"; 703 reg = <0x4d000000 0x100>; 704 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 705 ti,hwmods = "emif2"; 706 ti,no-idle-on-init; 707 phy-type = <1>; 708 hw-caps-read-idle-ctrl; 709 hw-caps-ll-interface; 710 hw-caps-temp-alert; 711 }; 712 713 ocp2scp@4a0ad000 { 714 compatible = "ti,omap-ocp2scp"; 715 reg = <0x4a0ad000 0x1f>; 716 #address-cells = <1>; 717 #size-cells = <1>; 718 ranges; 719 ti,hwmods = "ocp2scp_usb_phy"; 720 usb2_phy: usb2phy@4a0ad080 { 721 compatible = "ti,omap-usb2"; 722 reg = <0x4a0ad080 0x58>; 723 ctrl-module = <&omap_control_usb2phy>; 724 clocks = <&usb_phy_cm_clk32k>; 725 clock-names = "wkupclk"; 726 #phy-cells = <0>; 727 }; 728 }; 729 730 mailbox: mailbox@4a0f4000 { 731 compatible = "ti,omap4-mailbox"; 732 reg = <0x4a0f4000 0x200>; 733 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 734 ti,hwmods = "mailbox"; 735 #mbox-cells = <1>; 736 ti,mbox-num-users = <3>; 737 ti,mbox-num-fifos = <8>; 738 mbox_ipu: mbox_ipu { 739 ti,mbox-tx = <0 0 0>; 740 ti,mbox-rx = <1 0 0>; 741 }; 742 mbox_dsp: mbox_dsp { 743 ti,mbox-tx = <3 0 0>; 744 ti,mbox-rx = <2 0 0>; 745 }; 746 }; 747 748 timer1: timer@4a318000 { 749 compatible = "ti,omap3430-timer"; 750 reg = <0x4a318000 0x80>; 751 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 752 ti,hwmods = "timer1"; 753 ti,timer-alwon; 754 }; 755 756 timer2: timer@48032000 { 757 compatible = "ti,omap3430-timer"; 758 reg = <0x48032000 0x80>; 759 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 760 ti,hwmods = "timer2"; 761 }; 762 763 timer3: timer@48034000 { 764 compatible = "ti,omap4430-timer"; 765 reg = <0x48034000 0x80>; 766 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 767 ti,hwmods = "timer3"; 768 }; 769 770 timer4: timer@48036000 { 771 compatible = "ti,omap4430-timer"; 772 reg = <0x48036000 0x80>; 773 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 774 ti,hwmods = "timer4"; 775 }; 776 777 timer5: timer@40138000 { 778 compatible = "ti,omap4430-timer"; 779 reg = <0x40138000 0x80>, 780 <0x49038000 0x80>; 781 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 782 ti,hwmods = "timer5"; 783 ti,timer-dsp; 784 }; 785 786 timer6: timer@4013a000 { 787 compatible = "ti,omap4430-timer"; 788 reg = <0x4013a000 0x80>, 789 <0x4903a000 0x80>; 790 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 791 ti,hwmods = "timer6"; 792 ti,timer-dsp; 793 }; 794 795 timer7: timer@4013c000 { 796 compatible = "ti,omap4430-timer"; 797 reg = <0x4013c000 0x80>, 798 <0x4903c000 0x80>; 799 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 800 ti,hwmods = "timer7"; 801 ti,timer-dsp; 802 }; 803 804 timer8: timer@4013e000 { 805 compatible = "ti,omap4430-timer"; 806 reg = <0x4013e000 0x80>, 807 <0x4903e000 0x80>; 808 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 809 ti,hwmods = "timer8"; 810 ti,timer-pwm; 811 ti,timer-dsp; 812 }; 813 814 timer9: timer@4803e000 { 815 compatible = "ti,omap4430-timer"; 816 reg = <0x4803e000 0x80>; 817 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 818 ti,hwmods = "timer9"; 819 ti,timer-pwm; 820 }; 821 822 timer10: timer@48086000 { 823 compatible = "ti,omap3430-timer"; 824 reg = <0x48086000 0x80>; 825 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 826 ti,hwmods = "timer10"; 827 ti,timer-pwm; 828 }; 829 830 timer11: timer@48088000 { 831 compatible = "ti,omap4430-timer"; 832 reg = <0x48088000 0x80>; 833 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 834 ti,hwmods = "timer11"; 835 ti,timer-pwm; 836 }; 837 838 usbhstll: usbhstll@4a062000 { 839 compatible = "ti,usbhs-tll"; 840 reg = <0x4a062000 0x1000>; 841 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 842 ti,hwmods = "usb_tll_hs"; 843 }; 844 845 usbhshost: usbhshost@4a064000 { 846 compatible = "ti,usbhs-host"; 847 reg = <0x4a064000 0x800>; 848 ti,hwmods = "usb_host_hs"; 849 #address-cells = <1>; 850 #size-cells = <1>; 851 ranges; 852 clocks = <&init_60m_fclk>, 853 <&xclk60mhsp1_ck>, 854 <&xclk60mhsp2_ck>; 855 clock-names = "refclk_60m_int", 856 "refclk_60m_ext_p1", 857 "refclk_60m_ext_p2"; 858 859 usbhsohci: ohci@4a064800 { 860 compatible = "ti,ohci-omap3"; 861 reg = <0x4a064800 0x400>; 862 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 863 }; 864 865 usbhsehci: ehci@4a064c00 { 866 compatible = "ti,ehci-omap"; 867 reg = <0x4a064c00 0x400>; 868 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 869 }; 870 }; 871 872 omap_control_usb2phy: control-phy@4a002300 { 873 compatible = "ti,control-phy-usb2"; 874 reg = <0x4a002300 0x4>; 875 reg-names = "power"; 876 }; 877 878 omap_control_usbotg: control-phy@4a00233c { 879 compatible = "ti,control-phy-otghs"; 880 reg = <0x4a00233c 0x4>; 881 reg-names = "otghs_control"; 882 }; 883 884 usb_otg_hs: usb_otg_hs@4a0ab000 { 885 compatible = "ti,omap4-musb"; 886 reg = <0x4a0ab000 0x7ff>; 887 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 888 interrupt-names = "mc", "dma"; 889 ti,hwmods = "usb_otg_hs"; 890 usb-phy = <&usb2_phy>; 891 phys = <&usb2_phy>; 892 phy-names = "usb2-phy"; 893 multipoint = <1>; 894 num-eps = <16>; 895 ram-bits = <12>; 896 ctrl-module = <&omap_control_usbotg>; 897 }; 898 899 aes: aes@4b501000 { 900 compatible = "ti,omap4-aes"; 901 ti,hwmods = "aes"; 902 reg = <0x4b501000 0xa0>; 903 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 904 dmas = <&sdma 111>, <&sdma 110>; 905 dma-names = "tx", "rx"; 906 }; 907 908 des: des@480a5000 { 909 compatible = "ti,omap4-des"; 910 ti,hwmods = "des"; 911 reg = <0x480a5000 0xa0>; 912 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 913 dmas = <&sdma 117>, <&sdma 116>; 914 dma-names = "tx", "rx"; 915 }; 916 917 abb_mpu: regulator-abb-mpu { 918 compatible = "ti,abb-v2"; 919 regulator-name = "abb_mpu"; 920 #address-cells = <0>; 921 #size-cells = <0>; 922 ti,tranxdone-status-mask = <0x80>; 923 clocks = <&sys_clkin_ck>; 924 ti,settling-time = <50>; 925 ti,clock-cycles = <16>; 926 927 status = "disabled"; 928 }; 929 930 abb_iva: regulator-abb-iva { 931 compatible = "ti,abb-v2"; 932 regulator-name = "abb_iva"; 933 #address-cells = <0>; 934 #size-cells = <0>; 935 ti,tranxdone-status-mask = <0x80000000>; 936 clocks = <&sys_clkin_ck>; 937 ti,settling-time = <50>; 938 ti,clock-cycles = <16>; 939 940 status = "disabled"; 941 }; 942 943 dss: dss@58000000 { 944 compatible = "ti,omap4-dss"; 945 reg = <0x58000000 0x80>; 946 status = "disabled"; 947 ti,hwmods = "dss_core"; 948 clocks = <&dss_dss_clk>; 949 clock-names = "fck"; 950 #address-cells = <1>; 951 #size-cells = <1>; 952 ranges; 953 954 dispc@58001000 { 955 compatible = "ti,omap4-dispc"; 956 reg = <0x58001000 0x1000>; 957 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 958 ti,hwmods = "dss_dispc"; 959 clocks = <&dss_dss_clk>; 960 clock-names = "fck"; 961 }; 962 963 rfbi: encoder@58002000 { 964 compatible = "ti,omap4-rfbi"; 965 reg = <0x58002000 0x1000>; 966 status = "disabled"; 967 ti,hwmods = "dss_rfbi"; 968 clocks = <&dss_dss_clk>, <&l3_div_ck>; 969 clock-names = "fck", "ick"; 970 }; 971 972 venc: encoder@58003000 { 973 compatible = "ti,omap4-venc"; 974 reg = <0x58003000 0x1000>; 975 status = "disabled"; 976 ti,hwmods = "dss_venc"; 977 clocks = <&dss_tv_clk>; 978 clock-names = "fck"; 979 }; 980 981 dsi1: encoder@58004000 { 982 compatible = "ti,omap4-dsi"; 983 reg = <0x58004000 0x200>, 984 <0x58004200 0x40>, 985 <0x58004300 0x20>; 986 reg-names = "proto", "phy", "pll"; 987 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 988 status = "disabled"; 989 ti,hwmods = "dss_dsi1"; 990 clocks = <&dss_dss_clk>, <&dss_sys_clk>; 991 clock-names = "fck", "sys_clk"; 992 }; 993 994 dsi2: encoder@58005000 { 995 compatible = "ti,omap4-dsi"; 996 reg = <0x58005000 0x200>, 997 <0x58005200 0x40>, 998 <0x58005300 0x20>; 999 reg-names = "proto", "phy", "pll"; 1000 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1001 status = "disabled"; 1002 ti,hwmods = "dss_dsi2"; 1003 clocks = <&dss_dss_clk>, <&dss_sys_clk>; 1004 clock-names = "fck", "sys_clk"; 1005 }; 1006 1007 hdmi: encoder@58006000 { 1008 compatible = "ti,omap4-hdmi"; 1009 reg = <0x58006000 0x200>, 1010 <0x58006200 0x100>, 1011 <0x58006300 0x100>, 1012 <0x58006400 0x1000>; 1013 reg-names = "wp", "pll", "phy", "core"; 1014 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1015 status = "disabled"; 1016 ti,hwmods = "dss_hdmi"; 1017 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>; 1018 clock-names = "fck", "sys_clk"; 1019 dmas = <&sdma 76>; 1020 dma-names = "audio_tx"; 1021 }; 1022 }; 1023 }; 1024}; 1025 1026/include/ "omap44xx-clocks.dtsi" 1027