1/* 2 * Device Tree Source for the r8a7791 SoC 3 * 4 * Copyright (C) 2013-2015 Renesas Electronics Corporation 5 * Copyright (C) 2013-2014 Renesas Solutions Corp. 6 * Copyright (C) 2014 Cogent Embedded Inc. 7 * 8 * This file is licensed under the terms of the GNU General Public License 9 * version 2. This program is licensed "as is" without any warranty of any 10 * kind, whether express or implied. 11 */ 12 13#include <dt-bindings/clock/r8a7791-clock.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/power/r8a7791-sysc.h> 17 18/ { 19 compatible = "renesas,r8a7791"; 20 interrupt-parent = <&gic>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 i2c0 = &i2c0; 26 i2c1 = &i2c1; 27 i2c2 = &i2c2; 28 i2c3 = &i2c3; 29 i2c4 = &i2c4; 30 i2c5 = &i2c5; 31 i2c6 = &i2c6; 32 i2c7 = &i2c7; 33 i2c8 = &i2c8; 34 spi0 = &qspi; 35 spi1 = &msiof0; 36 spi2 = &msiof1; 37 spi3 = &msiof2; 38 vin0 = &vin0; 39 vin1 = &vin1; 40 vin2 = &vin2; 41 }; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 enable-method = "renesas,apmu"; 47 48 cpu0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a15"; 51 reg = <0>; 52 clock-frequency = <1500000000>; 53 voltage-tolerance = <1>; /* 1% */ 54 clocks = <&cpg_clocks R8A7791_CLK_Z>; 55 clock-latency = <300000>; /* 300 us */ 56 power-domains = <&sysc R8A7791_PD_CA15_CPU0>; 57 next-level-cache = <&L2_CA15>; 58 59 /* kHz - uV - OPPs unknown yet */ 60 operating-points = <1500000 1000000>, 61 <1312500 1000000>, 62 <1125000 1000000>, 63 < 937500 1000000>, 64 < 750000 1000000>, 65 < 375000 1000000>; 66 }; 67 68 cpu1: cpu@1 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a15"; 71 reg = <1>; 72 clock-frequency = <1500000000>; 73 power-domains = <&sysc R8A7791_PD_CA15_CPU1>; 74 next-level-cache = <&L2_CA15>; 75 }; 76 77 L2_CA15: cache-controller-0 { 78 compatible = "cache"; 79 power-domains = <&sysc R8A7791_PD_CA15_SCU>; 80 cache-unified; 81 cache-level = <2>; 82 }; 83 }; 84 85 thermal-zones { 86 cpu_thermal: cpu-thermal { 87 polling-delay-passive = <0>; 88 polling-delay = <0>; 89 90 thermal-sensors = <&thermal>; 91 92 trips { 93 cpu-crit { 94 temperature = <115000>; 95 hysteresis = <0>; 96 type = "critical"; 97 }; 98 }; 99 cooling-maps { 100 }; 101 }; 102 }; 103 104 apmu@e6152000 { 105 compatible = "renesas,r8a7791-apmu", "renesas,apmu"; 106 reg = <0 0xe6152000 0 0x188>; 107 cpus = <&cpu0 &cpu1>; 108 }; 109 110 gic: interrupt-controller@f1001000 { 111 compatible = "arm,gic-400"; 112 #interrupt-cells = <3>; 113 #address-cells = <0>; 114 interrupt-controller; 115 reg = <0 0xf1001000 0 0x1000>, 116 <0 0xf1002000 0 0x1000>, 117 <0 0xf1004000 0 0x2000>, 118 <0 0xf1006000 0 0x2000>; 119 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 120 }; 121 122 gpio0: gpio@e6050000 { 123 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 124 reg = <0 0xe6050000 0 0x50>; 125 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 126 #gpio-cells = <2>; 127 gpio-controller; 128 gpio-ranges = <&pfc 0 0 32>; 129 #interrupt-cells = <2>; 130 interrupt-controller; 131 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>; 132 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 133 }; 134 135 gpio1: gpio@e6051000 { 136 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 137 reg = <0 0xe6051000 0 0x50>; 138 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 139 #gpio-cells = <2>; 140 gpio-controller; 141 gpio-ranges = <&pfc 0 32 26>; 142 #interrupt-cells = <2>; 143 interrupt-controller; 144 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>; 145 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 146 }; 147 148 gpio2: gpio@e6052000 { 149 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 150 reg = <0 0xe6052000 0 0x50>; 151 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 152 #gpio-cells = <2>; 153 gpio-controller; 154 gpio-ranges = <&pfc 0 64 32>; 155 #interrupt-cells = <2>; 156 interrupt-controller; 157 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>; 158 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 159 }; 160 161 gpio3: gpio@e6053000 { 162 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 163 reg = <0 0xe6053000 0 0x50>; 164 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 165 #gpio-cells = <2>; 166 gpio-controller; 167 gpio-ranges = <&pfc 0 96 32>; 168 #interrupt-cells = <2>; 169 interrupt-controller; 170 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>; 171 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 172 }; 173 174 gpio4: gpio@e6054000 { 175 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 176 reg = <0 0xe6054000 0 0x50>; 177 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 178 #gpio-cells = <2>; 179 gpio-controller; 180 gpio-ranges = <&pfc 0 128 32>; 181 #interrupt-cells = <2>; 182 interrupt-controller; 183 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>; 184 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 185 }; 186 187 gpio5: gpio@e6055000 { 188 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 189 reg = <0 0xe6055000 0 0x50>; 190 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 191 #gpio-cells = <2>; 192 gpio-controller; 193 gpio-ranges = <&pfc 0 160 32>; 194 #interrupt-cells = <2>; 195 interrupt-controller; 196 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>; 197 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 198 }; 199 200 gpio6: gpio@e6055400 { 201 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 202 reg = <0 0xe6055400 0 0x50>; 203 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 204 #gpio-cells = <2>; 205 gpio-controller; 206 gpio-ranges = <&pfc 0 192 32>; 207 #interrupt-cells = <2>; 208 interrupt-controller; 209 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>; 210 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 211 }; 212 213 gpio7: gpio@e6055800 { 214 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar"; 215 reg = <0 0xe6055800 0 0x50>; 216 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 217 #gpio-cells = <2>; 218 gpio-controller; 219 gpio-ranges = <&pfc 0 224 26>; 220 #interrupt-cells = <2>; 221 interrupt-controller; 222 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>; 223 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 224 }; 225 226 thermal: thermal@e61f0000 { 227 compatible = "renesas,thermal-r8a7791", 228 "renesas,rcar-gen2-thermal", 229 "renesas,rcar-thermal"; 230 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; 231 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>; 233 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 234 #thermal-sensor-cells = <0>; 235 }; 236 237 timer { 238 compatible = "arm,armv7-timer"; 239 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 240 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 241 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 242 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 243 }; 244 245 cmt0: timer@ffca0000 { 246 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; 247 reg = <0 0xffca0000 0 0x1004>; 248 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&mstp1_clks R8A7791_CLK_CMT0>; 251 clock-names = "fck"; 252 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 253 254 renesas,channels-mask = <0x60>; 255 256 status = "disabled"; 257 }; 258 259 cmt1: timer@e6130000 { 260 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; 261 reg = <0 0xe6130000 0 0x1004>; 262 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&mstp3_clks R8A7791_CLK_CMT1>; 271 clock-names = "fck"; 272 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 273 274 renesas,channels-mask = <0xff>; 275 276 status = "disabled"; 277 }; 278 279 irqc0: interrupt-controller@e61c0000 { 280 compatible = "renesas,irqc-r8a7791", "renesas,irqc"; 281 #interrupt-cells = <2>; 282 interrupt-controller; 283 reg = <0 0xe61c0000 0 0x200>; 284 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&mstp4_clks R8A7791_CLK_IRQC>; 295 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 296 }; 297 298 dmac0: dma-controller@e6700000 { 299 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; 300 reg = <0 0xe6700000 0 0x20000>; 301 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 302 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH 303 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH 304 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 305 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 306 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 307 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 308 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 309 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 310 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 311 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH 312 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH 313 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH 314 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 315 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH 316 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 317 interrupt-names = "error", 318 "ch0", "ch1", "ch2", "ch3", 319 "ch4", "ch5", "ch6", "ch7", 320 "ch8", "ch9", "ch10", "ch11", 321 "ch12", "ch13", "ch14"; 322 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>; 323 clock-names = "fck"; 324 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 325 #dma-cells = <1>; 326 dma-channels = <15>; 327 }; 328 329 dmac1: dma-controller@e6720000 { 330 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; 331 reg = <0 0xe6720000 0 0x20000>; 332 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 333 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 334 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH 335 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 336 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 337 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH 338 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 339 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH 340 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH 341 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH 342 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH 343 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH 344 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 345 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 346 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 347 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 348 interrupt-names = "error", 349 "ch0", "ch1", "ch2", "ch3", 350 "ch4", "ch5", "ch6", "ch7", 351 "ch8", "ch9", "ch10", "ch11", 352 "ch12", "ch13", "ch14"; 353 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>; 354 clock-names = "fck"; 355 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 356 #dma-cells = <1>; 357 dma-channels = <15>; 358 }; 359 360 audma0: dma-controller@ec700000 { 361 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; 362 reg = <0 0xec700000 0 0x10000>; 363 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 364 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 365 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 366 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 367 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 368 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 369 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 370 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 371 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 372 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 373 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 374 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 375 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 376 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 377 interrupt-names = "error", 378 "ch0", "ch1", "ch2", "ch3", 379 "ch4", "ch5", "ch6", "ch7", 380 "ch8", "ch9", "ch10", "ch11", 381 "ch12"; 382 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>; 383 clock-names = "fck"; 384 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 385 #dma-cells = <1>; 386 dma-channels = <13>; 387 }; 388 389 audma1: dma-controller@ec720000 { 390 compatible = "renesas,dmac-r8a7791", "renesas,rcar-dmac"; 391 reg = <0 0xec720000 0 0x10000>; 392 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 393 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 394 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 395 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 396 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 397 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 398 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 399 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 400 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 401 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 402 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 403 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 404 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 405 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 406 interrupt-names = "error", 407 "ch0", "ch1", "ch2", "ch3", 408 "ch4", "ch5", "ch6", "ch7", 409 "ch8", "ch9", "ch10", "ch11", 410 "ch12"; 411 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>; 412 clock-names = "fck"; 413 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 414 #dma-cells = <1>; 415 dma-channels = <13>; 416 }; 417 418 usb_dmac0: dma-controller@e65a0000 { 419 compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac"; 420 reg = <0 0xe65a0000 0 0x100>; 421 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 422 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 423 interrupt-names = "ch0", "ch1"; 424 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>; 425 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 426 #dma-cells = <1>; 427 dma-channels = <2>; 428 }; 429 430 usb_dmac1: dma-controller@e65b0000 { 431 compatible = "renesas,r8a7791-usb-dmac", "renesas,usb-dmac"; 432 reg = <0 0xe65b0000 0 0x100>; 433 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 434 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 435 interrupt-names = "ch0", "ch1"; 436 clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>; 437 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 438 #dma-cells = <1>; 439 dma-channels = <2>; 440 }; 441 442 /* The memory map in the User's Manual maps the cores to bus numbers */ 443 i2c0: i2c@e6508000 { 444 #address-cells = <1>; 445 #size-cells = <0>; 446 compatible = "renesas,i2c-r8a7791"; 447 reg = <0 0xe6508000 0 0x40>; 448 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&mstp9_clks R8A7791_CLK_I2C0>; 450 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 451 i2c-scl-internal-delay-ns = <6>; 452 status = "disabled"; 453 }; 454 455 i2c1: i2c@e6518000 { 456 #address-cells = <1>; 457 #size-cells = <0>; 458 compatible = "renesas,i2c-r8a7791"; 459 reg = <0 0xe6518000 0 0x40>; 460 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&mstp9_clks R8A7791_CLK_I2C1>; 462 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 463 i2c-scl-internal-delay-ns = <6>; 464 status = "disabled"; 465 }; 466 467 i2c2: i2c@e6530000 { 468 #address-cells = <1>; 469 #size-cells = <0>; 470 compatible = "renesas,i2c-r8a7791"; 471 reg = <0 0xe6530000 0 0x40>; 472 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&mstp9_clks R8A7791_CLK_I2C2>; 474 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 475 i2c-scl-internal-delay-ns = <6>; 476 status = "disabled"; 477 }; 478 479 i2c3: i2c@e6540000 { 480 #address-cells = <1>; 481 #size-cells = <0>; 482 compatible = "renesas,i2c-r8a7791"; 483 reg = <0 0xe6540000 0 0x40>; 484 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&mstp9_clks R8A7791_CLK_I2C3>; 486 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 487 i2c-scl-internal-delay-ns = <6>; 488 status = "disabled"; 489 }; 490 491 i2c4: i2c@e6520000 { 492 #address-cells = <1>; 493 #size-cells = <0>; 494 compatible = "renesas,i2c-r8a7791"; 495 reg = <0 0xe6520000 0 0x40>; 496 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&mstp9_clks R8A7791_CLK_I2C4>; 498 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 499 i2c-scl-internal-delay-ns = <6>; 500 status = "disabled"; 501 }; 502 503 i2c5: i2c@e6528000 { 504 /* doesn't need pinmux */ 505 #address-cells = <1>; 506 #size-cells = <0>; 507 compatible = "renesas,i2c-r8a7791"; 508 reg = <0 0xe6528000 0 0x40>; 509 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&mstp9_clks R8A7791_CLK_I2C5>; 511 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 512 i2c-scl-internal-delay-ns = <110>; 513 status = "disabled"; 514 }; 515 516 i2c6: i2c@e60b0000 { 517 /* doesn't need pinmux */ 518 #address-cells = <1>; 519 #size-cells = <0>; 520 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; 521 reg = <0 0xe60b0000 0 0x425>; 522 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; 524 dmas = <&dmac0 0x77>, <&dmac0 0x78>, 525 <&dmac1 0x77>, <&dmac1 0x78>; 526 dma-names = "tx", "rx", "tx", "rx"; 527 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 528 status = "disabled"; 529 }; 530 531 i2c7: i2c@e6500000 { 532 #address-cells = <1>; 533 #size-cells = <0>; 534 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; 535 reg = <0 0xe6500000 0 0x425>; 536 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&mstp3_clks R8A7791_CLK_IIC0>; 538 dmas = <&dmac0 0x61>, <&dmac0 0x62>, 539 <&dmac1 0x61>, <&dmac1 0x62>; 540 dma-names = "tx", "rx", "tx", "rx"; 541 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 542 status = "disabled"; 543 }; 544 545 i2c8: i2c@e6510000 { 546 #address-cells = <1>; 547 #size-cells = <0>; 548 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic"; 549 reg = <0 0xe6510000 0 0x425>; 550 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&mstp3_clks R8A7791_CLK_IIC1>; 552 dmas = <&dmac0 0x65>, <&dmac0 0x66>, 553 <&dmac1 0x65>, <&dmac1 0x66>; 554 dma-names = "tx", "rx", "tx", "rx"; 555 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 556 status = "disabled"; 557 }; 558 559 pfc: pfc@e6060000 { 560 compatible = "renesas,pfc-r8a7791"; 561 reg = <0 0xe6060000 0 0x250>; 562 }; 563 564 mmcif0: mmc@ee200000 { 565 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif"; 566 reg = <0 0xee200000 0 0x80>; 567 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>; 569 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, 570 <&dmac1 0xd1>, <&dmac1 0xd2>; 571 dma-names = "tx", "rx", "tx", "rx"; 572 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 573 reg-io-width = <4>; 574 status = "disabled"; 575 max-frequency = <97500000>; 576 }; 577 578 sdhi0: sd@ee100000 { 579 compatible = "renesas,sdhi-r8a7791"; 580 reg = <0 0xee100000 0 0x328>; 581 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; 583 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, 584 <&dmac1 0xcd>, <&dmac1 0xce>; 585 dma-names = "tx", "rx", "tx", "rx"; 586 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 587 status = "disabled"; 588 }; 589 590 sdhi1: sd@ee140000 { 591 compatible = "renesas,sdhi-r8a7791"; 592 reg = <0 0xee140000 0 0x100>; 593 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; 595 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, 596 <&dmac1 0xc1>, <&dmac1 0xc2>; 597 dma-names = "tx", "rx", "tx", "rx"; 598 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 599 status = "disabled"; 600 }; 601 602 sdhi2: sd@ee160000 { 603 compatible = "renesas,sdhi-r8a7791"; 604 reg = <0 0xee160000 0 0x100>; 605 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; 607 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, 608 <&dmac1 0xd3>, <&dmac1 0xd4>; 609 dma-names = "tx", "rx", "tx", "rx"; 610 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 611 status = "disabled"; 612 }; 613 614 scifa0: serial@e6c40000 { 615 compatible = "renesas,scifa-r8a7791", 616 "renesas,rcar-gen2-scifa", "renesas,scifa"; 617 reg = <0 0xe6c40000 0 64>; 618 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>; 620 clock-names = "fck"; 621 dmas = <&dmac0 0x21>, <&dmac0 0x22>, 622 <&dmac1 0x21>, <&dmac1 0x22>; 623 dma-names = "tx", "rx", "tx", "rx"; 624 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 625 status = "disabled"; 626 }; 627 628 scifa1: serial@e6c50000 { 629 compatible = "renesas,scifa-r8a7791", 630 "renesas,rcar-gen2-scifa", "renesas,scifa"; 631 reg = <0 0xe6c50000 0 64>; 632 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>; 634 clock-names = "fck"; 635 dmas = <&dmac0 0x25>, <&dmac0 0x26>, 636 <&dmac1 0x25>, <&dmac1 0x26>; 637 dma-names = "tx", "rx", "tx", "rx"; 638 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 639 status = "disabled"; 640 }; 641 642 scifa2: serial@e6c60000 { 643 compatible = "renesas,scifa-r8a7791", 644 "renesas,rcar-gen2-scifa", "renesas,scifa"; 645 reg = <0 0xe6c60000 0 64>; 646 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>; 648 clock-names = "fck"; 649 dmas = <&dmac0 0x27>, <&dmac0 0x28>, 650 <&dmac1 0x27>, <&dmac1 0x28>; 651 dma-names = "tx", "rx", "tx", "rx"; 652 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 653 status = "disabled"; 654 }; 655 656 scifa3: serial@e6c70000 { 657 compatible = "renesas,scifa-r8a7791", 658 "renesas,rcar-gen2-scifa", "renesas,scifa"; 659 reg = <0 0xe6c70000 0 64>; 660 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>; 662 clock-names = "fck"; 663 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, 664 <&dmac1 0x1b>, <&dmac1 0x1c>; 665 dma-names = "tx", "rx", "tx", "rx"; 666 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 667 status = "disabled"; 668 }; 669 670 scifa4: serial@e6c78000 { 671 compatible = "renesas,scifa-r8a7791", 672 "renesas,rcar-gen2-scifa", "renesas,scifa"; 673 reg = <0 0xe6c78000 0 64>; 674 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>; 676 clock-names = "fck"; 677 dmas = <&dmac0 0x1f>, <&dmac0 0x20>, 678 <&dmac1 0x1f>, <&dmac1 0x20>; 679 dma-names = "tx", "rx", "tx", "rx"; 680 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 681 status = "disabled"; 682 }; 683 684 scifa5: serial@e6c80000 { 685 compatible = "renesas,scifa-r8a7791", 686 "renesas,rcar-gen2-scifa", "renesas,scifa"; 687 reg = <0 0xe6c80000 0 64>; 688 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>; 690 clock-names = "fck"; 691 dmas = <&dmac0 0x23>, <&dmac0 0x24>, 692 <&dmac1 0x23>, <&dmac1 0x24>; 693 dma-names = "tx", "rx", "tx", "rx"; 694 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 695 status = "disabled"; 696 }; 697 698 scifb0: serial@e6c20000 { 699 compatible = "renesas,scifb-r8a7791", 700 "renesas,rcar-gen2-scifb", "renesas,scifb"; 701 reg = <0 0xe6c20000 0 64>; 702 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>; 704 clock-names = "fck"; 705 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, 706 <&dmac1 0x3d>, <&dmac1 0x3e>; 707 dma-names = "tx", "rx", "tx", "rx"; 708 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 709 status = "disabled"; 710 }; 711 712 scifb1: serial@e6c30000 { 713 compatible = "renesas,scifb-r8a7791", 714 "renesas,rcar-gen2-scifb", "renesas,scifb"; 715 reg = <0 0xe6c30000 0 64>; 716 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>; 718 clock-names = "fck"; 719 dmas = <&dmac0 0x19>, <&dmac0 0x1a>, 720 <&dmac1 0x19>, <&dmac1 0x1a>; 721 dma-names = "tx", "rx", "tx", "rx"; 722 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 723 status = "disabled"; 724 }; 725 726 scifb2: serial@e6ce0000 { 727 compatible = "renesas,scifb-r8a7791", 728 "renesas,rcar-gen2-scifb", "renesas,scifb"; 729 reg = <0 0xe6ce0000 0 64>; 730 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>; 732 clock-names = "fck"; 733 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, 734 <&dmac1 0x1d>, <&dmac1 0x1e>; 735 dma-names = "tx", "rx", "tx", "rx"; 736 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 737 status = "disabled"; 738 }; 739 740 scif0: serial@e6e60000 { 741 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", 742 "renesas,scif"; 743 reg = <0 0xe6e60000 0 64>; 744 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 745 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>, <&zs_clk>, 746 <&scif_clk>; 747 clock-names = "fck", "brg_int", "scif_clk"; 748 dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 749 <&dmac1 0x29>, <&dmac1 0x2a>; 750 dma-names = "tx", "rx", "tx", "rx"; 751 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 752 status = "disabled"; 753 }; 754 755 scif1: serial@e6e68000 { 756 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", 757 "renesas,scif"; 758 reg = <0 0xe6e68000 0 64>; 759 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 760 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>, <&zs_clk>, 761 <&scif_clk>; 762 clock-names = "fck", "brg_int", "scif_clk"; 763 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 764 <&dmac1 0x2d>, <&dmac1 0x2e>; 765 dma-names = "tx", "rx", "tx", "rx"; 766 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 767 status = "disabled"; 768 }; 769 770 scif2: serial@e6e58000 { 771 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", 772 "renesas,scif"; 773 reg = <0 0xe6e58000 0 64>; 774 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>, <&zs_clk>, 776 <&scif_clk>; 777 clock-names = "fck", "brg_int", "scif_clk"; 778 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 779 <&dmac1 0x2b>, <&dmac1 0x2c>; 780 dma-names = "tx", "rx", "tx", "rx"; 781 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 782 status = "disabled"; 783 }; 784 785 scif3: serial@e6ea8000 { 786 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", 787 "renesas,scif"; 788 reg = <0 0xe6ea8000 0 64>; 789 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 790 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>, <&zs_clk>, 791 <&scif_clk>; 792 clock-names = "fck", "brg_int", "scif_clk"; 793 dmas = <&dmac0 0x2f>, <&dmac0 0x30>, 794 <&dmac1 0x2f>, <&dmac1 0x30>; 795 dma-names = "tx", "rx", "tx", "rx"; 796 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 797 status = "disabled"; 798 }; 799 800 scif4: serial@e6ee0000 { 801 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", 802 "renesas,scif"; 803 reg = <0 0xe6ee0000 0 64>; 804 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 805 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>, <&zs_clk>, 806 <&scif_clk>; 807 clock-names = "fck", "brg_int", "scif_clk"; 808 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, 809 <&dmac1 0xfb>, <&dmac1 0xfc>; 810 dma-names = "tx", "rx", "tx", "rx"; 811 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 812 status = "disabled"; 813 }; 814 815 scif5: serial@e6ee8000 { 816 compatible = "renesas,scif-r8a7791", "renesas,rcar-gen2-scif", 817 "renesas,scif"; 818 reg = <0 0xe6ee8000 0 64>; 819 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 820 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>, <&zs_clk>, 821 <&scif_clk>; 822 clock-names = "fck", "brg_int", "scif_clk"; 823 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, 824 <&dmac1 0xfd>, <&dmac1 0xfe>; 825 dma-names = "tx", "rx", "tx", "rx"; 826 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 827 status = "disabled"; 828 }; 829 830 hscif0: serial@e62c0000 { 831 compatible = "renesas,hscif-r8a7791", 832 "renesas,rcar-gen2-hscif", "renesas,hscif"; 833 reg = <0 0xe62c0000 0 96>; 834 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>, <&zs_clk>, 836 <&scif_clk>; 837 clock-names = "fck", "brg_int", "scif_clk"; 838 dmas = <&dmac0 0x39>, <&dmac0 0x3a>, 839 <&dmac1 0x39>, <&dmac1 0x3a>; 840 dma-names = "tx", "rx", "tx", "rx"; 841 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 842 status = "disabled"; 843 }; 844 845 hscif1: serial@e62c8000 { 846 compatible = "renesas,hscif-r8a7791", 847 "renesas,rcar-gen2-hscif", "renesas,hscif"; 848 reg = <0 0xe62c8000 0 96>; 849 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 850 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>, <&zs_clk>, 851 <&scif_clk>; 852 clock-names = "fck", "brg_int", "scif_clk"; 853 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, 854 <&dmac1 0x4d>, <&dmac1 0x4e>; 855 dma-names = "tx", "rx", "tx", "rx"; 856 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 857 status = "disabled"; 858 }; 859 860 hscif2: serial@e62d0000 { 861 compatible = "renesas,hscif-r8a7791", 862 "renesas,rcar-gen2-hscif", "renesas,hscif"; 863 reg = <0 0xe62d0000 0 96>; 864 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 865 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>, <&zs_clk>, 866 <&scif_clk>; 867 clock-names = "fck", "brg_int", "scif_clk"; 868 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, 869 <&dmac1 0x3b>, <&dmac1 0x3c>; 870 dma-names = "tx", "rx", "tx", "rx"; 871 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 872 status = "disabled"; 873 }; 874 875 ether: ethernet@ee700000 { 876 compatible = "renesas,ether-r8a7791"; 877 reg = <0 0xee700000 0 0x400>; 878 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 879 clocks = <&mstp8_clks R8A7791_CLK_ETHER>; 880 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 881 phy-mode = "rmii"; 882 #address-cells = <1>; 883 #size-cells = <0>; 884 status = "disabled"; 885 }; 886 887 avb: ethernet@e6800000 { 888 compatible = "renesas,etheravb-r8a7791", 889 "renesas,etheravb-rcar-gen2"; 890 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; 891 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>; 893 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 status = "disabled"; 897 }; 898 899 sata0: sata@ee300000 { 900 compatible = "renesas,sata-r8a7791"; 901 reg = <0 0xee300000 0 0x2000>; 902 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 903 clocks = <&mstp8_clks R8A7791_CLK_SATA0>; 904 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 905 status = "disabled"; 906 }; 907 908 sata1: sata@ee500000 { 909 compatible = "renesas,sata-r8a7791"; 910 reg = <0 0xee500000 0 0x2000>; 911 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 912 clocks = <&mstp8_clks R8A7791_CLK_SATA1>; 913 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 914 status = "disabled"; 915 }; 916 917 hsusb: usb@e6590000 { 918 compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs"; 919 reg = <0 0xe6590000 0 0x100>; 920 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 921 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; 922 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 923 <&usb_dmac1 0>, <&usb_dmac1 1>; 924 dma-names = "ch0", "ch1", "ch2", "ch3"; 925 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 926 renesas,buswait = <4>; 927 phys = <&usb0 1>; 928 phy-names = "usb"; 929 status = "disabled"; 930 }; 931 932 usbphy: usb-phy@e6590100 { 933 compatible = "renesas,usb-phy-r8a7791"; 934 reg = <0 0xe6590100 0 0x100>; 935 #address-cells = <1>; 936 #size-cells = <0>; 937 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; 938 clock-names = "usbhs"; 939 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 940 status = "disabled"; 941 942 usb0: usb-channel@0 { 943 reg = <0>; 944 #phy-cells = <1>; 945 }; 946 usb2: usb-channel@2 { 947 reg = <2>; 948 #phy-cells = <1>; 949 }; 950 }; 951 952 vin0: video@e6ef0000 { 953 compatible = "renesas,vin-r8a7791"; 954 reg = <0 0xe6ef0000 0 0x1000>; 955 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 956 clocks = <&mstp8_clks R8A7791_CLK_VIN0>; 957 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 958 status = "disabled"; 959 }; 960 961 vin1: video@e6ef1000 { 962 compatible = "renesas,vin-r8a7791"; 963 reg = <0 0xe6ef1000 0 0x1000>; 964 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&mstp8_clks R8A7791_CLK_VIN1>; 966 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 967 status = "disabled"; 968 }; 969 970 vin2: video@e6ef2000 { 971 compatible = "renesas,vin-r8a7791"; 972 reg = <0 0xe6ef2000 0 0x1000>; 973 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&mstp8_clks R8A7791_CLK_VIN2>; 975 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 976 status = "disabled"; 977 }; 978 979 vsp1@fe928000 { 980 compatible = "renesas,vsp1"; 981 reg = <0 0xfe928000 0 0x8000>; 982 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>; 984 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 985 }; 986 987 vsp1@fe930000 { 988 compatible = "renesas,vsp1"; 989 reg = <0 0xfe930000 0 0x8000>; 990 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>; 992 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 993 }; 994 995 vsp1@fe938000 { 996 compatible = "renesas,vsp1"; 997 reg = <0 0xfe938000 0 0x8000>; 998 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>; 1000 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 1001 }; 1002 1003 du: display@feb00000 { 1004 compatible = "renesas,du-r8a7791"; 1005 reg = <0 0xfeb00000 0 0x40000>, 1006 <0 0xfeb90000 0 0x1c>; 1007 reg-names = "du", "lvds.0"; 1008 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1009 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&mstp7_clks R8A7791_CLK_DU0>, 1011 <&mstp7_clks R8A7791_CLK_DU1>, 1012 <&mstp7_clks R8A7791_CLK_LVDS0>; 1013 clock-names = "du.0", "du.1", "lvds.0"; 1014 status = "disabled"; 1015 1016 ports { 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 1020 port@0 { 1021 reg = <0>; 1022 du_out_rgb: endpoint { 1023 }; 1024 }; 1025 port@1 { 1026 reg = <1>; 1027 du_out_lvds0: endpoint { 1028 }; 1029 }; 1030 }; 1031 }; 1032 1033 can0: can@e6e80000 { 1034 compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; 1035 reg = <0 0xe6e80000 0 0x1000>; 1036 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1037 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, 1038 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; 1039 clock-names = "clkp1", "clkp2", "can_clk"; 1040 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 1041 status = "disabled"; 1042 }; 1043 1044 can1: can@e6e88000 { 1045 compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; 1046 reg = <0 0xe6e88000 0 0x1000>; 1047 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1048 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>, 1049 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; 1050 clock-names = "clkp1", "clkp2", "can_clk"; 1051 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 1052 status = "disabled"; 1053 }; 1054 1055 jpu: jpeg-codec@fe980000 { 1056 compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu"; 1057 reg = <0 0xfe980000 0 0x10300>; 1058 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1059 clocks = <&mstp1_clks R8A7791_CLK_JPU>; 1060 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 1061 }; 1062 1063 clocks { 1064 #address-cells = <2>; 1065 #size-cells = <2>; 1066 ranges; 1067 1068 /* External root clock */ 1069 extal_clk: extal { 1070 compatible = "fixed-clock"; 1071 #clock-cells = <0>; 1072 /* This value must be overriden by the board. */ 1073 clock-frequency = <0>; 1074 }; 1075 1076 /* 1077 * The external audio clocks are configured as 0 Hz fixed frequency clocks by 1078 * default. Boards that provide audio clocks should override them. 1079 */ 1080 audio_clk_a: audio_clk_a { 1081 compatible = "fixed-clock"; 1082 #clock-cells = <0>; 1083 clock-frequency = <0>; 1084 }; 1085 audio_clk_b: audio_clk_b { 1086 compatible = "fixed-clock"; 1087 #clock-cells = <0>; 1088 clock-frequency = <0>; 1089 }; 1090 audio_clk_c: audio_clk_c { 1091 compatible = "fixed-clock"; 1092 #clock-cells = <0>; 1093 clock-frequency = <0>; 1094 }; 1095 1096 /* External PCIe clock - can be overridden by the board */ 1097 pcie_bus_clk: pcie_bus { 1098 compatible = "fixed-clock"; 1099 #clock-cells = <0>; 1100 clock-frequency = <0>; 1101 }; 1102 1103 /* External SCIF clock */ 1104 scif_clk: scif { 1105 compatible = "fixed-clock"; 1106 #clock-cells = <0>; 1107 /* This value must be overridden by the board. */ 1108 clock-frequency = <0>; 1109 }; 1110 1111 /* External USB clock - can be overridden by the board */ 1112 usb_extal_clk: usb_extal { 1113 compatible = "fixed-clock"; 1114 #clock-cells = <0>; 1115 clock-frequency = <48000000>; 1116 }; 1117 1118 /* External CAN clock */ 1119 can_clk: can_clk { 1120 compatible = "fixed-clock"; 1121 #clock-cells = <0>; 1122 /* This value must be overridden by the board. */ 1123 clock-frequency = <0>; 1124 }; 1125 1126 /* Special CPG clocks */ 1127 cpg_clocks: cpg_clocks@e6150000 { 1128 compatible = "renesas,r8a7791-cpg-clocks", 1129 "renesas,rcar-gen2-cpg-clocks"; 1130 reg = <0 0xe6150000 0 0x1000>; 1131 clocks = <&extal_clk &usb_extal_clk>; 1132 #clock-cells = <1>; 1133 clock-output-names = "main", "pll0", "pll1", "pll3", 1134 "lb", "qspi", "sdh", "sd0", "z", 1135 "rcan", "adsp"; 1136 #power-domain-cells = <0>; 1137 }; 1138 1139 /* Variable factor clocks */ 1140 sd2_clk: sd2@e6150078 { 1141 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; 1142 reg = <0 0xe6150078 0 4>; 1143 clocks = <&pll1_div2_clk>; 1144 #clock-cells = <0>; 1145 }; 1146 sd3_clk: sd3@e615026c { 1147 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; 1148 reg = <0 0xe615026c 0 4>; 1149 clocks = <&pll1_div2_clk>; 1150 #clock-cells = <0>; 1151 }; 1152 mmc0_clk: mmc0@e6150240 { 1153 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; 1154 reg = <0 0xe6150240 0 4>; 1155 clocks = <&pll1_div2_clk>; 1156 #clock-cells = <0>; 1157 }; 1158 ssp_clk: ssp@e6150248 { 1159 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; 1160 reg = <0 0xe6150248 0 4>; 1161 clocks = <&pll1_div2_clk>; 1162 #clock-cells = <0>; 1163 }; 1164 ssprs_clk: ssprs@e615024c { 1165 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; 1166 reg = <0 0xe615024c 0 4>; 1167 clocks = <&pll1_div2_clk>; 1168 #clock-cells = <0>; 1169 }; 1170 1171 /* Fixed factor clocks */ 1172 pll1_div2_clk: pll1_div2 { 1173 compatible = "fixed-factor-clock"; 1174 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1175 #clock-cells = <0>; 1176 clock-div = <2>; 1177 clock-mult = <1>; 1178 }; 1179 zg_clk: zg { 1180 compatible = "fixed-factor-clock"; 1181 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1182 #clock-cells = <0>; 1183 clock-div = <3>; 1184 clock-mult = <1>; 1185 }; 1186 zx_clk: zx { 1187 compatible = "fixed-factor-clock"; 1188 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1189 #clock-cells = <0>; 1190 clock-div = <3>; 1191 clock-mult = <1>; 1192 }; 1193 zs_clk: zs { 1194 compatible = "fixed-factor-clock"; 1195 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1196 #clock-cells = <0>; 1197 clock-div = <6>; 1198 clock-mult = <1>; 1199 }; 1200 hp_clk: hp { 1201 compatible = "fixed-factor-clock"; 1202 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1203 #clock-cells = <0>; 1204 clock-div = <12>; 1205 clock-mult = <1>; 1206 }; 1207 i_clk: i { 1208 compatible = "fixed-factor-clock"; 1209 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1210 #clock-cells = <0>; 1211 clock-div = <2>; 1212 clock-mult = <1>; 1213 }; 1214 b_clk: b { 1215 compatible = "fixed-factor-clock"; 1216 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1217 #clock-cells = <0>; 1218 clock-div = <12>; 1219 clock-mult = <1>; 1220 }; 1221 p_clk: p { 1222 compatible = "fixed-factor-clock"; 1223 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1224 #clock-cells = <0>; 1225 clock-div = <24>; 1226 clock-mult = <1>; 1227 }; 1228 cl_clk: cl { 1229 compatible = "fixed-factor-clock"; 1230 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1231 #clock-cells = <0>; 1232 clock-div = <48>; 1233 clock-mult = <1>; 1234 }; 1235 m2_clk: m2 { 1236 compatible = "fixed-factor-clock"; 1237 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1238 #clock-cells = <0>; 1239 clock-div = <8>; 1240 clock-mult = <1>; 1241 }; 1242 rclk_clk: rclk { 1243 compatible = "fixed-factor-clock"; 1244 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1245 #clock-cells = <0>; 1246 clock-div = <(48 * 1024)>; 1247 clock-mult = <1>; 1248 }; 1249 oscclk_clk: oscclk { 1250 compatible = "fixed-factor-clock"; 1251 clocks = <&cpg_clocks R8A7791_CLK_PLL1>; 1252 #clock-cells = <0>; 1253 clock-div = <(12 * 1024)>; 1254 clock-mult = <1>; 1255 }; 1256 zb3_clk: zb3 { 1257 compatible = "fixed-factor-clock"; 1258 clocks = <&cpg_clocks R8A7791_CLK_PLL3>; 1259 #clock-cells = <0>; 1260 clock-div = <4>; 1261 clock-mult = <1>; 1262 }; 1263 zb3d2_clk: zb3d2 { 1264 compatible = "fixed-factor-clock"; 1265 clocks = <&cpg_clocks R8A7791_CLK_PLL3>; 1266 #clock-cells = <0>; 1267 clock-div = <8>; 1268 clock-mult = <1>; 1269 }; 1270 ddr_clk: ddr { 1271 compatible = "fixed-factor-clock"; 1272 clocks = <&cpg_clocks R8A7791_CLK_PLL3>; 1273 #clock-cells = <0>; 1274 clock-div = <8>; 1275 clock-mult = <1>; 1276 }; 1277 mp_clk: mp { 1278 compatible = "fixed-factor-clock"; 1279 clocks = <&pll1_div2_clk>; 1280 #clock-cells = <0>; 1281 clock-div = <15>; 1282 clock-mult = <1>; 1283 }; 1284 cp_clk: cp { 1285 compatible = "fixed-factor-clock"; 1286 clocks = <&extal_clk>; 1287 #clock-cells = <0>; 1288 clock-div = <2>; 1289 clock-mult = <1>; 1290 }; 1291 1292 /* Gate clocks */ 1293 mstp0_clks: mstp0_clks@e6150130 { 1294 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1295 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; 1296 clocks = <&mp_clk>; 1297 #clock-cells = <1>; 1298 clock-indices = <R8A7791_CLK_MSIOF0>; 1299 clock-output-names = "msiof0"; 1300 }; 1301 mstp1_clks: mstp1_clks@e6150134 { 1302 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1303 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 1304 clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>, 1305 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, 1306 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, 1307 <&zs_clk>; 1308 #clock-cells = <1>; 1309 clock-indices = < 1310 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU 1311 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG 1312 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0 1313 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0 1314 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0 1315 R8A7791_CLK_VSP1_S 1316 >; 1317 clock-output-names = 1318 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg", 1319 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0", 1320 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy"; 1321 }; 1322 mstp2_clks: mstp2_clks@e6150138 { 1323 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1324 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; 1325 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, 1326 <&mp_clk>, <&mp_clk>, <&mp_clk>, 1327 <&zs_clk>, <&zs_clk>; 1328 #clock-cells = <1>; 1329 clock-indices = < 1330 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 1331 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 1332 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 1333 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0 1334 >; 1335 clock-output-names = 1336 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", 1337 "scifb1", "msiof1", "scifb2", 1338 "sys-dmac1", "sys-dmac0"; 1339 }; 1340 mstp3_clks: mstp3_clks@e615013c { 1341 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1342 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 1343 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>, 1344 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, 1345 <&hp_clk>, <&hp_clk>; 1346 #clock-cells = <1>; 1347 clock-indices = < 1348 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 1349 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 1350 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 1351 R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1 1352 >; 1353 clock-output-names = 1354 "tpu0", "sdhi2", "sdhi1", "sdhi0", 1355 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1", 1356 "usbdmac0", "usbdmac1"; 1357 }; 1358 mstp4_clks: mstp4_clks@e6150140 { 1359 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1360 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; 1361 clocks = <&cp_clk>; 1362 #clock-cells = <1>; 1363 clock-indices = <R8A7791_CLK_IRQC>; 1364 clock-output-names = "irqc"; 1365 }; 1366 mstp5_clks: mstp5_clks@e6150144 { 1367 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1368 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 1369 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>, 1370 <&extal_clk>, <&p_clk>; 1371 #clock-cells = <1>; 1372 clock-indices = < 1373 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1 1374 R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL 1375 R8A7791_CLK_PWM 1376 >; 1377 clock-output-names = "audmac0", "audmac1", "adsp_mod", 1378 "thermal", "pwm"; 1379 }; 1380 mstp7_clks: mstp7_clks@e615014c { 1381 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1382 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; 1383 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, 1384 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, 1385 <&zx_clk>, <&zx_clk>, <&zx_clk>; 1386 #clock-cells = <1>; 1387 clock-indices = < 1388 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 1389 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 1390 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 1391 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0 1392 R8A7791_CLK_LVDS0 1393 >; 1394 clock-output-names = 1395 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", 1396 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0"; 1397 }; 1398 mstp8_clks: mstp8_clks@e6150990 { 1399 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1400 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; 1401 clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>, 1402 <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>, 1403 <&zs_clk>; 1404 #clock-cells = <1>; 1405 clock-indices = < 1406 R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB 1407 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 1408 R8A7791_CLK_ETHERAVB R8A7791_CLK_ETHER 1409 R8A7791_CLK_SATA1 R8A7791_CLK_SATA0 1410 >; 1411 clock-output-names = 1412 "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", 1413 "etheravb", "ether", "sata1", "sata0"; 1414 }; 1415 mstp9_clks: mstp9_clks@e6150994 { 1416 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1417 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; 1418 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, 1419 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, 1420 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>, 1421 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, 1422 <&hp_clk>, <&hp_clk>; 1423 #clock-cells = <1>; 1424 clock-indices = < 1425 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 1426 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 1427 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 1428 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2 1429 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 1430 >; 1431 clock-output-names = 1432 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", 1433 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", 1434 "i2c1", "i2c0"; 1435 }; 1436 mstp10_clks: mstp10_clks@e6150998 { 1437 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1438 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; 1439 clocks = <&p_clk>, 1440 <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, 1441 <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, 1442 <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, 1443 <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, 1444 <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, 1445 <&p_clk>, 1446 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, 1447 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, 1448 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, 1449 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, 1450 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, 1451 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, 1452 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>; 1453 1454 #clock-cells = <1>; 1455 clock-indices = < 1456 R8A7791_CLK_SSI_ALL 1457 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5 1458 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0 1459 R8A7791_CLK_SCU_ALL 1460 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0 1461 R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0 1462 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5 1463 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0 1464 >; 1465 clock-output-names = 1466 "ssi-all", 1467 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", 1468 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", 1469 "scu-all", 1470 "scu-dvc1", "scu-dvc0", 1471 "scu-ctu1-mix1", "scu-ctu0-mix0", 1472 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", 1473 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; 1474 }; 1475 mstp11_clks: mstp11_clks@e615099c { 1476 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1477 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; 1478 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; 1479 #clock-cells = <1>; 1480 clock-indices = < 1481 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5 1482 >; 1483 clock-output-names = "scifa3", "scifa4", "scifa5"; 1484 }; 1485 }; 1486 1487 sysc: system-controller@e6180000 { 1488 compatible = "renesas,r8a7791-sysc"; 1489 reg = <0 0xe6180000 0 0x0200>; 1490 #power-domain-cells = <1>; 1491 }; 1492 1493 qspi: spi@e6b10000 { 1494 compatible = "renesas,qspi-r8a7791", "renesas,qspi"; 1495 reg = <0 0xe6b10000 0 0x2c>; 1496 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1497 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; 1498 dmas = <&dmac0 0x17>, <&dmac0 0x18>, 1499 <&dmac1 0x17>, <&dmac1 0x18>; 1500 dma-names = "tx", "rx", "tx", "rx"; 1501 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 1502 num-cs = <1>; 1503 #address-cells = <1>; 1504 #size-cells = <0>; 1505 status = "disabled"; 1506 }; 1507 1508 msiof0: spi@e6e20000 { 1509 compatible = "renesas,msiof-r8a7791"; 1510 reg = <0 0xe6e20000 0 0x0064>; 1511 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1512 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; 1513 dmas = <&dmac0 0x51>, <&dmac0 0x52>, 1514 <&dmac1 0x51>, <&dmac1 0x52>; 1515 dma-names = "tx", "rx", "tx", "rx"; 1516 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 1517 #address-cells = <1>; 1518 #size-cells = <0>; 1519 status = "disabled"; 1520 }; 1521 1522 msiof1: spi@e6e10000 { 1523 compatible = "renesas,msiof-r8a7791"; 1524 reg = <0 0xe6e10000 0 0x0064>; 1525 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1526 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; 1527 dmas = <&dmac0 0x55>, <&dmac0 0x56>, 1528 <&dmac1 0x55>, <&dmac1 0x56>; 1529 dma-names = "tx", "rx", "tx", "rx"; 1530 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 1531 #address-cells = <1>; 1532 #size-cells = <0>; 1533 status = "disabled"; 1534 }; 1535 1536 msiof2: spi@e6e00000 { 1537 compatible = "renesas,msiof-r8a7791"; 1538 reg = <0 0xe6e00000 0 0x0064>; 1539 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1540 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; 1541 dmas = <&dmac0 0x41>, <&dmac0 0x42>, 1542 <&dmac1 0x41>, <&dmac1 0x42>; 1543 dma-names = "tx", "rx", "tx", "rx"; 1544 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 1545 #address-cells = <1>; 1546 #size-cells = <0>; 1547 status = "disabled"; 1548 }; 1549 1550 xhci: usb@ee000000 { 1551 compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci"; 1552 reg = <0 0xee000000 0 0xc00>; 1553 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1554 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>; 1555 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 1556 phys = <&usb2 1>; 1557 phy-names = "usb"; 1558 status = "disabled"; 1559 }; 1560 1561 pci0: pci@ee090000 { 1562 compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2"; 1563 device_type = "pci"; 1564 reg = <0 0xee090000 0 0xc00>, 1565 <0 0xee080000 0 0x1100>; 1566 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1567 clocks = <&mstp7_clks R8A7791_CLK_EHCI>; 1568 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 1569 status = "disabled"; 1570 1571 bus-range = <0 0>; 1572 #address-cells = <3>; 1573 #size-cells = <2>; 1574 #interrupt-cells = <1>; 1575 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; 1576 interrupt-map-mask = <0xff00 0 0 0x7>; 1577 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 1578 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 1579 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1580 1581 usb@0,1 { 1582 reg = <0x800 0 0 0 0>; 1583 device_type = "pci"; 1584 phys = <&usb0 0>; 1585 phy-names = "usb"; 1586 }; 1587 1588 usb@0,2 { 1589 reg = <0x1000 0 0 0 0>; 1590 device_type = "pci"; 1591 phys = <&usb0 0>; 1592 phy-names = "usb"; 1593 }; 1594 }; 1595 1596 pci1: pci@ee0d0000 { 1597 compatible = "renesas,pci-r8a7791", "renesas,pci-rcar-gen2"; 1598 device_type = "pci"; 1599 reg = <0 0xee0d0000 0 0xc00>, 1600 <0 0xee0c0000 0 0x1100>; 1601 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1602 clocks = <&mstp7_clks R8A7791_CLK_EHCI>; 1603 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 1604 status = "disabled"; 1605 1606 bus-range = <1 1>; 1607 #address-cells = <3>; 1608 #size-cells = <2>; 1609 #interrupt-cells = <1>; 1610 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; 1611 interrupt-map-mask = <0xff00 0 0 0x7>; 1612 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 1613 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 1614 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1615 1616 usb@0,1 { 1617 reg = <0x800 0 0 0 0>; 1618 device_type = "pci"; 1619 phys = <&usb2 0>; 1620 phy-names = "usb"; 1621 }; 1622 1623 usb@0,2 { 1624 reg = <0x1000 0 0 0 0>; 1625 device_type = "pci"; 1626 phys = <&usb2 0>; 1627 phy-names = "usb"; 1628 }; 1629 }; 1630 1631 pciec: pcie@fe000000 { 1632 compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2"; 1633 reg = <0 0xfe000000 0 0x80000>; 1634 #address-cells = <3>; 1635 #size-cells = <2>; 1636 bus-range = <0x00 0xff>; 1637 device_type = "pci"; 1638 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 1639 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 1640 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 1641 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 1642 /* Map all possible DDR as inbound ranges */ 1643 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 1644 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>; 1645 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1648 #interrupt-cells = <1>; 1649 interrupt-map-mask = <0 0 0 0>; 1650 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1651 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>; 1652 clock-names = "pcie", "pcie_bus"; 1653 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 1654 status = "disabled"; 1655 }; 1656 1657 ipmmu_sy0: mmu@e6280000 { 1658 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; 1659 reg = <0 0xe6280000 0 0x1000>; 1660 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 1661 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1662 #iommu-cells = <1>; 1663 status = "disabled"; 1664 }; 1665 1666 ipmmu_sy1: mmu@e6290000 { 1667 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; 1668 reg = <0 0xe6290000 0 0x1000>; 1669 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1670 #iommu-cells = <1>; 1671 status = "disabled"; 1672 }; 1673 1674 ipmmu_ds: mmu@e6740000 { 1675 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; 1676 reg = <0 0xe6740000 0 0x1000>; 1677 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 1678 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 1679 #iommu-cells = <1>; 1680 status = "disabled"; 1681 }; 1682 1683 ipmmu_mp: mmu@ec680000 { 1684 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; 1685 reg = <0 0xec680000 0 0x1000>; 1686 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1687 #iommu-cells = <1>; 1688 status = "disabled"; 1689 }; 1690 1691 ipmmu_mx: mmu@fe951000 { 1692 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; 1693 reg = <0 0xfe951000 0 0x1000>; 1694 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 1695 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1696 #iommu-cells = <1>; 1697 status = "disabled"; 1698 }; 1699 1700 ipmmu_rt: mmu@ffc80000 { 1701 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; 1702 reg = <0 0xffc80000 0 0x1000>; 1703 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1704 #iommu-cells = <1>; 1705 status = "disabled"; 1706 }; 1707 1708 ipmmu_gp: mmu@e62a0000 { 1709 compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa"; 1710 reg = <0 0xe62a0000 0 0x1000>; 1711 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1712 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 1713 #iommu-cells = <1>; 1714 status = "disabled"; 1715 }; 1716 1717 rcar_sound: sound@ec500000 { 1718 /* 1719 * #sound-dai-cells is required 1720 * 1721 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1722 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1723 */ 1724 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2"; 1725 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1726 <0 0xec5a0000 0 0x100>, /* ADG */ 1727 <0 0xec540000 0 0x1000>, /* SSIU */ 1728 <0 0xec541000 0 0x280>, /* SSI */ 1729 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 1730 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1731 1732 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>, 1733 <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>, 1734 <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>, 1735 <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>, 1736 <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>, 1737 <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>, 1738 <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>, 1739 <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>, 1740 <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>, 1741 <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>, 1742 <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>, 1743 <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, 1744 <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, 1745 <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>, 1746 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; 1747 clock-names = "ssi-all", 1748 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", 1749 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", 1750 "src.9", "src.8", "src.7", "src.6", "src.5", 1751 "src.4", "src.3", "src.2", "src.1", "src.0", 1752 "ctu.0", "ctu.1", 1753 "mix.0", "mix.1", 1754 "dvc.0", "dvc.1", 1755 "clk_a", "clk_b", "clk_c", "clk_i"; 1756 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 1757 1758 status = "disabled"; 1759 1760 rcar_sound,dvc { 1761 dvc0: dvc-0 { 1762 dmas = <&audma0 0xbc>; 1763 dma-names = "tx"; 1764 }; 1765 dvc1: dvc-1 { 1766 dmas = <&audma0 0xbe>; 1767 dma-names = "tx"; 1768 }; 1769 }; 1770 1771 rcar_sound,mix { 1772 mix0: mix-0 { }; 1773 mix1: mix-1 { }; 1774 }; 1775 1776 rcar_sound,ctu { 1777 ctu00: ctu-0 { }; 1778 ctu01: ctu-1 { }; 1779 ctu02: ctu-2 { }; 1780 ctu03: ctu-3 { }; 1781 ctu10: ctu-4 { }; 1782 ctu11: ctu-5 { }; 1783 ctu12: ctu-6 { }; 1784 ctu13: ctu-7 { }; 1785 }; 1786 1787 rcar_sound,src { 1788 src0: src-0 { 1789 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1790 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1791 dma-names = "rx", "tx"; 1792 }; 1793 src1: src-1 { 1794 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1795 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1796 dma-names = "rx", "tx"; 1797 }; 1798 src2: src-2 { 1799 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1800 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1801 dma-names = "rx", "tx"; 1802 }; 1803 src3: src-3 { 1804 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1805 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1806 dma-names = "rx", "tx"; 1807 }; 1808 src4: src-4 { 1809 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1810 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1811 dma-names = "rx", "tx"; 1812 }; 1813 src5: src-5 { 1814 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1815 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1816 dma-names = "rx", "tx"; 1817 }; 1818 src6: src-6 { 1819 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1820 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1821 dma-names = "rx", "tx"; 1822 }; 1823 src7: src-7 { 1824 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1825 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1826 dma-names = "rx", "tx"; 1827 }; 1828 src8: src-8 { 1829 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1830 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1831 dma-names = "rx", "tx"; 1832 }; 1833 src9: src-9 { 1834 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1835 dmas = <&audma0 0x97>, <&audma1 0xba>; 1836 dma-names = "rx", "tx"; 1837 }; 1838 }; 1839 1840 rcar_sound,ssi { 1841 ssi0: ssi-0 { 1842 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1843 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; 1844 dma-names = "rx", "tx", "rxu", "txu"; 1845 }; 1846 ssi1: ssi-1 { 1847 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1848 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; 1849 dma-names = "rx", "tx", "rxu", "txu"; 1850 }; 1851 ssi2: ssi-2 { 1852 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1853 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; 1854 dma-names = "rx", "tx", "rxu", "txu"; 1855 }; 1856 ssi3: ssi-3 { 1857 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1858 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; 1859 dma-names = "rx", "tx", "rxu", "txu"; 1860 }; 1861 ssi4: ssi-4 { 1862 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1863 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; 1864 dma-names = "rx", "tx", "rxu", "txu"; 1865 }; 1866 ssi5: ssi-5 { 1867 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1868 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; 1869 dma-names = "rx", "tx", "rxu", "txu"; 1870 }; 1871 ssi6: ssi-6 { 1872 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1873 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; 1874 dma-names = "rx", "tx", "rxu", "txu"; 1875 }; 1876 ssi7: ssi-7 { 1877 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1878 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; 1879 dma-names = "rx", "tx", "rxu", "txu"; 1880 }; 1881 ssi8: ssi-8 { 1882 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1883 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; 1884 dma-names = "rx", "tx", "rxu", "txu"; 1885 }; 1886 ssi9: ssi-9 { 1887 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1888 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; 1889 dma-names = "rx", "tx", "rxu", "txu"; 1890 }; 1891 }; 1892 }; 1893}; 1894