1 #ifndef __ASM_ARM_CPUTYPE_H
2 #define __ASM_ARM_CPUTYPE_H
3
4 #include <linux/stringify.h>
5 #include <linux/kernel.h>
6
7 #define CPUID_ID 0
8 #define CPUID_CACHETYPE 1
9 #define CPUID_TCM 2
10 #define CPUID_TLBTYPE 3
11 #define CPUID_MPUIR 4
12 #define CPUID_MPIDR 5
13 #define CPUID_REVIDR 6
14
15 #ifdef CONFIG_CPU_V7M
16 #define CPUID_EXT_PFR0 0x40
17 #define CPUID_EXT_PFR1 0x44
18 #define CPUID_EXT_DFR0 0x48
19 #define CPUID_EXT_AFR0 0x4c
20 #define CPUID_EXT_MMFR0 0x50
21 #define CPUID_EXT_MMFR1 0x54
22 #define CPUID_EXT_MMFR2 0x58
23 #define CPUID_EXT_MMFR3 0x5c
24 #define CPUID_EXT_ISAR0 0x60
25 #define CPUID_EXT_ISAR1 0x64
26 #define CPUID_EXT_ISAR2 0x68
27 #define CPUID_EXT_ISAR3 0x6c
28 #define CPUID_EXT_ISAR4 0x70
29 #define CPUID_EXT_ISAR5 0x74
30 #else
31 #define CPUID_EXT_PFR0 "c1, 0"
32 #define CPUID_EXT_PFR1 "c1, 1"
33 #define CPUID_EXT_DFR0 "c1, 2"
34 #define CPUID_EXT_AFR0 "c1, 3"
35 #define CPUID_EXT_MMFR0 "c1, 4"
36 #define CPUID_EXT_MMFR1 "c1, 5"
37 #define CPUID_EXT_MMFR2 "c1, 6"
38 #define CPUID_EXT_MMFR3 "c1, 7"
39 #define CPUID_EXT_ISAR0 "c2, 0"
40 #define CPUID_EXT_ISAR1 "c2, 1"
41 #define CPUID_EXT_ISAR2 "c2, 2"
42 #define CPUID_EXT_ISAR3 "c2, 3"
43 #define CPUID_EXT_ISAR4 "c2, 4"
44 #define CPUID_EXT_ISAR5 "c2, 5"
45 #endif
46
47 #define MPIDR_SMP_BITMASK (0x3 << 30)
48 #define MPIDR_SMP_VALUE (0x2 << 30)
49
50 #define MPIDR_MT_BITMASK (0x1 << 24)
51
52 #define MPIDR_HWID_BITMASK 0xFFFFFF
53
54 #define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
55
56 #define MPIDR_LEVEL_BITS 8
57 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
58 #define MPIDR_LEVEL_SHIFT(level) (MPIDR_LEVEL_BITS * level)
59
60 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
61 ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
62
63 #define ARM_CPU_IMP_ARM 0x41
64 #define ARM_CPU_IMP_DEC 0x44
65 #define ARM_CPU_IMP_INTEL 0x69
66
67 /* ARM implemented processors */
68 #define ARM_CPU_PART_ARM1136 0x4100b360
69 #define ARM_CPU_PART_ARM1156 0x4100b560
70 #define ARM_CPU_PART_ARM1176 0x4100b760
71 #define ARM_CPU_PART_ARM11MPCORE 0x4100b020
72 #define ARM_CPU_PART_CORTEX_A8 0x4100c080
73 #define ARM_CPU_PART_CORTEX_A9 0x4100c090
74 #define ARM_CPU_PART_CORTEX_A5 0x4100c050
75 #define ARM_CPU_PART_CORTEX_A7 0x4100c070
76 #define ARM_CPU_PART_CORTEX_A12 0x4100c0d0
77 #define ARM_CPU_PART_CORTEX_A17 0x4100c0e0
78 #define ARM_CPU_PART_CORTEX_A15 0x4100c0f0
79 #define ARM_CPU_PART_MASK 0xff00fff0
80
81 /* DEC implemented cores */
82 #define ARM_CPU_PART_SA1100 0x4400a110
83
84 /* Intel implemented cores */
85 #define ARM_CPU_PART_SA1110 0x6900b110
86 #define ARM_CPU_REV_SA1110_A0 0
87 #define ARM_CPU_REV_SA1110_B0 4
88 #define ARM_CPU_REV_SA1110_B1 5
89 #define ARM_CPU_REV_SA1110_B2 6
90 #define ARM_CPU_REV_SA1110_B4 8
91
92 #define ARM_CPU_XSCALE_ARCH_MASK 0xe000
93 #define ARM_CPU_XSCALE_ARCH_V1 0x2000
94 #define ARM_CPU_XSCALE_ARCH_V2 0x4000
95 #define ARM_CPU_XSCALE_ARCH_V3 0x6000
96
97 /* Qualcomm implemented cores */
98 #define ARM_CPU_PART_SCORPION 0x510002d0
99
100 extern unsigned int processor_id;
101
102 #ifdef CONFIG_CPU_CP15
103 #define read_cpuid(reg) \
104 ({ \
105 unsigned int __val; \
106 asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
107 : "=r" (__val) \
108 : \
109 : "cc"); \
110 __val; \
111 })
112
113 /*
114 * The memory clobber prevents gcc 4.5 from reordering the mrc before
115 * any is_smp() tests, which can cause undefined instruction aborts on
116 * ARM1136 r0 due to the missing extended CP15 registers.
117 */
118 #define read_cpuid_ext(ext_reg) \
119 ({ \
120 unsigned int __val; \
121 asm("mrc p15, 0, %0, c0, " ext_reg \
122 : "=r" (__val) \
123 : \
124 : "memory"); \
125 __val; \
126 })
127
128 #elif defined(CONFIG_CPU_V7M)
129
130 #include <asm/io.h>
131 #include <asm/v7m.h>
132
133 #define read_cpuid(reg) \
134 ({ \
135 WARN_ON_ONCE(1); \
136 0; \
137 })
138
read_cpuid_ext(unsigned offset)139 static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
140 {
141 return readl(BASEADDR_V7M_SCB + offset);
142 }
143
144 #else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
145
146 /*
147 * read_cpuid and read_cpuid_ext should only ever be called on machines that
148 * have cp15 so warn on other usages.
149 */
150 #define read_cpuid(reg) \
151 ({ \
152 WARN_ON_ONCE(1); \
153 0; \
154 })
155
156 #define read_cpuid_ext(reg) read_cpuid(reg)
157
158 #endif /* ifdef CONFIG_CPU_CP15 / else */
159
160 #ifdef CONFIG_CPU_CP15
161 /*
162 * The CPU ID never changes at run time, so we might as well tell the
163 * compiler that it's constant. Use this function to read the CPU ID
164 * rather than directly reading processor_id or read_cpuid() directly.
165 */
read_cpuid_id(void)166 static inline unsigned int __attribute_const__ read_cpuid_id(void)
167 {
168 return read_cpuid(CPUID_ID);
169 }
170
read_cpuid_cachetype(void)171 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
172 {
173 return read_cpuid(CPUID_CACHETYPE);
174 }
175
176 #elif defined(CONFIG_CPU_V7M)
177
read_cpuid_id(void)178 static inline unsigned int __attribute_const__ read_cpuid_id(void)
179 {
180 return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
181 }
182
read_cpuid_cachetype(void)183 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
184 {
185 return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR);
186 }
187
188 #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
189
read_cpuid_id(void)190 static inline unsigned int __attribute_const__ read_cpuid_id(void)
191 {
192 return processor_id;
193 }
194
195 #endif /* ifdef CONFIG_CPU_CP15 / else */
196
read_cpuid_implementor(void)197 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
198 {
199 return (read_cpuid_id() & 0xFF000000) >> 24;
200 }
201
read_cpuid_revision(void)202 static inline unsigned int __attribute_const__ read_cpuid_revision(void)
203 {
204 return read_cpuid_id() & 0x0000000f;
205 }
206
207 /*
208 * The CPU part number is meaningless without referring to the CPU
209 * implementer: implementers are free to define their own part numbers
210 * which are permitted to clash with other implementer part numbers.
211 */
read_cpuid_part(void)212 static inline unsigned int __attribute_const__ read_cpuid_part(void)
213 {
214 return read_cpuid_id() & ARM_CPU_PART_MASK;
215 }
216
read_cpuid_part_number(void)217 static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void)
218 {
219 return read_cpuid_id() & 0xFFF0;
220 }
221
xscale_cpu_arch_version(void)222 static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
223 {
224 return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK;
225 }
226
read_cpuid_tcmstatus(void)227 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
228 {
229 return read_cpuid(CPUID_TCM);
230 }
231
read_cpuid_mpidr(void)232 static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
233 {
234 return read_cpuid(CPUID_MPIDR);
235 }
236
237 /* StrongARM-11x0 CPUs */
238 #define cpu_is_sa1100() (read_cpuid_part() == ARM_CPU_PART_SA1100)
239 #define cpu_is_sa1110() (read_cpuid_part() == ARM_CPU_PART_SA1110)
240
241 /*
242 * Intel's XScale3 core supports some v6 features (supersections, L2)
243 * but advertises itself as v5 as it does not support the v6 ISA. For
244 * this reason, we need a way to explicitly test for this type of CPU.
245 */
246 #ifndef CONFIG_CPU_XSC3
247 #define cpu_is_xsc3() 0
248 #else
cpu_is_xsc3(void)249 static inline int cpu_is_xsc3(void)
250 {
251 unsigned int id;
252 id = read_cpuid_id() & 0xffffe000;
253 /* It covers both Intel ID and Marvell ID */
254 if ((id == 0x69056000) || (id == 0x56056000))
255 return 1;
256
257 return 0;
258 }
259 #endif
260
261 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) && \
262 !defined(CONFIG_CPU_MOHAWK)
263 #define cpu_is_xscale_family() 0
264 #else
cpu_is_xscale_family(void)265 static inline int cpu_is_xscale_family(void)
266 {
267 unsigned int id;
268 id = read_cpuid_id() & 0xffffe000;
269
270 switch (id) {
271 case 0x69052000: /* Intel XScale 1 */
272 case 0x69054000: /* Intel XScale 2 */
273 case 0x69056000: /* Intel XScale 3 */
274 case 0x56056000: /* Marvell XScale 3 */
275 case 0x56158000: /* Marvell Mohawk */
276 return 1;
277 }
278
279 return 0;
280 }
281 #endif
282
283 /*
284 * Marvell's PJ4 and PJ4B cores are based on V7 version,
285 * but require a specical sequence for enabling coprocessors.
286 * For this reason, we need a way to distinguish them.
287 */
288 #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
cpu_is_pj4(void)289 static inline int cpu_is_pj4(void)
290 {
291 unsigned int id;
292
293 id = read_cpuid_id();
294 if ((id & 0xff0fff00) == 0x560f5800)
295 return 1;
296
297 return 0;
298 }
299 #else
300 #define cpu_is_pj4() 0
301 #endif
302
cpuid_feature_extract_field(u32 features,int field)303 static inline int __attribute_const__ cpuid_feature_extract_field(u32 features,
304 int field)
305 {
306 int feature = (features >> field) & 15;
307
308 /* feature registers are signed values */
309 if (feature > 7)
310 feature -= 16;
311
312 return feature;
313 }
314
315 #define cpuid_feature_extract(reg, field) \
316 cpuid_feature_extract_field(read_cpuid_ext(reg), field)
317
318 #endif
319