1 /*
2 * Copyright (C) 2013 Texas Instruments Incorporated
3 *
4 * Hwmod present only in AM43x and those that differ other than register
5 * offsets as compared to AM335x.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/platform_data/gpio-omap.h>
18 #include <linux/platform_data/spi-omap2-mcspi.h>
19 #include "omap_hwmod.h"
20 #include "omap_hwmod_33xx_43xx_common_data.h"
21 #include "prcm43xx.h"
22 #include "omap_hwmod_common_data.h"
23 #include "hdq1w.h"
24
25
26 /* IP blocks */
27 static struct omap_hwmod am43xx_emif_hwmod = {
28 .name = "emif",
29 .class = &am33xx_emif_hwmod_class,
30 .clkdm_name = "emif_clkdm",
31 .flags = HWMOD_INIT_NO_IDLE,
32 .main_clk = "dpll_ddr_m2_ck",
33 .prcm = {
34 .omap4 = {
35 .clkctrl_offs = AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET,
36 .modulemode = MODULEMODE_SWCTRL,
37 },
38 },
39 };
40
41 static struct omap_hwmod am43xx_l4_hs_hwmod = {
42 .name = "l4_hs",
43 .class = &am33xx_l4_hwmod_class,
44 .clkdm_name = "l3_clkdm",
45 .flags = HWMOD_INIT_NO_IDLE,
46 .main_clk = "l4hs_gclk",
47 .prcm = {
48 .omap4 = {
49 .clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
50 .modulemode = MODULEMODE_SWCTRL,
51 },
52 },
53 };
54
55 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
56 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
57 };
58
59 static struct omap_hwmod am43xx_wkup_m3_hwmod = {
60 .name = "wkup_m3",
61 .class = &am33xx_wkup_m3_hwmod_class,
62 .clkdm_name = "l4_wkup_aon_clkdm",
63 /* Keep hardreset asserted */
64 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
65 .main_clk = "sys_clkin_ck",
66 .prcm = {
67 .omap4 = {
68 .clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
69 .rstctrl_offs = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
70 .rstst_offs = AM43XX_RM_WKUP_RSTST_OFFSET,
71 .modulemode = MODULEMODE_SWCTRL,
72 },
73 },
74 .rst_lines = am33xx_wkup_m3_resets,
75 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
76 };
77
78 static struct omap_hwmod am43xx_control_hwmod = {
79 .name = "control",
80 .class = &am33xx_control_hwmod_class,
81 .clkdm_name = "l4_wkup_clkdm",
82 .flags = HWMOD_INIT_NO_IDLE,
83 .main_clk = "sys_clkin_ck",
84 .prcm = {
85 .omap4 = {
86 .clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
87 .modulemode = MODULEMODE_SWCTRL,
88 },
89 },
90 };
91
92 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
93 { .role = "dbclk", .clk = "gpio0_dbclk" },
94 };
95
96 static struct omap_hwmod am43xx_gpio0_hwmod = {
97 .name = "gpio1",
98 .class = &am33xx_gpio_hwmod_class,
99 .clkdm_name = "l4_wkup_clkdm",
100 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
101 .main_clk = "sys_clkin_ck",
102 .prcm = {
103 .omap4 = {
104 .clkctrl_offs = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
105 .modulemode = MODULEMODE_SWCTRL,
106 },
107 },
108 .opt_clks = gpio0_opt_clks,
109 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
110 .dev_attr = &gpio_dev_attr,
111 };
112
113 static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
114 .rev_offs = 0x0,
115 .sysc_offs = 0x4,
116 .sysc_flags = SYSC_HAS_SIDLEMODE,
117 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
118 .sysc_fields = &omap_hwmod_sysc_type1,
119 };
120
121 static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
122 .name = "synctimer",
123 .sysc = &am43xx_synctimer_sysc,
124 };
125
126 static struct omap_hwmod am43xx_synctimer_hwmod = {
127 .name = "counter_32k",
128 .class = &am43xx_synctimer_hwmod_class,
129 .clkdm_name = "l4_wkup_aon_clkdm",
130 .flags = HWMOD_SWSUP_SIDLE,
131 .main_clk = "synctimer_32kclk",
132 .prcm = {
133 .omap4 = {
134 .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
135 .modulemode = MODULEMODE_SWCTRL,
136 },
137 },
138 };
139
140 static struct omap_hwmod am43xx_timer8_hwmod = {
141 .name = "timer8",
142 .class = &am33xx_timer_hwmod_class,
143 .clkdm_name = "l4ls_clkdm",
144 .main_clk = "timer8_fck",
145 .prcm = {
146 .omap4 = {
147 .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
148 .modulemode = MODULEMODE_SWCTRL,
149 },
150 },
151 };
152
153 static struct omap_hwmod am43xx_timer9_hwmod = {
154 .name = "timer9",
155 .class = &am33xx_timer_hwmod_class,
156 .clkdm_name = "l4ls_clkdm",
157 .main_clk = "timer9_fck",
158 .prcm = {
159 .omap4 = {
160 .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
161 .modulemode = MODULEMODE_SWCTRL,
162 },
163 },
164 };
165
166 static struct omap_hwmod am43xx_timer10_hwmod = {
167 .name = "timer10",
168 .class = &am33xx_timer_hwmod_class,
169 .clkdm_name = "l4ls_clkdm",
170 .main_clk = "timer10_fck",
171 .prcm = {
172 .omap4 = {
173 .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
174 .modulemode = MODULEMODE_SWCTRL,
175 },
176 },
177 };
178
179 static struct omap_hwmod am43xx_timer11_hwmod = {
180 .name = "timer11",
181 .class = &am33xx_timer_hwmod_class,
182 .clkdm_name = "l4ls_clkdm",
183 .main_clk = "timer11_fck",
184 .prcm = {
185 .omap4 = {
186 .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
187 .modulemode = MODULEMODE_SWCTRL,
188 },
189 },
190 };
191
192 static struct omap_hwmod am43xx_epwmss3_hwmod = {
193 .name = "epwmss3",
194 .class = &am33xx_epwmss_hwmod_class,
195 .clkdm_name = "l4ls_clkdm",
196 .main_clk = "l4ls_gclk",
197 .prcm = {
198 .omap4 = {
199 .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
200 .modulemode = MODULEMODE_SWCTRL,
201 },
202 },
203 };
204
205 static struct omap_hwmod am43xx_epwmss4_hwmod = {
206 .name = "epwmss4",
207 .class = &am33xx_epwmss_hwmod_class,
208 .clkdm_name = "l4ls_clkdm",
209 .main_clk = "l4ls_gclk",
210 .prcm = {
211 .omap4 = {
212 .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
213 .modulemode = MODULEMODE_SWCTRL,
214 },
215 },
216 };
217
218 static struct omap_hwmod am43xx_epwmss5_hwmod = {
219 .name = "epwmss5",
220 .class = &am33xx_epwmss_hwmod_class,
221 .clkdm_name = "l4ls_clkdm",
222 .main_clk = "l4ls_gclk",
223 .prcm = {
224 .omap4 = {
225 .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
226 .modulemode = MODULEMODE_SWCTRL,
227 },
228 },
229 };
230
231 static struct omap_hwmod am43xx_spi2_hwmod = {
232 .name = "spi2",
233 .class = &am33xx_spi_hwmod_class,
234 .clkdm_name = "l4ls_clkdm",
235 .main_clk = "dpll_per_m2_div4_ck",
236 .prcm = {
237 .omap4 = {
238 .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
239 .modulemode = MODULEMODE_SWCTRL,
240 },
241 },
242 .dev_attr = &mcspi_attrib,
243 };
244
245 static struct omap_hwmod am43xx_spi3_hwmod = {
246 .name = "spi3",
247 .class = &am33xx_spi_hwmod_class,
248 .clkdm_name = "l4ls_clkdm",
249 .main_clk = "dpll_per_m2_div4_ck",
250 .prcm = {
251 .omap4 = {
252 .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
253 .modulemode = MODULEMODE_SWCTRL,
254 },
255 },
256 .dev_attr = &mcspi_attrib,
257 };
258
259 static struct omap_hwmod am43xx_spi4_hwmod = {
260 .name = "spi4",
261 .class = &am33xx_spi_hwmod_class,
262 .clkdm_name = "l4ls_clkdm",
263 .main_clk = "dpll_per_m2_div4_ck",
264 .prcm = {
265 .omap4 = {
266 .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
267 .modulemode = MODULEMODE_SWCTRL,
268 },
269 },
270 .dev_attr = &mcspi_attrib,
271 };
272
273 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
274 { .role = "dbclk", .clk = "gpio4_dbclk" },
275 };
276
277 static struct omap_hwmod am43xx_gpio4_hwmod = {
278 .name = "gpio5",
279 .class = &am33xx_gpio_hwmod_class,
280 .clkdm_name = "l4ls_clkdm",
281 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
282 .main_clk = "l4ls_gclk",
283 .prcm = {
284 .omap4 = {
285 .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
286 .modulemode = MODULEMODE_SWCTRL,
287 },
288 },
289 .opt_clks = gpio4_opt_clks,
290 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
291 .dev_attr = &gpio_dev_attr,
292 };
293
294 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
295 { .role = "dbclk", .clk = "gpio5_dbclk" },
296 };
297
298 static struct omap_hwmod am43xx_gpio5_hwmod = {
299 .name = "gpio6",
300 .class = &am33xx_gpio_hwmod_class,
301 .clkdm_name = "l4ls_clkdm",
302 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
303 .main_clk = "l4ls_gclk",
304 .prcm = {
305 .omap4 = {
306 .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
307 .modulemode = MODULEMODE_SWCTRL,
308 },
309 },
310 .opt_clks = gpio5_opt_clks,
311 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
312 .dev_attr = &gpio_dev_attr,
313 };
314
315 static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
316 .name = "ocp2scp",
317 };
318
319 static struct omap_hwmod am43xx_ocp2scp0_hwmod = {
320 .name = "ocp2scp0",
321 .class = &am43xx_ocp2scp_hwmod_class,
322 .clkdm_name = "l4ls_clkdm",
323 .main_clk = "l4ls_gclk",
324 .prcm = {
325 .omap4 = {
326 .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET,
327 .modulemode = MODULEMODE_SWCTRL,
328 },
329 },
330 };
331
332 static struct omap_hwmod am43xx_ocp2scp1_hwmod = {
333 .name = "ocp2scp1",
334 .class = &am43xx_ocp2scp_hwmod_class,
335 .clkdm_name = "l4ls_clkdm",
336 .main_clk = "l4ls_gclk",
337 .prcm = {
338 .omap4 = {
339 .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET,
340 .modulemode = MODULEMODE_SWCTRL,
341 },
342 },
343 };
344
345 static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
346 .rev_offs = 0x0000,
347 .sysc_offs = 0x0010,
348 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
349 SYSC_HAS_SIDLEMODE),
350 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
351 SIDLE_SMART_WKUP | MSTANDBY_FORCE |
352 MSTANDBY_NO | MSTANDBY_SMART |
353 MSTANDBY_SMART_WKUP),
354 .sysc_fields = &omap_hwmod_sysc_type2,
355 };
356
357 static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = {
358 .name = "usb_otg_ss",
359 .sysc = &am43xx_usb_otg_ss_sysc,
360 };
361
362 static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = {
363 .name = "usb_otg_ss0",
364 .class = &am43xx_usb_otg_ss_hwmod_class,
365 .clkdm_name = "l3s_clkdm",
366 .main_clk = "l3s_gclk",
367 .prcm = {
368 .omap4 = {
369 .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET,
370 .modulemode = MODULEMODE_SWCTRL,
371 },
372 },
373 };
374
375 static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
376 .name = "usb_otg_ss1",
377 .class = &am43xx_usb_otg_ss_hwmod_class,
378 .clkdm_name = "l3s_clkdm",
379 .main_clk = "l3s_gclk",
380 .prcm = {
381 .omap4 = {
382 .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET,
383 .modulemode = MODULEMODE_SWCTRL,
384 },
385 },
386 };
387
388 static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = {
389 .sysc_offs = 0x0010,
390 .sysc_flags = SYSC_HAS_SIDLEMODE,
391 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
392 SIDLE_SMART_WKUP),
393 .sysc_fields = &omap_hwmod_sysc_type2,
394 };
395
396 static struct omap_hwmod_class am43xx_qspi_hwmod_class = {
397 .name = "qspi",
398 .sysc = &am43xx_qspi_sysc,
399 };
400
401 static struct omap_hwmod am43xx_qspi_hwmod = {
402 .name = "qspi",
403 .class = &am43xx_qspi_hwmod_class,
404 .clkdm_name = "l3s_clkdm",
405 .main_clk = "l3s_gclk",
406 .prcm = {
407 .omap4 = {
408 .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET,
409 .modulemode = MODULEMODE_SWCTRL,
410 },
411 },
412 };
413
414 /*
415 * 'adc/tsc' class
416 * TouchScreen Controller (Analog-To-Digital Converter)
417 */
418 static struct omap_hwmod_class_sysconfig am43xx_adc_tsc_sysc = {
419 .rev_offs = 0x00,
420 .sysc_offs = 0x10,
421 .sysc_flags = SYSC_HAS_SIDLEMODE,
422 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
423 SIDLE_SMART_WKUP),
424 .sysc_fields = &omap_hwmod_sysc_type2,
425 };
426
427 static struct omap_hwmod_class am43xx_adc_tsc_hwmod_class = {
428 .name = "adc_tsc",
429 .sysc = &am43xx_adc_tsc_sysc,
430 };
431
432 static struct omap_hwmod am43xx_adc_tsc_hwmod = {
433 .name = "adc_tsc",
434 .class = &am43xx_adc_tsc_hwmod_class,
435 .clkdm_name = "l3s_tsc_clkdm",
436 .main_clk = "adc_tsc_fck",
437 .prcm = {
438 .omap4 = {
439 .clkctrl_offs = AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
440 .modulemode = MODULEMODE_SWCTRL,
441 },
442 },
443 };
444
445 /* dss */
446
447 static struct omap_hwmod am43xx_dss_core_hwmod = {
448 .name = "dss_core",
449 .class = &omap2_dss_hwmod_class,
450 .clkdm_name = "dss_clkdm",
451 .main_clk = "disp_clk",
452 .prcm = {
453 .omap4 = {
454 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
455 .modulemode = MODULEMODE_SWCTRL,
456 },
457 },
458 };
459
460 /* dispc */
461
462 static struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
463 .manager_count = 1,
464 .has_framedonetv_irq = 0
465 };
466
467 static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {
468 .rev_offs = 0x0000,
469 .sysc_offs = 0x0010,
470 .syss_offs = 0x0014,
471 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
472 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
473 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE),
474 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
475 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
476 .sysc_fields = &omap_hwmod_sysc_type1,
477 };
478
479 static struct omap_hwmod_class am43xx_dispc_hwmod_class = {
480 .name = "dispc",
481 .sysc = &am43xx_dispc_sysc,
482 };
483
484 static struct omap_hwmod am43xx_dss_dispc_hwmod = {
485 .name = "dss_dispc",
486 .class = &am43xx_dispc_hwmod_class,
487 .clkdm_name = "dss_clkdm",
488 .main_clk = "disp_clk",
489 .prcm = {
490 .omap4 = {
491 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
492 },
493 },
494 .dev_attr = &am43xx_dss_dispc_dev_attr,
495 .parent_hwmod = &am43xx_dss_core_hwmod,
496 };
497
498 /* rfbi */
499
500 static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
501 .name = "dss_rfbi",
502 .class = &omap2_rfbi_hwmod_class,
503 .clkdm_name = "dss_clkdm",
504 .main_clk = "disp_clk",
505 .prcm = {
506 .omap4 = {
507 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
508 },
509 },
510 .parent_hwmod = &am43xx_dss_core_hwmod,
511 };
512
513 /* HDQ1W */
514 static struct omap_hwmod_class_sysconfig am43xx_hdq1w_sysc = {
515 .rev_offs = 0x0000,
516 .sysc_offs = 0x0014,
517 .syss_offs = 0x0018,
518 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
519 .sysc_fields = &omap_hwmod_sysc_type1,
520 };
521
522 static struct omap_hwmod_class am43xx_hdq1w_hwmod_class = {
523 .name = "hdq1w",
524 .sysc = &am43xx_hdq1w_sysc,
525 .reset = &omap_hdq1w_reset,
526 };
527
528 static struct omap_hwmod am43xx_hdq1w_hwmod = {
529 .name = "hdq1w",
530 .class = &am43xx_hdq1w_hwmod_class,
531 .clkdm_name = "l4ls_clkdm",
532 .prcm = {
533 .omap4 = {
534 .clkctrl_offs = AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET,
535 .modulemode = MODULEMODE_SWCTRL,
536 },
537 },
538 };
539
540 static struct omap_hwmod_class_sysconfig am43xx_vpfe_sysc = {
541 .rev_offs = 0x0,
542 .sysc_offs = 0x104,
543 .sysc_flags = SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE,
544 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
545 MSTANDBY_FORCE | MSTANDBY_SMART | MSTANDBY_NO),
546 .sysc_fields = &omap_hwmod_sysc_type2,
547 };
548
549 static struct omap_hwmod_class am43xx_vpfe_hwmod_class = {
550 .name = "vpfe",
551 .sysc = &am43xx_vpfe_sysc,
552 };
553
554 static struct omap_hwmod am43xx_vpfe0_hwmod = {
555 .name = "vpfe0",
556 .class = &am43xx_vpfe_hwmod_class,
557 .clkdm_name = "l3s_clkdm",
558 .prcm = {
559 .omap4 = {
560 .modulemode = MODULEMODE_SWCTRL,
561 .clkctrl_offs = AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET,
562 },
563 },
564 };
565
566 static struct omap_hwmod am43xx_vpfe1_hwmod = {
567 .name = "vpfe1",
568 .class = &am43xx_vpfe_hwmod_class,
569 .clkdm_name = "l3s_clkdm",
570 .prcm = {
571 .omap4 = {
572 .modulemode = MODULEMODE_SWCTRL,
573 .clkctrl_offs = AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET,
574 },
575 },
576 };
577
578 /* Interfaces */
579 static struct omap_hwmod_ocp_if am43xx_l3_main__emif = {
580 .master = &am33xx_l3_main_hwmod,
581 .slave = &am43xx_emif_hwmod,
582 .clk = "dpll_core_m4_ck",
583 .user = OCP_USER_MPU | OCP_USER_SDMA,
584 };
585
586 static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
587 .master = &am33xx_l3_main_hwmod,
588 .slave = &am43xx_l4_hs_hwmod,
589 .clk = "l3s_gclk",
590 .user = OCP_USER_MPU | OCP_USER_SDMA,
591 };
592
593 static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
594 .master = &am43xx_wkup_m3_hwmod,
595 .slave = &am33xx_l4_wkup_hwmod,
596 .clk = "sys_clkin_ck",
597 .user = OCP_USER_MPU | OCP_USER_SDMA,
598 };
599
600 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
601 .master = &am33xx_l4_wkup_hwmod,
602 .slave = &am43xx_wkup_m3_hwmod,
603 .clk = "sys_clkin_ck",
604 .user = OCP_USER_MPU | OCP_USER_SDMA,
605 };
606
607 static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
608 .master = &am33xx_l3_main_hwmod,
609 .slave = &am33xx_pruss_hwmod,
610 .clk = "dpll_core_m4_ck",
611 .user = OCP_USER_MPU,
612 };
613
614 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
615 .master = &am33xx_l4_wkup_hwmod,
616 .slave = &am33xx_smartreflex0_hwmod,
617 .clk = "sys_clkin_ck",
618 .user = OCP_USER_MPU,
619 };
620
621 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
622 .master = &am33xx_l4_wkup_hwmod,
623 .slave = &am33xx_smartreflex1_hwmod,
624 .clk = "sys_clkin_ck",
625 .user = OCP_USER_MPU,
626 };
627
628 static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
629 .master = &am33xx_l4_wkup_hwmod,
630 .slave = &am43xx_control_hwmod,
631 .clk = "sys_clkin_ck",
632 .user = OCP_USER_MPU,
633 };
634
635 static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = {
636 .master = &am33xx_l4_wkup_hwmod,
637 .slave = &am33xx_i2c1_hwmod,
638 .clk = "sys_clkin_ck",
639 .user = OCP_USER_MPU,
640 };
641
642 static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
643 .master = &am33xx_l4_wkup_hwmod,
644 .slave = &am43xx_gpio0_hwmod,
645 .clk = "sys_clkin_ck",
646 .user = OCP_USER_MPU | OCP_USER_SDMA,
647 };
648
649 static struct omap_hwmod_ocp_if am43xx_l4_wkup__adc_tsc = {
650 .master = &am33xx_l4_wkup_hwmod,
651 .slave = &am43xx_adc_tsc_hwmod,
652 .clk = "dpll_core_m4_div2_ck",
653 .user = OCP_USER_MPU,
654 };
655
656 static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
657 .master = &am43xx_l4_hs_hwmod,
658 .slave = &am33xx_cpgmac0_hwmod,
659 .clk = "cpsw_125mhz_gclk",
660 .user = OCP_USER_MPU,
661 };
662
663 static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
664 .master = &am33xx_l4_wkup_hwmod,
665 .slave = &am33xx_timer1_hwmod,
666 .clk = "sys_clkin_ck",
667 .user = OCP_USER_MPU,
668 };
669
670 static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = {
671 .master = &am33xx_l4_wkup_hwmod,
672 .slave = &am33xx_uart1_hwmod,
673 .clk = "sys_clkin_ck",
674 .user = OCP_USER_MPU,
675 };
676
677 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
678 .master = &am33xx_l4_wkup_hwmod,
679 .slave = &am33xx_wd_timer1_hwmod,
680 .clk = "sys_clkin_ck",
681 .user = OCP_USER_MPU,
682 };
683
684 static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
685 .master = &am33xx_l4_wkup_hwmod,
686 .slave = &am43xx_synctimer_hwmod,
687 .clk = "sys_clkin_ck",
688 .user = OCP_USER_MPU,
689 };
690
691 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
692 .master = &am33xx_l4_ls_hwmod,
693 .slave = &am43xx_timer8_hwmod,
694 .clk = "l4ls_gclk",
695 .user = OCP_USER_MPU,
696 };
697
698 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
699 .master = &am33xx_l4_ls_hwmod,
700 .slave = &am43xx_timer9_hwmod,
701 .clk = "l4ls_gclk",
702 .user = OCP_USER_MPU,
703 };
704
705 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
706 .master = &am33xx_l4_ls_hwmod,
707 .slave = &am43xx_timer10_hwmod,
708 .clk = "l4ls_gclk",
709 .user = OCP_USER_MPU,
710 };
711
712 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
713 .master = &am33xx_l4_ls_hwmod,
714 .slave = &am43xx_timer11_hwmod,
715 .clk = "l4ls_gclk",
716 .user = OCP_USER_MPU,
717 };
718
719 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
720 .master = &am33xx_l4_ls_hwmod,
721 .slave = &am43xx_epwmss3_hwmod,
722 .clk = "l4ls_gclk",
723 .user = OCP_USER_MPU,
724 };
725
726 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
727 .master = &am33xx_l4_ls_hwmod,
728 .slave = &am43xx_epwmss4_hwmod,
729 .clk = "l4ls_gclk",
730 .user = OCP_USER_MPU,
731 };
732
733 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
734 .master = &am33xx_l4_ls_hwmod,
735 .slave = &am43xx_epwmss5_hwmod,
736 .clk = "l4ls_gclk",
737 .user = OCP_USER_MPU,
738 };
739
740 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
741 .master = &am33xx_l4_ls_hwmod,
742 .slave = &am43xx_spi2_hwmod,
743 .clk = "l4ls_gclk",
744 .user = OCP_USER_MPU,
745 };
746
747 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
748 .master = &am33xx_l4_ls_hwmod,
749 .slave = &am43xx_spi3_hwmod,
750 .clk = "l4ls_gclk",
751 .user = OCP_USER_MPU,
752 };
753
754 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
755 .master = &am33xx_l4_ls_hwmod,
756 .slave = &am43xx_spi4_hwmod,
757 .clk = "l4ls_gclk",
758 .user = OCP_USER_MPU,
759 };
760
761 static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
762 .master = &am33xx_l4_ls_hwmod,
763 .slave = &am43xx_gpio4_hwmod,
764 .clk = "l4ls_gclk",
765 .user = OCP_USER_MPU | OCP_USER_SDMA,
766 };
767
768 static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
769 .master = &am33xx_l4_ls_hwmod,
770 .slave = &am43xx_gpio5_hwmod,
771 .clk = "l4ls_gclk",
772 .user = OCP_USER_MPU | OCP_USER_SDMA,
773 };
774
775 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = {
776 .master = &am33xx_l4_ls_hwmod,
777 .slave = &am43xx_ocp2scp0_hwmod,
778 .clk = "l4ls_gclk",
779 .user = OCP_USER_MPU,
780 };
781
782 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = {
783 .master = &am33xx_l4_ls_hwmod,
784 .slave = &am43xx_ocp2scp1_hwmod,
785 .clk = "l4ls_gclk",
786 .user = OCP_USER_MPU,
787 };
788
789 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
790 .master = &am33xx_l3_s_hwmod,
791 .slave = &am43xx_usb_otg_ss0_hwmod,
792 .clk = "l3s_gclk",
793 .user = OCP_USER_MPU | OCP_USER_SDMA,
794 };
795
796 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
797 .master = &am33xx_l3_s_hwmod,
798 .slave = &am43xx_usb_otg_ss1_hwmod,
799 .clk = "l3s_gclk",
800 .user = OCP_USER_MPU | OCP_USER_SDMA,
801 };
802
803 static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
804 .master = &am33xx_l3_s_hwmod,
805 .slave = &am43xx_qspi_hwmod,
806 .clk = "l3s_gclk",
807 .user = OCP_USER_MPU | OCP_USER_SDMA,
808 };
809
810 static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {
811 .master = &am43xx_dss_core_hwmod,
812 .slave = &am33xx_l3_main_hwmod,
813 .clk = "l3_gclk",
814 .user = OCP_USER_MPU | OCP_USER_SDMA,
815 };
816
817 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {
818 .master = &am33xx_l4_ls_hwmod,
819 .slave = &am43xx_dss_core_hwmod,
820 .clk = "l4ls_gclk",
821 .user = OCP_USER_MPU | OCP_USER_SDMA,
822 };
823
824 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {
825 .master = &am33xx_l4_ls_hwmod,
826 .slave = &am43xx_dss_dispc_hwmod,
827 .clk = "l4ls_gclk",
828 .user = OCP_USER_MPU | OCP_USER_SDMA,
829 };
830
831 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
832 .master = &am33xx_l4_ls_hwmod,
833 .slave = &am43xx_dss_rfbi_hwmod,
834 .clk = "l4ls_gclk",
835 .user = OCP_USER_MPU | OCP_USER_SDMA,
836 };
837
838 static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = {
839 .master = &am33xx_l4_ls_hwmod,
840 .slave = &am43xx_hdq1w_hwmod,
841 .clk = "l4ls_gclk",
842 .user = OCP_USER_MPU | OCP_USER_SDMA,
843 };
844
845 static struct omap_hwmod_ocp_if am43xx_l3__vpfe0 = {
846 .master = &am43xx_vpfe0_hwmod,
847 .slave = &am33xx_l3_main_hwmod,
848 .clk = "l3_gclk",
849 .user = OCP_USER_MPU | OCP_USER_SDMA,
850 };
851
852 static struct omap_hwmod_ocp_if am43xx_l3__vpfe1 = {
853 .master = &am43xx_vpfe1_hwmod,
854 .slave = &am33xx_l3_main_hwmod,
855 .clk = "l3_gclk",
856 .user = OCP_USER_MPU | OCP_USER_SDMA,
857 };
858
859 static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe0 = {
860 .master = &am33xx_l4_ls_hwmod,
861 .slave = &am43xx_vpfe0_hwmod,
862 .clk = "l4ls_gclk",
863 .user = OCP_USER_MPU | OCP_USER_SDMA,
864 };
865
866 static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe1 = {
867 .master = &am33xx_l4_ls_hwmod,
868 .slave = &am43xx_vpfe1_hwmod,
869 .clk = "l4ls_gclk",
870 .user = OCP_USER_MPU | OCP_USER_SDMA,
871 };
872
873 static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
874 &am33xx_l4_wkup__synctimer,
875 &am43xx_l4_ls__timer8,
876 &am43xx_l4_ls__timer9,
877 &am43xx_l4_ls__timer10,
878 &am43xx_l4_ls__timer11,
879 &am43xx_l4_ls__epwmss3,
880 &am43xx_l4_ls__epwmss4,
881 &am43xx_l4_ls__epwmss5,
882 &am43xx_l4_ls__mcspi2,
883 &am43xx_l4_ls__mcspi3,
884 &am43xx_l4_ls__mcspi4,
885 &am43xx_l4_ls__gpio4,
886 &am43xx_l4_ls__gpio5,
887 &am43xx_l3_main__pruss,
888 &am33xx_mpu__l3_main,
889 &am33xx_mpu__prcm,
890 &am33xx_l3_s__l4_ls,
891 &am33xx_l3_s__l4_wkup,
892 &am43xx_l3_main__l4_hs,
893 &am33xx_l3_main__l3_s,
894 &am33xx_l3_main__l3_instr,
895 &am33xx_l3_main__gfx,
896 &am33xx_l3_s__l3_main,
897 &am43xx_l3_main__emif,
898 &am33xx_pruss__l3_main,
899 &am43xx_wkup_m3__l4_wkup,
900 &am33xx_gfx__l3_main,
901 &am43xx_l4_wkup__wkup_m3,
902 &am43xx_l4_wkup__control,
903 &am43xx_l4_wkup__smartreflex0,
904 &am43xx_l4_wkup__smartreflex1,
905 &am43xx_l4_wkup__uart1,
906 &am43xx_l4_wkup__timer1,
907 &am43xx_l4_wkup__i2c1,
908 &am43xx_l4_wkup__gpio0,
909 &am43xx_l4_wkup__wd_timer1,
910 &am43xx_l4_wkup__adc_tsc,
911 &am43xx_l3_s__qspi,
912 &am33xx_l4_per__dcan0,
913 &am33xx_l4_per__dcan1,
914 &am33xx_l4_per__gpio1,
915 &am33xx_l4_per__gpio2,
916 &am33xx_l4_per__gpio3,
917 &am33xx_l4_per__i2c2,
918 &am33xx_l4_per__i2c3,
919 &am33xx_l4_per__mailbox,
920 &am33xx_l4_ls__mcasp0,
921 &am33xx_l4_ls__mcasp1,
922 &am33xx_l4_ls__mmc0,
923 &am33xx_l4_ls__mmc1,
924 &am33xx_l3_s__mmc2,
925 &am33xx_l4_ls__timer2,
926 &am33xx_l4_ls__timer3,
927 &am33xx_l4_ls__timer4,
928 &am33xx_l4_ls__timer5,
929 &am33xx_l4_ls__timer6,
930 &am33xx_l4_ls__timer7,
931 &am33xx_l3_main__tpcc,
932 &am33xx_l4_ls__uart2,
933 &am33xx_l4_ls__uart3,
934 &am33xx_l4_ls__uart4,
935 &am33xx_l4_ls__uart5,
936 &am33xx_l4_ls__uart6,
937 &am33xx_l4_ls__spinlock,
938 &am33xx_l4_ls__elm,
939 &am33xx_l4_ls__epwmss0,
940 &am33xx_l4_ls__epwmss1,
941 &am33xx_l4_ls__epwmss2,
942 &am33xx_l3_s__gpmc,
943 &am33xx_l4_ls__mcspi0,
944 &am33xx_l4_ls__mcspi1,
945 &am33xx_l3_main__tptc0,
946 &am33xx_l3_main__tptc1,
947 &am33xx_l3_main__tptc2,
948 &am33xx_l3_main__ocmc,
949 &am43xx_l4_hs__cpgmac0,
950 &am33xx_cpgmac0__mdio,
951 &am33xx_l3_main__sha0,
952 &am33xx_l3_main__aes0,
953 &am43xx_l4_ls__ocp2scp0,
954 &am43xx_l4_ls__ocp2scp1,
955 &am43xx_l3_s__usbotgss0,
956 &am43xx_l3_s__usbotgss1,
957 &am43xx_dss__l3_main,
958 &am43xx_l4_ls__dss,
959 &am43xx_l4_ls__dss_dispc,
960 &am43xx_l4_ls__dss_rfbi,
961 &am43xx_l4_ls__hdq1w,
962 &am43xx_l3__vpfe0,
963 &am43xx_l3__vpfe1,
964 &am43xx_l4_ls__vpfe0,
965 &am43xx_l4_ls__vpfe1,
966 NULL,
967 };
968
969 static struct omap_hwmod_ocp_if *am43xx_rtc_hwmod_ocp_ifs[] __initdata = {
970 &am33xx_l4_wkup__rtc,
971 NULL,
972 };
973
am43xx_hwmod_init(void)974 int __init am43xx_hwmod_init(void)
975 {
976 int ret;
977
978 omap_hwmod_am43xx_reg();
979 omap_hwmod_init();
980 ret = omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
981
982 if (!ret && of_machine_is_compatible("ti,am4372"))
983 ret = omap_hwmod_register_links(am43xx_rtc_hwmod_ocp_ifs);
984
985 return ret;
986 }
987