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1 /* linux/arch/arm/mach-s3c64xx/mach-anw6410.c
2  *
3  * Copyright 2008 Openmoko, Inc.
4  * Copyright 2008 Simtec Electronics
5  *	Ben Dooks <ben@simtec.co.uk>
6  *	http://armlinux.simtec.co.uk/
7  * Copyright 2009 Kwangwoo Lee
8  * 	Kwangwoo Lee <kwangwoo.lee@gmail.com>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  *
14 */
15 
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/timer.h>
21 #include <linux/init.h>
22 #include <linux/serial_core.h>
23 #include <linux/serial_s3c.h>
24 #include <linux/platform_device.h>
25 #include <linux/io.h>
26 #include <linux/i2c.h>
27 #include <linux/fb.h>
28 #include <linux/gpio.h>
29 #include <linux/delay.h>
30 #include <linux/dm9000.h>
31 
32 #include <video/platform_lcd.h>
33 #include <video/samsung_fimd.h>
34 
35 #include <asm/mach/arch.h>
36 #include <asm/mach/map.h>
37 #include <asm/mach/irq.h>
38 
39 #include <mach/hardware.h>
40 #include <mach/map.h>
41 
42 #include <asm/irq.h>
43 #include <asm/mach-types.h>
44 
45 #include <linux/platform_data/i2c-s3c2410.h>
46 #include <plat/fb.h>
47 
48 #include <plat/devs.h>
49 #include <plat/cpu.h>
50 #include <mach/irqs.h>
51 #include <mach/regs-gpio.h>
52 #include <mach/gpio-samsung.h>
53 #include <plat/samsung-time.h>
54 
55 #include "common.h"
56 #include "regs-modem.h"
57 
58 /* DM9000 */
59 #define ANW6410_PA_DM9000	(0x18000000)
60 
61 /* A hardware buffer to control external devices is mapped at 0x30000000.
62  * It can not be read. So current status must be kept in anw6410_extdev_status.
63  */
64 #define ANW6410_VA_EXTDEV	S3C_ADDR(0x02000000)
65 #define ANW6410_PA_EXTDEV	(0x30000000)
66 
67 #define ANW6410_EN_DM9000	(1<<11)
68 #define ANW6410_EN_LCD		(1<<14)
69 
70 static __u32 anw6410_extdev_status;
71 
72 static struct s3c2410_uartcfg anw6410_uartcfgs[] __initdata = {
73 	[0] = {
74 		.hwport	     = 0,
75 		.flags	     = 0,
76 		.ucon	     = 0x3c5,
77 		.ulcon	     = 0x03,
78 		.ufcon	     = 0x51,
79 	},
80 	[1] = {
81 		.hwport	     = 1,
82 		.flags	     = 0,
83 		.ucon	     = 0x3c5,
84 		.ulcon	     = 0x03,
85 		.ufcon	     = 0x51,
86 	},
87 };
88 
89 /* framebuffer and LCD setup. */
anw6410_lcd_mode_set(void)90 static void __init anw6410_lcd_mode_set(void)
91 {
92 	u32 tmp;
93 
94 	/* set the LCD type */
95 	tmp = __raw_readl(S3C64XX_SPCON);
96 	tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
97 	tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
98 	__raw_writel(tmp, S3C64XX_SPCON);
99 
100 	/* remove the LCD bypass */
101 	tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
102 	tmp &= ~MIFPCON_LCD_BYPASS;
103 	__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
104 }
105 
106 /* GPF1 = LCD panel power
107  * GPF4 = LCD backlight control
108  */
anw6410_lcd_power_set(struct plat_lcd_data * pd,unsigned int power)109 static void anw6410_lcd_power_set(struct plat_lcd_data *pd,
110 				   unsigned int power)
111 {
112 	if (power) {
113 		anw6410_extdev_status |= (ANW6410_EN_LCD << 16);
114 		__raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
115 
116 		gpio_direction_output(S3C64XX_GPF(1), 1);
117 		gpio_direction_output(S3C64XX_GPF(4), 1);
118 	} else {
119 		anw6410_extdev_status &= ~(ANW6410_EN_LCD << 16);
120 		__raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
121 
122 		gpio_direction_output(S3C64XX_GPF(1), 0);
123 		gpio_direction_output(S3C64XX_GPF(4), 0);
124 	}
125 }
126 
127 static struct plat_lcd_data anw6410_lcd_power_data = {
128 	.set_power	= anw6410_lcd_power_set,
129 };
130 
131 static struct platform_device anw6410_lcd_powerdev = {
132 	.name			= "platform-lcd",
133 	.dev.parent		= &s3c_device_fb.dev,
134 	.dev.platform_data	= &anw6410_lcd_power_data,
135 };
136 
137 static struct s3c_fb_pd_win anw6410_fb_win0 = {
138 	.max_bpp	= 32,
139 	.default_bpp	= 16,
140 	.xres		= 800,
141 	.yres		= 480,
142 };
143 
144 static struct fb_videomode anw6410_lcd_timing = {
145 	.left_margin	= 8,
146 	.right_margin	= 13,
147 	.upper_margin	= 7,
148 	.lower_margin	= 5,
149 	.hsync_len	= 3,
150 	.vsync_len	= 1,
151 	.xres		= 800,
152 	.yres		= 480,
153 };
154 
155 /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
156 static struct s3c_fb_platdata anw6410_lcd_pdata __initdata = {
157 	.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
158 	.vtiming	= &anw6410_lcd_timing,
159 	.win[0]		= &anw6410_fb_win0,
160 	.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
161 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
162 };
163 
164 /* DM9000AEP 10/100 ethernet controller */
anw6410_dm9000_enable(void)165 static void __init anw6410_dm9000_enable(void)
166 {
167 	anw6410_extdev_status |= (ANW6410_EN_DM9000 << 16);
168 	__raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
169 }
170 
171 static struct resource anw6410_dm9000_resource[] = {
172 	[0] = DEFINE_RES_MEM(ANW6410_PA_DM9000, 4),
173 	[1] = DEFINE_RES_MEM(ANW6410_PA_DM9000 + 4, 501),
174 	[2] = DEFINE_RES_NAMED(IRQ_EINT(15), 1, NULL, IORESOURCE_IRQ \
175 					| IRQF_TRIGGER_HIGH),
176 };
177 
178 static struct dm9000_plat_data anw6410_dm9000_pdata = {
179 	.flags	  = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
180 	/* dev_addr can be set to provide hwaddr. */
181 };
182 
183 static struct platform_device anw6410_device_eth = {
184 	.name	= "dm9000",
185 	.id	= -1,
186 	.num_resources	= ARRAY_SIZE(anw6410_dm9000_resource),
187 	.resource	= anw6410_dm9000_resource,
188 	.dev	= {
189 		.platform_data  = &anw6410_dm9000_pdata,
190 	},
191 };
192 
193 static struct map_desc anw6410_iodesc[] __initdata = {
194 	{
195 		.virtual	= (unsigned long)ANW6410_VA_EXTDEV,
196 		.pfn		= __phys_to_pfn(ANW6410_PA_EXTDEV),
197 		.length		= SZ_64K,
198 		.type		= MT_DEVICE,
199 	},
200 };
201 
202 static struct platform_device *anw6410_devices[] __initdata = {
203 	&s3c_device_fb,
204 	&anw6410_lcd_powerdev,
205 	&anw6410_device_eth,
206 };
207 
anw6410_map_io(void)208 static void __init anw6410_map_io(void)
209 {
210 	s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
211 	s3c64xx_set_xtal_freq(12000000);
212 	s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
213 	samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
214 
215 	anw6410_lcd_mode_set();
216 }
217 
anw6410_machine_init(void)218 static void __init anw6410_machine_init(void)
219 {
220 	s3c_fb_set_platdata(&anw6410_lcd_pdata);
221 
222 	gpio_request(S3C64XX_GPF(1), "panel power");
223 	gpio_request(S3C64XX_GPF(4), "LCD backlight");
224 
225 	anw6410_dm9000_enable();
226 
227 	platform_add_devices(anw6410_devices, ARRAY_SIZE(anw6410_devices));
228 }
229 
230 MACHINE_START(ANW6410, "A&W6410")
231 	/* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
232 	.atag_offset	= 0x100,
233 	.nr_irqs	= S3C64XX_NR_IRQS,
234 	.init_irq	= s3c6410_init_irq,
235 	.map_io		= anw6410_map_io,
236 	.init_machine	= anw6410_machine_init,
237 	.init_time	= samsung_timer_init,
238 	.restart	= s3c64xx_restart,
239 MACHINE_END
240