1 /*
2 * Based on arch/arm/include/asm/uaccess.h
3 *
4 * Copyright (C) 2012 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18 #ifndef __ASM_UACCESS_H
19 #define __ASM_UACCESS_H
20
21 #include <asm/alternative.h>
22 #include <asm/kernel-pgtable.h>
23 #include <asm/mmu.h>
24 #include <asm/sysreg.h>
25
26 #ifndef __ASSEMBLY__
27
28 /*
29 * User space memory access functions
30 */
31 #include <linux/bitops.h>
32 #include <linux/kasan-checks.h>
33 #include <linux/string.h>
34 #include <linux/thread_info.h>
35
36 #include <asm/cpufeature.h>
37 #include <asm/processor.h>
38 #include <asm/ptrace.h>
39 #include <asm/errno.h>
40 #include <asm/memory.h>
41 #include <asm/compiler.h>
42
43 #define VERIFY_READ 0
44 #define VERIFY_WRITE 1
45
46 /*
47 * The exception table consists of pairs of relative offsets: the first
48 * is the relative offset to an instruction that is allowed to fault,
49 * and the second is the relative offset at which the program should
50 * continue. No registers are modified, so it is entirely up to the
51 * continuation code to figure out what to do.
52 *
53 * All the routines below use bits of fixup code that are out of line
54 * with the main instruction path. This means when everything is well,
55 * we don't even have to jump over them. Further, they do not intrude
56 * on our cache or tlb entries.
57 */
58
59 struct exception_table_entry
60 {
61 int insn, fixup;
62 };
63
64 #define ARCH_HAS_RELATIVE_EXTABLE
65
66 extern int fixup_exception(struct pt_regs *regs);
67
68 #define get_ds() (KERNEL_DS)
69 #define get_fs() (current_thread_info()->addr_limit)
70
set_fs(mm_segment_t fs)71 static inline void set_fs(mm_segment_t fs)
72 {
73 current_thread_info()->addr_limit = fs;
74
75 /*
76 * Prevent a mispredicted conditional call to set_fs from forwarding
77 * the wrong address limit to access_ok under speculation.
78 */
79 dsb(nsh);
80 isb();
81
82 /*
83 * Enable/disable UAO so that copy_to_user() etc can access
84 * kernel memory with the unprivileged instructions.
85 */
86 if (IS_ENABLED(CONFIG_ARM64_UAO) && fs == KERNEL_DS)
87 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO));
88 else
89 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO,
90 CONFIG_ARM64_UAO));
91 }
92
93 #define segment_eq(a, b) ((a) == (b))
94
95 /*
96 * Test whether a block of memory is a valid user space address.
97 * Returns 1 if the range is valid, 0 otherwise.
98 *
99 * This is equivalent to the following test:
100 * (u65)addr + (u65)size <= (u65)current->addr_limit + 1
101 */
__range_ok(unsigned long addr,unsigned long size)102 static inline unsigned long __range_ok(unsigned long addr, unsigned long size)
103 {
104 unsigned long limit = current_thread_info()->addr_limit;
105
106 __chk_user_ptr(addr);
107 asm volatile(
108 // A + B <= C + 1 for all A,B,C, in four easy steps:
109 // 1: X = A + B; X' = X % 2^64
110 " adds %0, %0, %2\n"
111 // 2: Set C = 0 if X > 2^64, to guarantee X' > C in step 4
112 " csel %1, xzr, %1, hi\n"
113 // 3: Set X' = ~0 if X >= 2^64. For X == 2^64, this decrements X'
114 // to compensate for the carry flag being set in step 4. For
115 // X > 2^64, X' merely has to remain nonzero, which it does.
116 " csinv %0, %0, xzr, cc\n"
117 // 4: For X < 2^64, this gives us X' - C - 1 <= 0, where the -1
118 // comes from the carry in being clear. Otherwise, we are
119 // testing X' - C == 0, subject to the previous adjustments.
120 " sbcs xzr, %0, %1\n"
121 " cset %0, ls\n"
122 : "+r" (addr), "+r" (limit) : "Ir" (size) : "cc");
123
124 return addr;
125 }
126
127 /*
128 * When dealing with data aborts, watchpoints, or instruction traps we may end
129 * up with a tagged userland pointer. Clear the tag to get a sane pointer to
130 * pass on to access_ok(), for instance.
131 */
132 #define untagged_addr(addr) sign_extend64(addr, 55)
133
134 #define access_ok(type, addr, size) __range_ok((unsigned long)(addr), size)
135 #define user_addr_max get_fs
136
137 #define _ASM_EXTABLE(from, to) \
138 " .pushsection __ex_table, \"a\"\n" \
139 " .align 3\n" \
140 " .long (" #from " - .), (" #to " - .)\n" \
141 " .popsection\n"
142
143 /*
144 * User access enabling/disabling.
145 */
146 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
__uaccess_ttbr0_disable(void)147 static inline void __uaccess_ttbr0_disable(void)
148 {
149 unsigned long flags, ttbr;
150
151 local_irq_save(flags);
152 ttbr = read_sysreg(ttbr1_el1);
153 ttbr &= ~TTBR_ASID_MASK;
154 /* reserved_ttbr0 placed at the end of swapper_pg_dir */
155 write_sysreg(ttbr + SWAPPER_DIR_SIZE, ttbr0_el1);
156 isb();
157 /* Set reserved ASID */
158 write_sysreg(ttbr, ttbr1_el1);
159 isb();
160 local_irq_restore(flags);
161 }
162
__uaccess_ttbr0_enable(void)163 static inline void __uaccess_ttbr0_enable(void)
164 {
165 unsigned long flags, ttbr0, ttbr1;
166
167 /*
168 * Disable interrupts to avoid preemption between reading the 'ttbr0'
169 * variable and the MSR. A context switch could trigger an ASID
170 * roll-over and an update of 'ttbr0'.
171 */
172 local_irq_save(flags);
173 ttbr0 = READ_ONCE(current_thread_info()->ttbr0);
174
175 /* Restore active ASID */
176 ttbr1 = read_sysreg(ttbr1_el1);
177 ttbr1 &= ~TTBR_ASID_MASK; /* safety measure */
178 ttbr1 |= ttbr0 & TTBR_ASID_MASK;
179 write_sysreg(ttbr1, ttbr1_el1);
180 isb();
181
182 /* Restore user page table */
183 write_sysreg(ttbr0, ttbr0_el1);
184 isb();
185 local_irq_restore(flags);
186 }
187
uaccess_ttbr0_disable(void)188 static inline bool uaccess_ttbr0_disable(void)
189 {
190 if (!system_uses_ttbr0_pan())
191 return false;
192 __uaccess_ttbr0_disable();
193 return true;
194 }
195
uaccess_ttbr0_enable(void)196 static inline bool uaccess_ttbr0_enable(void)
197 {
198 if (!system_uses_ttbr0_pan())
199 return false;
200 __uaccess_ttbr0_enable();
201 return true;
202 }
203 #else
uaccess_ttbr0_disable(void)204 static inline bool uaccess_ttbr0_disable(void)
205 {
206 return false;
207 }
208
uaccess_ttbr0_enable(void)209 static inline bool uaccess_ttbr0_enable(void)
210 {
211 return false;
212 }
213 #endif
214
215 #define __uaccess_disable(alt) \
216 do { \
217 if (!uaccess_ttbr0_disable()) \
218 asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), alt, \
219 CONFIG_ARM64_PAN)); \
220 } while (0)
221
222 #define __uaccess_enable(alt) \
223 do { \
224 if (!uaccess_ttbr0_enable()) \
225 asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), alt, \
226 CONFIG_ARM64_PAN)); \
227 } while (0)
228
uaccess_disable(void)229 static inline void uaccess_disable(void)
230 {
231 __uaccess_disable(ARM64_HAS_PAN);
232 }
233
uaccess_enable(void)234 static inline void uaccess_enable(void)
235 {
236 __uaccess_enable(ARM64_HAS_PAN);
237 }
238
239 /*
240 * These functions are no-ops when UAO is present.
241 */
uaccess_disable_not_uao(void)242 static inline void uaccess_disable_not_uao(void)
243 {
244 __uaccess_disable(ARM64_ALT_PAN_NOT_UAO);
245 }
246
uaccess_enable_not_uao(void)247 static inline void uaccess_enable_not_uao(void)
248 {
249 __uaccess_enable(ARM64_ALT_PAN_NOT_UAO);
250 }
251
252 /*
253 * Sanitise a uaccess pointer such that it becomes NULL if above the
254 * current addr_limit.
255 */
256 #define uaccess_mask_ptr(ptr) (__typeof__(ptr))__uaccess_mask_ptr(ptr)
__uaccess_mask_ptr(const void __user * ptr)257 static inline void __user *__uaccess_mask_ptr(const void __user *ptr)
258 {
259 void __user *safe_ptr;
260
261 asm volatile(
262 " bics xzr, %1, %2\n"
263 " csel %0, %1, xzr, eq\n"
264 : "=&r" (safe_ptr)
265 : "r" (ptr), "r" (current_thread_info()->addr_limit)
266 : "cc");
267
268 csdb();
269 return safe_ptr;
270 }
271
272 /*
273 * The "__xxx" versions of the user access functions do not verify the address
274 * space - it must have been done previously with a separate "access_ok()"
275 * call.
276 *
277 * The "__xxx_error" versions set the third argument to -EFAULT if an error
278 * occurs, and leave it unchanged on success.
279 */
280 #define __get_user_asm(instr, alt_instr, reg, x, addr, err, feature) \
281 asm volatile( \
282 "1:"ALTERNATIVE(instr " " reg "1, [%2]\n", \
283 alt_instr " " reg "1, [%2]\n", feature) \
284 "2:\n" \
285 " .section .fixup, \"ax\"\n" \
286 " .align 2\n" \
287 "3: mov %w0, %3\n" \
288 " mov %1, #0\n" \
289 " b 2b\n" \
290 " .previous\n" \
291 _ASM_EXTABLE(1b, 3b) \
292 : "+r" (err), "=&r" (x) \
293 : "r" (addr), "i" (-EFAULT))
294
295 #define __get_user_err(x, ptr, err) \
296 do { \
297 unsigned long __gu_val; \
298 __chk_user_ptr(ptr); \
299 uaccess_enable_not_uao(); \
300 switch (sizeof(*(ptr))) { \
301 case 1: \
302 __get_user_asm("ldrb", "ldtrb", "%w", __gu_val, (ptr), \
303 (err), ARM64_HAS_UAO); \
304 break; \
305 case 2: \
306 __get_user_asm("ldrh", "ldtrh", "%w", __gu_val, (ptr), \
307 (err), ARM64_HAS_UAO); \
308 break; \
309 case 4: \
310 __get_user_asm("ldr", "ldtr", "%w", __gu_val, (ptr), \
311 (err), ARM64_HAS_UAO); \
312 break; \
313 case 8: \
314 __get_user_asm("ldr", "ldtr", "%", __gu_val, (ptr), \
315 (err), ARM64_HAS_UAO); \
316 break; \
317 default: \
318 BUILD_BUG(); \
319 } \
320 uaccess_disable_not_uao(); \
321 (x) = (__force __typeof__(*(ptr)))__gu_val; \
322 } while (0)
323
324 #define __get_user_check(x, ptr, err) \
325 ({ \
326 __typeof__(*(ptr)) __user *__p = (ptr); \
327 might_fault(); \
328 if (access_ok(VERIFY_READ, __p, sizeof(*__p))) { \
329 __p = uaccess_mask_ptr(__p); \
330 __get_user_err((x), __p, (err)); \
331 } else { \
332 (x) = 0; (err) = -EFAULT; \
333 } \
334 })
335
336 #define __get_user_error(x, ptr, err) \
337 ({ \
338 __get_user_check((x), (ptr), (err)); \
339 (void)0; \
340 })
341
342 #define __get_user(x, ptr) \
343 ({ \
344 int __gu_err = 0; \
345 __get_user_check((x), (ptr), __gu_err); \
346 __gu_err; \
347 })
348
349 #define __get_user_unaligned __get_user
350
351 #define get_user __get_user
352
353 #define __put_user_asm(instr, alt_instr, reg, x, addr, err, feature) \
354 asm volatile( \
355 "1:"ALTERNATIVE(instr " " reg "1, [%2]\n", \
356 alt_instr " " reg "1, [%2]\n", feature) \
357 "2:\n" \
358 " .section .fixup,\"ax\"\n" \
359 " .align 2\n" \
360 "3: mov %w0, %3\n" \
361 " b 2b\n" \
362 " .previous\n" \
363 _ASM_EXTABLE(1b, 3b) \
364 : "+r" (err) \
365 : "r" (x), "r" (addr), "i" (-EFAULT))
366
367 #define __put_user_err(x, ptr, err) \
368 do { \
369 __typeof__(*(ptr)) __pu_val = (x); \
370 __chk_user_ptr(ptr); \
371 uaccess_enable_not_uao(); \
372 switch (sizeof(*(ptr))) { \
373 case 1: \
374 __put_user_asm("strb", "sttrb", "%w", __pu_val, (ptr), \
375 (err), ARM64_HAS_UAO); \
376 break; \
377 case 2: \
378 __put_user_asm("strh", "sttrh", "%w", __pu_val, (ptr), \
379 (err), ARM64_HAS_UAO); \
380 break; \
381 case 4: \
382 __put_user_asm("str", "sttr", "%w", __pu_val, (ptr), \
383 (err), ARM64_HAS_UAO); \
384 break; \
385 case 8: \
386 __put_user_asm("str", "sttr", "%", __pu_val, (ptr), \
387 (err), ARM64_HAS_UAO); \
388 break; \
389 default: \
390 BUILD_BUG(); \
391 } \
392 uaccess_disable_not_uao(); \
393 } while (0)
394
395 #define __put_user_check(x, ptr, err) \
396 ({ \
397 __typeof__(*(ptr)) __user *__p = (ptr); \
398 might_fault(); \
399 if (access_ok(VERIFY_WRITE, __p, sizeof(*__p))) { \
400 __p = uaccess_mask_ptr(__p); \
401 __put_user_err((x), __p, (err)); \
402 } else { \
403 (err) = -EFAULT; \
404 } \
405 })
406
407 #define __put_user_error(x, ptr, err) \
408 ({ \
409 __put_user_check((x), (ptr), (err)); \
410 (void)0; \
411 })
412
413 #define __put_user(x, ptr) \
414 ({ \
415 int __pu_err = 0; \
416 __put_user_check((x), (ptr), __pu_err); \
417 __pu_err; \
418 })
419
420 #define __put_user_unaligned __put_user
421
422 #define put_user __put_user
423
424 extern unsigned long __must_check __arch_copy_from_user(void *to, const void __user *from, unsigned long n);
425 extern unsigned long __must_check __arch_copy_to_user(void __user *to, const void *from, unsigned long n);
426 extern unsigned long __must_check __arch_copy_in_user(void __user *to, const void __user *from, unsigned long n);
427
__copy_from_user(void * to,const void __user * from,unsigned long n)428 static inline unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n)
429 {
430 kasan_check_write(to, n);
431 check_object_size(to, n, false);
432 return __arch_copy_from_user(to, __uaccess_mask_ptr(from), n);
433 }
434
__copy_to_user(void __user * to,const void * from,unsigned long n)435 static inline unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n)
436 {
437 kasan_check_read(from, n);
438 check_object_size(from, n, true);
439 return __arch_copy_to_user(__uaccess_mask_ptr(to), from, n);
440 }
441
copy_from_user(void * to,const void __user * from,unsigned long n)442 static inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n)
443 {
444 unsigned long res = n;
445 kasan_check_write(to, n);
446
447 if (access_ok(VERIFY_READ, from, n)) {
448 check_object_size(to, n, false);
449 res = __arch_copy_from_user(to, from, n);
450 }
451 if (unlikely(res))
452 memset(to + (n - res), 0, res);
453 return res;
454 }
455
copy_to_user(void __user * to,const void * from,unsigned long n)456 static inline unsigned long __must_check copy_to_user(void __user *to, const void *from, unsigned long n)
457 {
458 kasan_check_read(from, n);
459
460 if (access_ok(VERIFY_WRITE, to, n)) {
461 check_object_size(from, n, true);
462 n = __arch_copy_to_user(to, from, n);
463 }
464 return n;
465 }
466
__copy_in_user(void __user * to,const void __user * from,unsigned long n)467 static inline unsigned long __must_check __copy_in_user(void __user *to, const void __user *from, unsigned long n)
468 {
469 if (access_ok(VERIFY_READ, from, n) && access_ok(VERIFY_WRITE, to, n))
470 n = __arch_copy_in_user(__uaccess_mask_ptr(to), __uaccess_mask_ptr(from), n);
471 return n;
472 }
473 #define copy_in_user __copy_in_user
474
475 #define __copy_to_user_inatomic __copy_to_user
476 #define __copy_from_user_inatomic __copy_from_user
477
478 extern unsigned long __must_check __arch_clear_user(void __user *to, unsigned long n);
__clear_user(void __user * to,unsigned long n)479 static inline unsigned long __must_check __clear_user(void __user *to, unsigned long n)
480 {
481 if (access_ok(VERIFY_WRITE, to, n))
482 n = __arch_clear_user(__uaccess_mask_ptr(to), n);
483 return n;
484 }
485 #define clear_user __clear_user
486
487 extern long strncpy_from_user(char *dest, const char __user *src, long count);
488
489 extern __must_check long strlen_user(const char __user *str);
490 extern __must_check long strnlen_user(const char __user *str, long n);
491
492 #else /* __ASSEMBLY__ */
493
494 #include <asm/assembler.h>
495
496 /*
497 * User access enabling/disabling macros.
498 */
499 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
500 .macro __uaccess_ttbr0_disable, tmp1
501 mrs \tmp1, ttbr1_el1 // swapper_pg_dir
502 bic \tmp1, \tmp1, #TTBR_ASID_MASK
503 add \tmp1, \tmp1, #SWAPPER_DIR_SIZE // reserved_ttbr0 at the end of swapper_pg_dir
504 msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1
505 isb
506 sub \tmp1, \tmp1, #SWAPPER_DIR_SIZE
507 msr ttbr1_el1, \tmp1 // set reserved ASID
508 isb
509 .endm
510
511 .macro __uaccess_ttbr0_enable, tmp1, tmp2
512 get_thread_info \tmp1
513 ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1
514 mrs \tmp2, ttbr1_el1
515 extr \tmp2, \tmp2, \tmp1, #48
516 ror \tmp2, \tmp2, #16
517 msr ttbr1_el1, \tmp2 // set the active ASID
518 isb
519 msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1
520 isb
521 .endm
522
523 .macro uaccess_ttbr0_disable, tmp1, tmp2
524 alternative_if_not ARM64_HAS_PAN
525 save_and_disable_irq \tmp2 // avoid preemption
526 __uaccess_ttbr0_disable \tmp1
527 restore_irq \tmp2
528 alternative_else_nop_endif
529 .endm
530
531 .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3
532 alternative_if_not ARM64_HAS_PAN
533 save_and_disable_irq \tmp3 // avoid preemption
534 __uaccess_ttbr0_enable \tmp1, \tmp2
535 restore_irq \tmp3
536 alternative_else_nop_endif
537 .endm
538 #else
539 .macro uaccess_ttbr0_disable, tmp1, tmp2
540 .endm
541
542 .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3
543 .endm
544 #endif
545
546 /*
547 * These macros are no-ops when UAO is present.
548 */
549 .macro uaccess_disable_not_uao, tmp1, tmp2
550 uaccess_ttbr0_disable \tmp1, \tmp2
551 alternative_if ARM64_ALT_PAN_NOT_UAO
552 SET_PSTATE_PAN(1)
553 alternative_else_nop_endif
554 .endm
555
556 .macro uaccess_enable_not_uao, tmp1, tmp2, tmp3
557 uaccess_ttbr0_enable \tmp1, \tmp2, \tmp3
558 alternative_if ARM64_ALT_PAN_NOT_UAO
559 SET_PSTATE_PAN(0)
560 alternative_else_nop_endif
561 .endm
562
563 #endif /* __ASSEMBLY__ */
564
565 #endif /* __ASM_UACCESS_H */
566