1 /*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/platform_data/dma-dw.h>
11 #include <linux/fb.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/slab.h>
16 #include <linux/gpio.h>
17 #include <linux/spi/spi.h>
18 #include <linux/usb/atmel_usba_udc.h>
19
20 #include <linux/atmel-mci.h>
21
22 #include <asm/io.h>
23 #include <asm/irq.h>
24
25 #include <mach/at32ap700x.h>
26 #include <mach/board.h>
27 #include <mach/hmatrix.h>
28 #include <mach/portmux.h>
29 #include <mach/sram.h>
30
31 #include <sound/atmel-abdac.h>
32 #include <sound/atmel-ac97c.h>
33
34 #include <video/atmel_lcdc.h>
35
36 #include "clock.h"
37 #include "pio.h"
38 #include "pm.h"
39
40
41 #define PBMEM(base) \
42 { \
43 .start = base, \
44 .end = base + 0x3ff, \
45 .flags = IORESOURCE_MEM, \
46 }
47 #define IRQ(num) \
48 { \
49 .start = num, \
50 .end = num, \
51 .flags = IORESOURCE_IRQ, \
52 }
53 #define NAMED_IRQ(num, _name) \
54 { \
55 .start = num, \
56 .end = num, \
57 .name = _name, \
58 .flags = IORESOURCE_IRQ, \
59 }
60
61 /* REVISIT these assume *every* device supports DMA, but several
62 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
63 */
64 #define DEFINE_DEV(_name, _id) \
65 static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \
66 static struct platform_device _name##_id##_device = { \
67 .name = #_name, \
68 .id = _id, \
69 .dev = { \
70 .dma_mask = &_name##_id##_dma_mask, \
71 .coherent_dma_mask = DMA_BIT_MASK(32), \
72 }, \
73 .resource = _name##_id##_resource, \
74 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
75 }
76 #define DEFINE_DEV_DATA(_name, _id) \
77 static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \
78 static struct platform_device _name##_id##_device = { \
79 .name = #_name, \
80 .id = _id, \
81 .dev = { \
82 .dma_mask = &_name##_id##_dma_mask, \
83 .platform_data = &_name##_id##_data, \
84 .coherent_dma_mask = DMA_BIT_MASK(32), \
85 }, \
86 .resource = _name##_id##_resource, \
87 .num_resources = ARRAY_SIZE(_name##_id##_resource), \
88 }
89
90 #define select_peripheral(port, pin_mask, periph, flags) \
91 at32_select_periph(GPIO_##port##_BASE, pin_mask, \
92 GPIO_##periph, flags)
93
94 #define DEV_CLK(_name, devname, bus, _index) \
95 static struct clk devname##_##_name = { \
96 .name = #_name, \
97 .dev = &devname##_device.dev, \
98 .parent = &bus##_clk, \
99 .mode = bus##_clk_mode, \
100 .get_rate = bus##_clk_get_rate, \
101 .index = _index, \
102 }
103
104 static DEFINE_SPINLOCK(pm_lock);
105
106 static struct clk osc0;
107 static struct clk osc1;
108
osc_get_rate(struct clk * clk)109 static unsigned long osc_get_rate(struct clk *clk)
110 {
111 return at32_board_osc_rates[clk->index];
112 }
113
pll_get_rate(struct clk * clk,unsigned long control)114 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
115 {
116 unsigned long div, mul, rate;
117
118 div = PM_BFEXT(PLLDIV, control) + 1;
119 mul = PM_BFEXT(PLLMUL, control) + 1;
120
121 rate = clk->parent->get_rate(clk->parent);
122 rate = (rate + div / 2) / div;
123 rate *= mul;
124
125 return rate;
126 }
127
pll_set_rate(struct clk * clk,unsigned long rate,u32 * pll_ctrl)128 static long pll_set_rate(struct clk *clk, unsigned long rate,
129 u32 *pll_ctrl)
130 {
131 unsigned long mul;
132 unsigned long mul_best_fit = 0;
133 unsigned long div;
134 unsigned long div_min;
135 unsigned long div_max;
136 unsigned long div_best_fit = 0;
137 unsigned long base;
138 unsigned long pll_in;
139 unsigned long actual = 0;
140 unsigned long rate_error;
141 unsigned long rate_error_prev = ~0UL;
142 u32 ctrl;
143
144 /* Rate must be between 80 MHz and 200 Mhz. */
145 if (rate < 80000000UL || rate > 200000000UL)
146 return -EINVAL;
147
148 ctrl = PM_BF(PLLOPT, 4);
149 base = clk->parent->get_rate(clk->parent);
150
151 /* PLL input frequency must be between 6 MHz and 32 MHz. */
152 div_min = DIV_ROUND_UP(base, 32000000UL);
153 div_max = base / 6000000UL;
154
155 if (div_max < div_min)
156 return -EINVAL;
157
158 for (div = div_min; div <= div_max; div++) {
159 pll_in = (base + div / 2) / div;
160 mul = (rate + pll_in / 2) / pll_in;
161
162 if (mul == 0)
163 continue;
164
165 actual = pll_in * mul;
166 rate_error = abs(actual - rate);
167
168 if (rate_error < rate_error_prev) {
169 mul_best_fit = mul;
170 div_best_fit = div;
171 rate_error_prev = rate_error;
172 }
173
174 if (rate_error == 0)
175 break;
176 }
177
178 if (div_best_fit == 0)
179 return -EINVAL;
180
181 ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
182 ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
183 ctrl |= PM_BF(PLLCOUNT, 16);
184
185 if (clk->parent == &osc1)
186 ctrl |= PM_BIT(PLLOSC);
187
188 *pll_ctrl = ctrl;
189
190 return actual;
191 }
192
pll0_get_rate(struct clk * clk)193 static unsigned long pll0_get_rate(struct clk *clk)
194 {
195 u32 control;
196
197 control = pm_readl(PLL0);
198
199 return pll_get_rate(clk, control);
200 }
201
pll1_mode(struct clk * clk,int enabled)202 static void pll1_mode(struct clk *clk, int enabled)
203 {
204 unsigned long timeout;
205 u32 status;
206 u32 ctrl;
207
208 ctrl = pm_readl(PLL1);
209
210 if (enabled) {
211 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
212 pr_debug("clk %s: failed to enable, rate not set\n",
213 clk->name);
214 return;
215 }
216
217 ctrl |= PM_BIT(PLLEN);
218 pm_writel(PLL1, ctrl);
219
220 /* Wait for PLL lock. */
221 for (timeout = 10000; timeout; timeout--) {
222 status = pm_readl(ISR);
223 if (status & PM_BIT(LOCK1))
224 break;
225 udelay(10);
226 }
227
228 if (!(status & PM_BIT(LOCK1)))
229 printk(KERN_ERR "clk %s: timeout waiting for lock\n",
230 clk->name);
231 } else {
232 ctrl &= ~PM_BIT(PLLEN);
233 pm_writel(PLL1, ctrl);
234 }
235 }
236
pll1_get_rate(struct clk * clk)237 static unsigned long pll1_get_rate(struct clk *clk)
238 {
239 u32 control;
240
241 control = pm_readl(PLL1);
242
243 return pll_get_rate(clk, control);
244 }
245
pll1_set_rate(struct clk * clk,unsigned long rate,int apply)246 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
247 {
248 u32 ctrl = 0;
249 unsigned long actual_rate;
250
251 actual_rate = pll_set_rate(clk, rate, &ctrl);
252
253 if (apply) {
254 if (actual_rate != rate)
255 return -EINVAL;
256 if (clk->users > 0)
257 return -EBUSY;
258 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
259 clk->name, rate, actual_rate);
260 pm_writel(PLL1, ctrl);
261 }
262
263 return actual_rate;
264 }
265
pll1_set_parent(struct clk * clk,struct clk * parent)266 static int pll1_set_parent(struct clk *clk, struct clk *parent)
267 {
268 u32 ctrl;
269
270 if (clk->users > 0)
271 return -EBUSY;
272
273 ctrl = pm_readl(PLL1);
274 WARN_ON(ctrl & PM_BIT(PLLEN));
275
276 if (parent == &osc0)
277 ctrl &= ~PM_BIT(PLLOSC);
278 else if (parent == &osc1)
279 ctrl |= PM_BIT(PLLOSC);
280 else
281 return -EINVAL;
282
283 pm_writel(PLL1, ctrl);
284 clk->parent = parent;
285
286 return 0;
287 }
288
289 /*
290 * The AT32AP7000 has five primary clock sources: One 32kHz
291 * oscillator, two crystal oscillators and two PLLs.
292 */
293 static struct clk osc32k = {
294 .name = "osc32k",
295 .get_rate = osc_get_rate,
296 .users = 1,
297 .index = 0,
298 };
299 static struct clk osc0 = {
300 .name = "osc0",
301 .get_rate = osc_get_rate,
302 .users = 1,
303 .index = 1,
304 };
305 static struct clk osc1 = {
306 .name = "osc1",
307 .get_rate = osc_get_rate,
308 .index = 2,
309 };
310 static struct clk pll0 = {
311 .name = "pll0",
312 .get_rate = pll0_get_rate,
313 .parent = &osc0,
314 };
315 static struct clk pll1 = {
316 .name = "pll1",
317 .mode = pll1_mode,
318 .get_rate = pll1_get_rate,
319 .set_rate = pll1_set_rate,
320 .set_parent = pll1_set_parent,
321 .parent = &osc0,
322 };
323
324 /*
325 * The main clock can be either osc0 or pll0. The boot loader may
326 * have chosen one for us, so we don't really know which one until we
327 * have a look at the SM.
328 */
329 static struct clk *main_clock;
330
331 /*
332 * Synchronous clocks are generated from the main clock. The clocks
333 * must satisfy the constraint
334 * fCPU >= fHSB >= fPB
335 * i.e. each clock must not be faster than its parent.
336 */
bus_clk_get_rate(struct clk * clk,unsigned int shift)337 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
338 {
339 return main_clock->get_rate(main_clock) >> shift;
340 };
341
cpu_clk_mode(struct clk * clk,int enabled)342 static void cpu_clk_mode(struct clk *clk, int enabled)
343 {
344 unsigned long flags;
345 u32 mask;
346
347 spin_lock_irqsave(&pm_lock, flags);
348 mask = pm_readl(CPU_MASK);
349 if (enabled)
350 mask |= 1 << clk->index;
351 else
352 mask &= ~(1 << clk->index);
353 pm_writel(CPU_MASK, mask);
354 spin_unlock_irqrestore(&pm_lock, flags);
355 }
356
cpu_clk_get_rate(struct clk * clk)357 static unsigned long cpu_clk_get_rate(struct clk *clk)
358 {
359 unsigned long cksel, shift = 0;
360
361 cksel = pm_readl(CKSEL);
362 if (cksel & PM_BIT(CPUDIV))
363 shift = PM_BFEXT(CPUSEL, cksel) + 1;
364
365 return bus_clk_get_rate(clk, shift);
366 }
367
cpu_clk_set_rate(struct clk * clk,unsigned long rate,int apply)368 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
369 {
370 u32 control;
371 unsigned long parent_rate, child_div, actual_rate, div;
372
373 parent_rate = clk->parent->get_rate(clk->parent);
374 control = pm_readl(CKSEL);
375
376 if (control & PM_BIT(HSBDIV))
377 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
378 else
379 child_div = 1;
380
381 if (rate > 3 * (parent_rate / 4) || child_div == 1) {
382 actual_rate = parent_rate;
383 control &= ~PM_BIT(CPUDIV);
384 } else {
385 unsigned int cpusel;
386 div = (parent_rate + rate / 2) / rate;
387 if (div > child_div)
388 div = child_div;
389 cpusel = (div > 1) ? (fls(div) - 2) : 0;
390 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
391 actual_rate = parent_rate / (1 << (cpusel + 1));
392 }
393
394 pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
395 clk->name, rate, actual_rate);
396
397 if (apply)
398 pm_writel(CKSEL, control);
399
400 return actual_rate;
401 }
402
hsb_clk_mode(struct clk * clk,int enabled)403 static void hsb_clk_mode(struct clk *clk, int enabled)
404 {
405 unsigned long flags;
406 u32 mask;
407
408 spin_lock_irqsave(&pm_lock, flags);
409 mask = pm_readl(HSB_MASK);
410 if (enabled)
411 mask |= 1 << clk->index;
412 else
413 mask &= ~(1 << clk->index);
414 pm_writel(HSB_MASK, mask);
415 spin_unlock_irqrestore(&pm_lock, flags);
416 }
417
hsb_clk_get_rate(struct clk * clk)418 static unsigned long hsb_clk_get_rate(struct clk *clk)
419 {
420 unsigned long cksel, shift = 0;
421
422 cksel = pm_readl(CKSEL);
423 if (cksel & PM_BIT(HSBDIV))
424 shift = PM_BFEXT(HSBSEL, cksel) + 1;
425
426 return bus_clk_get_rate(clk, shift);
427 }
428
pba_clk_mode(struct clk * clk,int enabled)429 void pba_clk_mode(struct clk *clk, int enabled)
430 {
431 unsigned long flags;
432 u32 mask;
433
434 spin_lock_irqsave(&pm_lock, flags);
435 mask = pm_readl(PBA_MASK);
436 if (enabled)
437 mask |= 1 << clk->index;
438 else
439 mask &= ~(1 << clk->index);
440 pm_writel(PBA_MASK, mask);
441 spin_unlock_irqrestore(&pm_lock, flags);
442 }
443
pba_clk_get_rate(struct clk * clk)444 unsigned long pba_clk_get_rate(struct clk *clk)
445 {
446 unsigned long cksel, shift = 0;
447
448 cksel = pm_readl(CKSEL);
449 if (cksel & PM_BIT(PBADIV))
450 shift = PM_BFEXT(PBASEL, cksel) + 1;
451
452 return bus_clk_get_rate(clk, shift);
453 }
454
pbb_clk_mode(struct clk * clk,int enabled)455 static void pbb_clk_mode(struct clk *clk, int enabled)
456 {
457 unsigned long flags;
458 u32 mask;
459
460 spin_lock_irqsave(&pm_lock, flags);
461 mask = pm_readl(PBB_MASK);
462 if (enabled)
463 mask |= 1 << clk->index;
464 else
465 mask &= ~(1 << clk->index);
466 pm_writel(PBB_MASK, mask);
467 spin_unlock_irqrestore(&pm_lock, flags);
468 }
469
pbb_clk_get_rate(struct clk * clk)470 static unsigned long pbb_clk_get_rate(struct clk *clk)
471 {
472 unsigned long cksel, shift = 0;
473
474 cksel = pm_readl(CKSEL);
475 if (cksel & PM_BIT(PBBDIV))
476 shift = PM_BFEXT(PBBSEL, cksel) + 1;
477
478 return bus_clk_get_rate(clk, shift);
479 }
480
481 static struct clk cpu_clk = {
482 .name = "cpu",
483 .get_rate = cpu_clk_get_rate,
484 .set_rate = cpu_clk_set_rate,
485 .users = 1,
486 };
487 static struct clk hsb_clk = {
488 .name = "hsb",
489 .parent = &cpu_clk,
490 .get_rate = hsb_clk_get_rate,
491 };
492 static struct clk pba_clk = {
493 .name = "pba",
494 .parent = &hsb_clk,
495 .mode = hsb_clk_mode,
496 .get_rate = pba_clk_get_rate,
497 .index = 1,
498 };
499 static struct clk pbb_clk = {
500 .name = "pbb",
501 .parent = &hsb_clk,
502 .mode = hsb_clk_mode,
503 .get_rate = pbb_clk_get_rate,
504 .users = 1,
505 .index = 2,
506 };
507
508 /* --------------------------------------------------------------------
509 * Generic Clock operations
510 * -------------------------------------------------------------------- */
511
genclk_mode(struct clk * clk,int enabled)512 static void genclk_mode(struct clk *clk, int enabled)
513 {
514 u32 control;
515
516 control = pm_readl(GCCTRL(clk->index));
517 if (enabled)
518 control |= PM_BIT(CEN);
519 else
520 control &= ~PM_BIT(CEN);
521 pm_writel(GCCTRL(clk->index), control);
522 }
523
genclk_get_rate(struct clk * clk)524 static unsigned long genclk_get_rate(struct clk *clk)
525 {
526 u32 control;
527 unsigned long div = 1;
528
529 control = pm_readl(GCCTRL(clk->index));
530 if (control & PM_BIT(DIVEN))
531 div = 2 * (PM_BFEXT(DIV, control) + 1);
532
533 return clk->parent->get_rate(clk->parent) / div;
534 }
535
genclk_set_rate(struct clk * clk,unsigned long rate,int apply)536 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
537 {
538 u32 control;
539 unsigned long parent_rate, actual_rate, div;
540
541 parent_rate = clk->parent->get_rate(clk->parent);
542 control = pm_readl(GCCTRL(clk->index));
543
544 if (rate > 3 * parent_rate / 4) {
545 actual_rate = parent_rate;
546 control &= ~PM_BIT(DIVEN);
547 } else {
548 div = (parent_rate + rate) / (2 * rate) - 1;
549 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
550 actual_rate = parent_rate / (2 * (div + 1));
551 }
552
553 dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
554 clk->name, rate, actual_rate);
555
556 if (apply)
557 pm_writel(GCCTRL(clk->index), control);
558
559 return actual_rate;
560 }
561
genclk_set_parent(struct clk * clk,struct clk * parent)562 int genclk_set_parent(struct clk *clk, struct clk *parent)
563 {
564 u32 control;
565
566 dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
567 clk->name, parent->name, clk->parent->name);
568
569 control = pm_readl(GCCTRL(clk->index));
570
571 if (parent == &osc1 || parent == &pll1)
572 control |= PM_BIT(OSCSEL);
573 else if (parent == &osc0 || parent == &pll0)
574 control &= ~PM_BIT(OSCSEL);
575 else
576 return -EINVAL;
577
578 if (parent == &pll0 || parent == &pll1)
579 control |= PM_BIT(PLLSEL);
580 else
581 control &= ~PM_BIT(PLLSEL);
582
583 pm_writel(GCCTRL(clk->index), control);
584 clk->parent = parent;
585
586 return 0;
587 }
588
genclk_init_parent(struct clk * clk)589 static void __init genclk_init_parent(struct clk *clk)
590 {
591 u32 control;
592 struct clk *parent;
593
594 BUG_ON(clk->index > 7);
595
596 control = pm_readl(GCCTRL(clk->index));
597 if (control & PM_BIT(OSCSEL))
598 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
599 else
600 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
601
602 clk->parent = parent;
603 }
604
605 static struct resource dw_dmac0_resource[] = {
606 PBMEM(0xff200000),
607 IRQ(2),
608 };
609 DEFINE_DEV(dw_dmac, 0);
610 DEV_CLK(hclk, dw_dmac0, hsb, 10);
611
612 /* --------------------------------------------------------------------
613 * System peripherals
614 * -------------------------------------------------------------------- */
615 static struct resource at32_pm0_resource[] = {
616 {
617 .start = 0xfff00000,
618 .end = 0xfff0007f,
619 .flags = IORESOURCE_MEM,
620 },
621 IRQ(20),
622 };
623
624 static struct resource at32ap700x_rtc0_resource[] = {
625 {
626 .start = 0xfff00080,
627 .end = 0xfff000af,
628 .flags = IORESOURCE_MEM,
629 },
630 IRQ(21),
631 };
632
633 static struct resource at32_wdt0_resource[] = {
634 {
635 .start = 0xfff000b0,
636 .end = 0xfff000cf,
637 .flags = IORESOURCE_MEM,
638 },
639 };
640
641 static struct resource at32_eic0_resource[] = {
642 {
643 .start = 0xfff00100,
644 .end = 0xfff0013f,
645 .flags = IORESOURCE_MEM,
646 },
647 IRQ(19),
648 };
649
650 DEFINE_DEV(at32_pm, 0);
651 DEFINE_DEV(at32ap700x_rtc, 0);
652 DEFINE_DEV(at32_wdt, 0);
653 DEFINE_DEV(at32_eic, 0);
654
655 /*
656 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
657 * is always running.
658 */
659 static struct clk at32_pm_pclk = {
660 .name = "pclk",
661 .dev = &at32_pm0_device.dev,
662 .parent = &pbb_clk,
663 .mode = pbb_clk_mode,
664 .get_rate = pbb_clk_get_rate,
665 .users = 1,
666 .index = 0,
667 };
668
669 static struct resource intc0_resource[] = {
670 PBMEM(0xfff00400),
671 };
672 struct platform_device at32_intc0_device = {
673 .name = "intc",
674 .id = 0,
675 .resource = intc0_resource,
676 .num_resources = ARRAY_SIZE(intc0_resource),
677 };
678 DEV_CLK(pclk, at32_intc0, pbb, 1);
679
680 static struct clk ebi_clk = {
681 .name = "ebi",
682 .parent = &hsb_clk,
683 .mode = hsb_clk_mode,
684 .get_rate = hsb_clk_get_rate,
685 .users = 1,
686 };
687 static struct clk hramc_clk = {
688 .name = "hramc",
689 .parent = &hsb_clk,
690 .mode = hsb_clk_mode,
691 .get_rate = hsb_clk_get_rate,
692 .users = 1,
693 .index = 3,
694 };
695 static struct clk sdramc_clk = {
696 .name = "sdramc_clk",
697 .parent = &pbb_clk,
698 .mode = pbb_clk_mode,
699 .get_rate = pbb_clk_get_rate,
700 .users = 1,
701 .index = 14,
702 };
703
704 static struct resource smc0_resource[] = {
705 PBMEM(0xfff03400),
706 };
707 DEFINE_DEV(smc, 0);
708 DEV_CLK(pclk, smc0, pbb, 13);
709 DEV_CLK(mck, smc0, hsb, 0);
710
711 static struct platform_device pdc_device = {
712 .name = "pdc",
713 .id = 0,
714 };
715 DEV_CLK(hclk, pdc, hsb, 4);
716 DEV_CLK(pclk, pdc, pba, 16);
717
718 static struct clk pico_clk = {
719 .name = "pico",
720 .parent = &cpu_clk,
721 .mode = cpu_clk_mode,
722 .get_rate = cpu_clk_get_rate,
723 .users = 1,
724 };
725
726 /* --------------------------------------------------------------------
727 * HMATRIX
728 * -------------------------------------------------------------------- */
729
730 struct clk at32_hmatrix_clk = {
731 .name = "hmatrix_clk",
732 .parent = &pbb_clk,
733 .mode = pbb_clk_mode,
734 .get_rate = pbb_clk_get_rate,
735 .index = 2,
736 .users = 1,
737 };
738
739 /*
740 * Set bits in the HMATRIX Special Function Register (SFR) used by the
741 * External Bus Interface (EBI). This can be used to enable special
742 * features like CompactFlash support, NAND Flash support, etc. on
743 * certain chipselects.
744 */
set_ebi_sfr_bits(u32 mask)745 static inline void set_ebi_sfr_bits(u32 mask)
746 {
747 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
748 }
749
750 /* --------------------------------------------------------------------
751 * Timer/Counter (TC)
752 * -------------------------------------------------------------------- */
753
754 static struct resource at32_tcb0_resource[] = {
755 PBMEM(0xfff00c00),
756 IRQ(22),
757 };
758 static struct platform_device at32_tcb0_device = {
759 .name = "atmel_tcb",
760 .id = 0,
761 .resource = at32_tcb0_resource,
762 .num_resources = ARRAY_SIZE(at32_tcb0_resource),
763 };
764 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
765
766 static struct resource at32_tcb1_resource[] = {
767 PBMEM(0xfff01000),
768 IRQ(23),
769 };
770 static struct platform_device at32_tcb1_device = {
771 .name = "atmel_tcb",
772 .id = 1,
773 .resource = at32_tcb1_resource,
774 .num_resources = ARRAY_SIZE(at32_tcb1_resource),
775 };
776 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
777
778 /* --------------------------------------------------------------------
779 * PIO
780 * -------------------------------------------------------------------- */
781
782 static struct resource pio0_resource[] = {
783 PBMEM(0xffe02800),
784 IRQ(13),
785 };
786 DEFINE_DEV(pio, 0);
787 DEV_CLK(mck, pio0, pba, 10);
788
789 static struct resource pio1_resource[] = {
790 PBMEM(0xffe02c00),
791 IRQ(14),
792 };
793 DEFINE_DEV(pio, 1);
794 DEV_CLK(mck, pio1, pba, 11);
795
796 static struct resource pio2_resource[] = {
797 PBMEM(0xffe03000),
798 IRQ(15),
799 };
800 DEFINE_DEV(pio, 2);
801 DEV_CLK(mck, pio2, pba, 12);
802
803 static struct resource pio3_resource[] = {
804 PBMEM(0xffe03400),
805 IRQ(16),
806 };
807 DEFINE_DEV(pio, 3);
808 DEV_CLK(mck, pio3, pba, 13);
809
810 static struct resource pio4_resource[] = {
811 PBMEM(0xffe03800),
812 IRQ(17),
813 };
814 DEFINE_DEV(pio, 4);
815 DEV_CLK(mck, pio4, pba, 14);
816
system_device_init(void)817 static int __init system_device_init(void)
818 {
819 platform_device_register(&at32_pm0_device);
820 platform_device_register(&at32_intc0_device);
821 platform_device_register(&at32ap700x_rtc0_device);
822 platform_device_register(&at32_wdt0_device);
823 platform_device_register(&at32_eic0_device);
824 platform_device_register(&smc0_device);
825 platform_device_register(&pdc_device);
826 platform_device_register(&dw_dmac0_device);
827
828 platform_device_register(&at32_tcb0_device);
829 platform_device_register(&at32_tcb1_device);
830
831 platform_device_register(&pio0_device);
832 platform_device_register(&pio1_device);
833 platform_device_register(&pio2_device);
834 platform_device_register(&pio3_device);
835 platform_device_register(&pio4_device);
836
837 return 0;
838 }
839 core_initcall(system_device_init);
840
841 /* --------------------------------------------------------------------
842 * PSIF
843 * -------------------------------------------------------------------- */
844 static struct resource atmel_psif0_resource[] __initdata = {
845 {
846 .start = 0xffe03c00,
847 .end = 0xffe03cff,
848 .flags = IORESOURCE_MEM,
849 },
850 IRQ(18),
851 };
852 static struct clk atmel_psif0_pclk = {
853 .name = "pclk",
854 .parent = &pba_clk,
855 .mode = pba_clk_mode,
856 .get_rate = pba_clk_get_rate,
857 .index = 15,
858 };
859
860 static struct resource atmel_psif1_resource[] __initdata = {
861 {
862 .start = 0xffe03d00,
863 .end = 0xffe03dff,
864 .flags = IORESOURCE_MEM,
865 },
866 IRQ(18),
867 };
868 static struct clk atmel_psif1_pclk = {
869 .name = "pclk",
870 .parent = &pba_clk,
871 .mode = pba_clk_mode,
872 .get_rate = pba_clk_get_rate,
873 .index = 15,
874 };
875
at32_add_device_psif(unsigned int id)876 struct platform_device *__init at32_add_device_psif(unsigned int id)
877 {
878 struct platform_device *pdev;
879 u32 pin_mask;
880
881 if (!(id == 0 || id == 1))
882 return NULL;
883
884 pdev = platform_device_alloc("atmel_psif", id);
885 if (!pdev)
886 return NULL;
887
888 switch (id) {
889 case 0:
890 pin_mask = (1 << 8) | (1 << 9); /* CLOCK & DATA */
891
892 if (platform_device_add_resources(pdev, atmel_psif0_resource,
893 ARRAY_SIZE(atmel_psif0_resource)))
894 goto err_add_resources;
895 atmel_psif0_pclk.dev = &pdev->dev;
896 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
897 break;
898 case 1:
899 pin_mask = (1 << 11) | (1 << 12); /* CLOCK & DATA */
900
901 if (platform_device_add_resources(pdev, atmel_psif1_resource,
902 ARRAY_SIZE(atmel_psif1_resource)))
903 goto err_add_resources;
904 atmel_psif1_pclk.dev = &pdev->dev;
905 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
906 break;
907 default:
908 return NULL;
909 }
910
911 platform_device_add(pdev);
912 return pdev;
913
914 err_add_resources:
915 platform_device_put(pdev);
916 return NULL;
917 }
918
919 /* --------------------------------------------------------------------
920 * USART
921 * -------------------------------------------------------------------- */
922
923 static struct atmel_uart_data atmel_usart0_data = {
924 .use_dma_tx = 1,
925 .use_dma_rx = 1,
926 };
927 static struct resource atmel_usart0_resource[] = {
928 PBMEM(0xffe00c00),
929 IRQ(6),
930 };
931 DEFINE_DEV_DATA(atmel_usart, 0);
932 DEV_CLK(usart, atmel_usart0, pba, 3);
933
934 static struct atmel_uart_data atmel_usart1_data = {
935 .use_dma_tx = 1,
936 .use_dma_rx = 1,
937 };
938 static struct resource atmel_usart1_resource[] = {
939 PBMEM(0xffe01000),
940 IRQ(7),
941 };
942 DEFINE_DEV_DATA(atmel_usart, 1);
943 DEV_CLK(usart, atmel_usart1, pba, 4);
944
945 static struct atmel_uart_data atmel_usart2_data = {
946 .use_dma_tx = 1,
947 .use_dma_rx = 1,
948 };
949 static struct resource atmel_usart2_resource[] = {
950 PBMEM(0xffe01400),
951 IRQ(8),
952 };
953 DEFINE_DEV_DATA(atmel_usart, 2);
954 DEV_CLK(usart, atmel_usart2, pba, 5);
955
956 static struct atmel_uart_data atmel_usart3_data = {
957 .use_dma_tx = 1,
958 .use_dma_rx = 1,
959 };
960 static struct resource atmel_usart3_resource[] = {
961 PBMEM(0xffe01800),
962 IRQ(9),
963 };
964 DEFINE_DEV_DATA(atmel_usart, 3);
965 DEV_CLK(usart, atmel_usart3, pba, 6);
966
configure_usart0_pins(int flags)967 static inline void configure_usart0_pins(int flags)
968 {
969 u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */
970 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 6);
971 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 7);
972 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 10);
973
974 select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
975 }
976
configure_usart1_pins(int flags)977 static inline void configure_usart1_pins(int flags)
978 {
979 u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */
980 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 19);
981 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 20);
982 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 16);
983
984 select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP);
985 }
986
configure_usart2_pins(int flags)987 static inline void configure_usart2_pins(int flags)
988 {
989 u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */
990 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 30);
991 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 29);
992 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 28);
993
994 select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
995 }
996
configure_usart3_pins(int flags)997 static inline void configure_usart3_pins(int flags)
998 {
999 u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */
1000 if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 16);
1001 if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 15);
1002 if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 19);
1003
1004 select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
1005 }
1006
1007 static struct platform_device *__initdata at32_usarts[4];
1008
at32_map_usart(unsigned int hw_id,unsigned int line,int flags)1009 void __init at32_map_usart(unsigned int hw_id, unsigned int line, int flags)
1010 {
1011 struct platform_device *pdev;
1012 struct atmel_uart_data *pdata;
1013
1014 switch (hw_id) {
1015 case 0:
1016 pdev = &atmel_usart0_device;
1017 configure_usart0_pins(flags);
1018 break;
1019 case 1:
1020 pdev = &atmel_usart1_device;
1021 configure_usart1_pins(flags);
1022 break;
1023 case 2:
1024 pdev = &atmel_usart2_device;
1025 configure_usart2_pins(flags);
1026 break;
1027 case 3:
1028 pdev = &atmel_usart3_device;
1029 configure_usart3_pins(flags);
1030 break;
1031 default:
1032 return;
1033 }
1034
1035 if (PXSEG(pdev->resource[0].start) == P4SEG) {
1036 /* Addresses in the P4 segment are permanently mapped 1:1 */
1037 struct atmel_uart_data *data = pdev->dev.platform_data;
1038 data->regs = (void __iomem *)pdev->resource[0].start;
1039 }
1040
1041 pdev->id = line;
1042 pdata = pdev->dev.platform_data;
1043 pdata->num = line;
1044 at32_usarts[line] = pdev;
1045 }
1046
at32_add_device_usart(unsigned int id)1047 struct platform_device *__init at32_add_device_usart(unsigned int id)
1048 {
1049 platform_device_register(at32_usarts[id]);
1050 return at32_usarts[id];
1051 }
1052
at32_setup_serial_console(unsigned int usart_id)1053 void __init at32_setup_serial_console(unsigned int usart_id)
1054 {
1055 #ifdef CONFIG_SERIAL_ATMEL
1056 atmel_default_console_device = at32_usarts[usart_id];
1057 #endif
1058 }
1059
1060 /* --------------------------------------------------------------------
1061 * Ethernet
1062 * -------------------------------------------------------------------- */
1063
1064 #ifdef CONFIG_CPU_AT32AP7000
1065 static struct macb_platform_data macb0_data;
1066 static struct resource macb0_resource[] = {
1067 PBMEM(0xfff01800),
1068 IRQ(25),
1069 };
1070 DEFINE_DEV_DATA(macb, 0);
1071 DEV_CLK(hclk, macb0, hsb, 8);
1072 DEV_CLK(pclk, macb0, pbb, 6);
1073
1074 static struct macb_platform_data macb1_data;
1075 static struct resource macb1_resource[] = {
1076 PBMEM(0xfff01c00),
1077 IRQ(26),
1078 };
1079 DEFINE_DEV_DATA(macb, 1);
1080 DEV_CLK(hclk, macb1, hsb, 9);
1081 DEV_CLK(pclk, macb1, pbb, 7);
1082
1083 struct platform_device *__init
at32_add_device_eth(unsigned int id,struct macb_platform_data * data)1084 at32_add_device_eth(unsigned int id, struct macb_platform_data *data)
1085 {
1086 struct platform_device *pdev;
1087 u32 pin_mask;
1088
1089 switch (id) {
1090 case 0:
1091 pdev = &macb0_device;
1092
1093 pin_mask = (1 << 3); /* TXD0 */
1094 pin_mask |= (1 << 4); /* TXD1 */
1095 pin_mask |= (1 << 7); /* TXEN */
1096 pin_mask |= (1 << 8); /* TXCK */
1097 pin_mask |= (1 << 9); /* RXD0 */
1098 pin_mask |= (1 << 10); /* RXD1 */
1099 pin_mask |= (1 << 13); /* RXER */
1100 pin_mask |= (1 << 15); /* RXDV */
1101 pin_mask |= (1 << 16); /* MDC */
1102 pin_mask |= (1 << 17); /* MDIO */
1103
1104 if (!data->is_rmii) {
1105 pin_mask |= (1 << 0); /* COL */
1106 pin_mask |= (1 << 1); /* CRS */
1107 pin_mask |= (1 << 2); /* TXER */
1108 pin_mask |= (1 << 5); /* TXD2 */
1109 pin_mask |= (1 << 6); /* TXD3 */
1110 pin_mask |= (1 << 11); /* RXD2 */
1111 pin_mask |= (1 << 12); /* RXD3 */
1112 pin_mask |= (1 << 14); /* RXCK */
1113 #ifndef CONFIG_BOARD_MIMC200
1114 pin_mask |= (1 << 18); /* SPD */
1115 #endif
1116 }
1117
1118 select_peripheral(PIOC, pin_mask, PERIPH_A, 0);
1119
1120 break;
1121
1122 case 1:
1123 pdev = &macb1_device;
1124
1125 pin_mask = (1 << 13); /* TXD0 */
1126 pin_mask |= (1 << 14); /* TXD1 */
1127 pin_mask |= (1 << 11); /* TXEN */
1128 pin_mask |= (1 << 12); /* TXCK */
1129 pin_mask |= (1 << 10); /* RXD0 */
1130 pin_mask |= (1 << 6); /* RXD1 */
1131 pin_mask |= (1 << 5); /* RXER */
1132 pin_mask |= (1 << 4); /* RXDV */
1133 pin_mask |= (1 << 3); /* MDC */
1134 pin_mask |= (1 << 2); /* MDIO */
1135
1136 #ifndef CONFIG_BOARD_MIMC200
1137 if (!data->is_rmii)
1138 pin_mask |= (1 << 15); /* SPD */
1139 #endif
1140
1141 select_peripheral(PIOD, pin_mask, PERIPH_B, 0);
1142
1143 if (!data->is_rmii) {
1144 pin_mask = (1 << 19); /* COL */
1145 pin_mask |= (1 << 23); /* CRS */
1146 pin_mask |= (1 << 26); /* TXER */
1147 pin_mask |= (1 << 27); /* TXD2 */
1148 pin_mask |= (1 << 28); /* TXD3 */
1149 pin_mask |= (1 << 29); /* RXD2 */
1150 pin_mask |= (1 << 30); /* RXD3 */
1151 pin_mask |= (1 << 24); /* RXCK */
1152
1153 select_peripheral(PIOC, pin_mask, PERIPH_B, 0);
1154 }
1155 break;
1156
1157 default:
1158 return NULL;
1159 }
1160
1161 memcpy(pdev->dev.platform_data, data, sizeof(struct macb_platform_data));
1162 platform_device_register(pdev);
1163
1164 return pdev;
1165 }
1166 #endif
1167
1168 /* --------------------------------------------------------------------
1169 * SPI
1170 * -------------------------------------------------------------------- */
1171 static struct resource atmel_spi0_resource[] = {
1172 PBMEM(0xffe00000),
1173 IRQ(3),
1174 };
1175 DEFINE_DEV(atmel_spi, 0);
1176 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1177
1178 static struct resource atmel_spi1_resource[] = {
1179 PBMEM(0xffe00400),
1180 IRQ(4),
1181 };
1182 DEFINE_DEV(atmel_spi, 1);
1183 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1184
1185 void __init
at32_spi_setup_slaves(unsigned int bus_num,struct spi_board_info * b,unsigned int n)1186 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, unsigned int n)
1187 {
1188 /*
1189 * Manage the chipselects as GPIOs, normally using the same pins
1190 * the SPI controller expects; but boards can use other pins.
1191 */
1192 static u8 __initdata spi_pins[][4] = {
1193 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1194 GPIO_PIN_PA(5), GPIO_PIN_PA(20) },
1195 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1196 GPIO_PIN_PB(4), GPIO_PIN_PA(27) },
1197 };
1198 unsigned int pin, mode;
1199
1200 /* There are only 2 SPI controllers */
1201 if (bus_num > 1)
1202 return;
1203
1204 for (; n; n--, b++) {
1205 b->bus_num = bus_num;
1206 if (b->chip_select >= 4)
1207 continue;
1208 pin = (unsigned)b->controller_data;
1209 if (!pin) {
1210 pin = spi_pins[bus_num][b->chip_select];
1211 b->controller_data = (void *)pin;
1212 }
1213 mode = AT32_GPIOF_OUTPUT;
1214 if (!(b->mode & SPI_CS_HIGH))
1215 mode |= AT32_GPIOF_HIGH;
1216 at32_select_gpio(pin, mode);
1217 }
1218 }
1219
1220 struct platform_device *__init
at32_add_device_spi(unsigned int id,struct spi_board_info * b,unsigned int n)1221 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1222 {
1223 struct platform_device *pdev;
1224 u32 pin_mask;
1225
1226 switch (id) {
1227 case 0:
1228 pdev = &atmel_spi0_device;
1229 pin_mask = (1 << 1) | (1 << 2); /* MOSI & SCK */
1230
1231 /* pullup MISO so a level is always defined */
1232 select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
1233 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1234
1235 at32_spi_setup_slaves(0, b, n);
1236 break;
1237
1238 case 1:
1239 pdev = &atmel_spi1_device;
1240 pin_mask = (1 << 1) | (1 << 5); /* MOSI */
1241
1242 /* pullup MISO so a level is always defined */
1243 select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
1244 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
1245
1246 at32_spi_setup_slaves(1, b, n);
1247 break;
1248
1249 default:
1250 return NULL;
1251 }
1252
1253 spi_register_board_info(b, n);
1254 platform_device_register(pdev);
1255 return pdev;
1256 }
1257
1258 /* --------------------------------------------------------------------
1259 * TWI
1260 * -------------------------------------------------------------------- */
1261 static struct resource atmel_twi0_resource[] __initdata = {
1262 PBMEM(0xffe00800),
1263 IRQ(5),
1264 };
1265 static struct clk atmel_twi0_pclk = {
1266 .name = "twi_pclk",
1267 .parent = &pba_clk,
1268 .mode = pba_clk_mode,
1269 .get_rate = pba_clk_get_rate,
1270 .index = 2,
1271 };
1272
at32_add_device_twi(unsigned int id,struct i2c_board_info * b,unsigned int n)1273 struct platform_device *__init at32_add_device_twi(unsigned int id,
1274 struct i2c_board_info *b,
1275 unsigned int n)
1276 {
1277 struct platform_device *pdev;
1278 u32 pin_mask;
1279
1280 if (id != 0)
1281 return NULL;
1282
1283 pdev = platform_device_alloc("atmel_twi", id);
1284 if (!pdev)
1285 return NULL;
1286
1287 if (platform_device_add_resources(pdev, atmel_twi0_resource,
1288 ARRAY_SIZE(atmel_twi0_resource)))
1289 goto err_add_resources;
1290
1291 pin_mask = (1 << 6) | (1 << 7); /* SDA & SDL */
1292
1293 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1294
1295 atmel_twi0_pclk.dev = &pdev->dev;
1296
1297 if (b)
1298 i2c_register_board_info(id, b, n);
1299
1300 platform_device_add(pdev);
1301 return pdev;
1302
1303 err_add_resources:
1304 platform_device_put(pdev);
1305 return NULL;
1306 }
1307
1308 /* --------------------------------------------------------------------
1309 * MMC
1310 * -------------------------------------------------------------------- */
1311 static struct resource atmel_mci0_resource[] __initdata = {
1312 PBMEM(0xfff02400),
1313 IRQ(28),
1314 };
1315 static struct clk atmel_mci0_pclk = {
1316 .name = "mci_clk",
1317 .parent = &pbb_clk,
1318 .mode = pbb_clk_mode,
1319 .get_rate = pbb_clk_get_rate,
1320 .index = 9,
1321 };
1322
at32_mci_dma_filter(struct dma_chan * chan,void * pdata)1323 static bool at32_mci_dma_filter(struct dma_chan *chan, void *pdata)
1324 {
1325 struct dw_dma_slave *sl = pdata;
1326
1327 if (!sl)
1328 return false;
1329
1330 if (sl->dma_dev == chan->device->dev) {
1331 chan->private = sl;
1332 return true;
1333 }
1334
1335 return false;
1336 }
1337
1338 struct platform_device *__init
at32_add_device_mci(unsigned int id,struct mci_platform_data * data)1339 at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1340 {
1341 struct platform_device *pdev;
1342 struct dw_dma_slave *slave;
1343 u32 pioa_mask;
1344 u32 piob_mask;
1345
1346 if (id != 0 || !data)
1347 return NULL;
1348
1349 /* Must have at least one usable slot */
1350 if (!data->slot[0].bus_width && !data->slot[1].bus_width)
1351 return NULL;
1352
1353 pdev = platform_device_alloc("atmel_mci", id);
1354 if (!pdev)
1355 goto fail;
1356
1357 if (platform_device_add_resources(pdev, atmel_mci0_resource,
1358 ARRAY_SIZE(atmel_mci0_resource)))
1359 goto fail;
1360
1361 slave = kzalloc(sizeof(*slave), GFP_KERNEL);
1362 if (!slave)
1363 goto fail;
1364
1365 slave->dma_dev = &dw_dmac0_device.dev;
1366 slave->src_id = 0;
1367 slave->dst_id = 1;
1368 slave->m_master = 1;
1369 slave->p_master = 0;
1370
1371 data->dma_slave = slave;
1372 data->dma_filter = at32_mci_dma_filter;
1373
1374 if (platform_device_add_data(pdev, data,
1375 sizeof(struct mci_platform_data)))
1376 goto fail_free;
1377
1378 /* CLK line is common to both slots */
1379 pioa_mask = 1 << 10;
1380
1381 switch (data->slot[0].bus_width) {
1382 case 4:
1383 pioa_mask |= 1 << 13; /* DATA1 */
1384 pioa_mask |= 1 << 14; /* DATA2 */
1385 pioa_mask |= 1 << 15; /* DATA3 */
1386 /* fall through */
1387 case 1:
1388 pioa_mask |= 1 << 11; /* CMD */
1389 pioa_mask |= 1 << 12; /* DATA0 */
1390
1391 if (gpio_is_valid(data->slot[0].detect_pin))
1392 at32_select_gpio(data->slot[0].detect_pin, 0);
1393 if (gpio_is_valid(data->slot[0].wp_pin))
1394 at32_select_gpio(data->slot[0].wp_pin, 0);
1395 break;
1396 case 0:
1397 /* Slot is unused */
1398 break;
1399 default:
1400 goto fail_free;
1401 }
1402
1403 select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
1404 piob_mask = 0;
1405
1406 switch (data->slot[1].bus_width) {
1407 case 4:
1408 piob_mask |= 1 << 8; /* DATA1 */
1409 piob_mask |= 1 << 9; /* DATA2 */
1410 piob_mask |= 1 << 10; /* DATA3 */
1411 /* fall through */
1412 case 1:
1413 piob_mask |= 1 << 6; /* CMD */
1414 piob_mask |= 1 << 7; /* DATA0 */
1415 select_peripheral(PIOB, piob_mask, PERIPH_B, 0);
1416
1417 if (gpio_is_valid(data->slot[1].detect_pin))
1418 at32_select_gpio(data->slot[1].detect_pin, 0);
1419 if (gpio_is_valid(data->slot[1].wp_pin))
1420 at32_select_gpio(data->slot[1].wp_pin, 0);
1421 break;
1422 case 0:
1423 /* Slot is unused */
1424 break;
1425 default:
1426 if (!data->slot[0].bus_width)
1427 goto fail_free;
1428
1429 data->slot[1].bus_width = 0;
1430 break;
1431 }
1432
1433 atmel_mci0_pclk.dev = &pdev->dev;
1434
1435 platform_device_add(pdev);
1436 return pdev;
1437
1438 fail_free:
1439 kfree(slave);
1440 fail:
1441 data->dma_slave = NULL;
1442 platform_device_put(pdev);
1443 return NULL;
1444 }
1445
1446 /* --------------------------------------------------------------------
1447 * LCDC
1448 * -------------------------------------------------------------------- */
1449 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1450 static struct atmel_lcdfb_pdata atmel_lcdfb0_data;
1451 static struct resource atmel_lcdfb0_resource[] = {
1452 {
1453 .start = 0xff000000,
1454 .end = 0xff000fff,
1455 .flags = IORESOURCE_MEM,
1456 },
1457 IRQ(1),
1458 {
1459 /* Placeholder for pre-allocated fb memory */
1460 .start = 0x00000000,
1461 .end = 0x00000000,
1462 .flags = 0,
1463 },
1464 };
1465 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1466 DEV_CLK(hclk, atmel_lcdfb0, hsb, 7);
1467 static struct clk atmel_lcdfb0_pixclk = {
1468 .name = "lcdc_clk",
1469 .dev = &atmel_lcdfb0_device.dev,
1470 .mode = genclk_mode,
1471 .get_rate = genclk_get_rate,
1472 .set_rate = genclk_set_rate,
1473 .set_parent = genclk_set_parent,
1474 .index = 7,
1475 };
1476
1477 struct platform_device *__init
at32_add_device_lcdc(unsigned int id,struct atmel_lcdfb_pdata * data,unsigned long fbmem_start,unsigned long fbmem_len,u64 pin_mask)1478 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_pdata *data,
1479 unsigned long fbmem_start, unsigned long fbmem_len,
1480 u64 pin_mask)
1481 {
1482 struct platform_device *pdev;
1483 struct atmel_lcdfb_pdata *info;
1484 struct fb_monspecs *monspecs;
1485 struct fb_videomode *modedb;
1486 unsigned int modedb_size;
1487 u32 portc_mask, portd_mask, porte_mask;
1488
1489 /*
1490 * Do a deep copy of the fb data, monspecs and modedb. Make
1491 * sure all allocations are done before setting up the
1492 * portmux.
1493 */
1494 monspecs = kmemdup(data->default_monspecs,
1495 sizeof(struct fb_monspecs), GFP_KERNEL);
1496 if (!monspecs)
1497 return NULL;
1498
1499 modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1500 modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1501 if (!modedb)
1502 goto err_dup_modedb;
1503 monspecs->modedb = modedb;
1504
1505 switch (id) {
1506 case 0:
1507 pdev = &atmel_lcdfb0_device;
1508
1509 if (pin_mask == 0ULL)
1510 /* Default to "full" lcdc control signals and 24bit */
1511 pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;
1512
1513 /* LCDC on port C */
1514 portc_mask = pin_mask & 0xfff80000;
1515 select_peripheral(PIOC, portc_mask, PERIPH_A, 0);
1516
1517 /* LCDC on port D */
1518 portd_mask = pin_mask & 0x0003ffff;
1519 select_peripheral(PIOD, portd_mask, PERIPH_A, 0);
1520
1521 /* LCDC on port E */
1522 porte_mask = (pin_mask >> 32) & 0x0007ffff;
1523 select_peripheral(PIOE, porte_mask, PERIPH_B, 0);
1524
1525 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1526 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1527 break;
1528
1529 default:
1530 goto err_invalid_id;
1531 }
1532
1533 if (fbmem_len) {
1534 pdev->resource[2].start = fbmem_start;
1535 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1536 pdev->resource[2].flags = IORESOURCE_MEM;
1537 }
1538
1539 info = pdev->dev.platform_data;
1540 memcpy(info, data, sizeof(struct atmel_lcdfb_pdata));
1541 info->default_monspecs = monspecs;
1542
1543 pdev->name = "at32ap-lcdfb";
1544
1545 platform_device_register(pdev);
1546 return pdev;
1547
1548 err_invalid_id:
1549 kfree(modedb);
1550 err_dup_modedb:
1551 kfree(monspecs);
1552 return NULL;
1553 }
1554 #endif
1555
1556 /* --------------------------------------------------------------------
1557 * PWM
1558 * -------------------------------------------------------------------- */
1559 static struct resource atmel_pwm0_resource[] __initdata = {
1560 PBMEM(0xfff01400),
1561 IRQ(24),
1562 };
1563 static struct clk atmel_pwm0_mck = {
1564 .name = "at91sam9rl-pwm",
1565 .parent = &pbb_clk,
1566 .mode = pbb_clk_mode,
1567 .get_rate = pbb_clk_get_rate,
1568 .index = 5,
1569 };
1570
at32_add_device_pwm(u32 mask)1571 struct platform_device *__init at32_add_device_pwm(u32 mask)
1572 {
1573 struct platform_device *pdev;
1574 u32 pin_mask;
1575
1576 if (!mask)
1577 return NULL;
1578
1579 pdev = platform_device_alloc("at91sam9rl-pwm", 0);
1580 if (!pdev)
1581 return NULL;
1582
1583 if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1584 ARRAY_SIZE(atmel_pwm0_resource)))
1585 goto out_free_pdev;
1586
1587 pin_mask = 0;
1588 if (mask & (1 << 0))
1589 pin_mask |= (1 << 28);
1590 if (mask & (1 << 1))
1591 pin_mask |= (1 << 29);
1592 if (pin_mask > 0)
1593 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1594
1595 pin_mask = 0;
1596 if (mask & (1 << 2))
1597 pin_mask |= (1 << 21);
1598 if (mask & (1 << 3))
1599 pin_mask |= (1 << 22);
1600 if (pin_mask > 0)
1601 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1602
1603 atmel_pwm0_mck.dev = &pdev->dev;
1604
1605 platform_device_add(pdev);
1606
1607 return pdev;
1608
1609 out_free_pdev:
1610 platform_device_put(pdev);
1611 return NULL;
1612 }
1613
1614 /* --------------------------------------------------------------------
1615 * SSC
1616 * -------------------------------------------------------------------- */
1617 static struct resource ssc0_resource[] = {
1618 PBMEM(0xffe01c00),
1619 IRQ(10),
1620 };
1621 DEFINE_DEV(ssc, 0);
1622 DEV_CLK(pclk, ssc0, pba, 7);
1623
1624 static struct resource ssc1_resource[] = {
1625 PBMEM(0xffe02000),
1626 IRQ(11),
1627 };
1628 DEFINE_DEV(ssc, 1);
1629 DEV_CLK(pclk, ssc1, pba, 8);
1630
1631 static struct resource ssc2_resource[] = {
1632 PBMEM(0xffe02400),
1633 IRQ(12),
1634 };
1635 DEFINE_DEV(ssc, 2);
1636 DEV_CLK(pclk, ssc2, pba, 9);
1637
1638 struct platform_device *__init
at32_add_device_ssc(unsigned int id,unsigned int flags)1639 at32_add_device_ssc(unsigned int id, unsigned int flags)
1640 {
1641 struct platform_device *pdev;
1642 u32 pin_mask = 0;
1643
1644 switch (id) {
1645 case 0:
1646 pdev = &ssc0_device;
1647 if (flags & ATMEL_SSC_RF)
1648 pin_mask |= (1 << 21); /* RF */
1649 if (flags & ATMEL_SSC_RK)
1650 pin_mask |= (1 << 22); /* RK */
1651 if (flags & ATMEL_SSC_TK)
1652 pin_mask |= (1 << 23); /* TK */
1653 if (flags & ATMEL_SSC_TF)
1654 pin_mask |= (1 << 24); /* TF */
1655 if (flags & ATMEL_SSC_TD)
1656 pin_mask |= (1 << 25); /* TD */
1657 if (flags & ATMEL_SSC_RD)
1658 pin_mask |= (1 << 26); /* RD */
1659
1660 if (pin_mask > 0)
1661 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1662
1663 break;
1664 case 1:
1665 pdev = &ssc1_device;
1666 if (flags & ATMEL_SSC_RF)
1667 pin_mask |= (1 << 0); /* RF */
1668 if (flags & ATMEL_SSC_RK)
1669 pin_mask |= (1 << 1); /* RK */
1670 if (flags & ATMEL_SSC_TK)
1671 pin_mask |= (1 << 2); /* TK */
1672 if (flags & ATMEL_SSC_TF)
1673 pin_mask |= (1 << 3); /* TF */
1674 if (flags & ATMEL_SSC_TD)
1675 pin_mask |= (1 << 4); /* TD */
1676 if (flags & ATMEL_SSC_RD)
1677 pin_mask |= (1 << 5); /* RD */
1678
1679 if (pin_mask > 0)
1680 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1681
1682 break;
1683 case 2:
1684 pdev = &ssc2_device;
1685 if (flags & ATMEL_SSC_TD)
1686 pin_mask |= (1 << 13); /* TD */
1687 if (flags & ATMEL_SSC_RD)
1688 pin_mask |= (1 << 14); /* RD */
1689 if (flags & ATMEL_SSC_TK)
1690 pin_mask |= (1 << 15); /* TK */
1691 if (flags & ATMEL_SSC_TF)
1692 pin_mask |= (1 << 16); /* TF */
1693 if (flags & ATMEL_SSC_RF)
1694 pin_mask |= (1 << 17); /* RF */
1695 if (flags & ATMEL_SSC_RK)
1696 pin_mask |= (1 << 18); /* RK */
1697
1698 if (pin_mask > 0)
1699 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
1700
1701 break;
1702 default:
1703 return NULL;
1704 }
1705
1706 platform_device_register(pdev);
1707 return pdev;
1708 }
1709
1710 /* --------------------------------------------------------------------
1711 * USB Device Controller
1712 * -------------------------------------------------------------------- */
1713 static struct resource usba0_resource[] __initdata = {
1714 {
1715 .start = 0xff300000,
1716 .end = 0xff3fffff,
1717 .flags = IORESOURCE_MEM,
1718 }, {
1719 .start = 0xfff03000,
1720 .end = 0xfff033ff,
1721 .flags = IORESOURCE_MEM,
1722 },
1723 IRQ(31),
1724 };
1725 static struct clk usba0_pclk = {
1726 .name = "pclk",
1727 .parent = &pbb_clk,
1728 .mode = pbb_clk_mode,
1729 .get_rate = pbb_clk_get_rate,
1730 .index = 12,
1731 };
1732 static struct clk usba0_hclk = {
1733 .name = "hclk",
1734 .parent = &hsb_clk,
1735 .mode = hsb_clk_mode,
1736 .get_rate = hsb_clk_get_rate,
1737 .index = 6,
1738 };
1739
1740 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
1741 [idx] = { \
1742 .name = nam, \
1743 .index = idx, \
1744 .fifo_size = maxpkt, \
1745 .nr_banks = maxbk, \
1746 .can_dma = dma, \
1747 .can_isoc = isoc, \
1748 }
1749
1750 static struct usba_ep_data at32_usba_ep[] __initdata = {
1751 EP("ep0", 0, 64, 1, 0, 0),
1752 EP("ep1", 1, 512, 2, 1, 1),
1753 EP("ep2", 2, 512, 2, 1, 1),
1754 EP("ep3-int", 3, 64, 3, 1, 0),
1755 EP("ep4-int", 4, 64, 3, 1, 0),
1756 EP("ep5", 5, 1024, 3, 1, 1),
1757 EP("ep6", 6, 1024, 3, 1, 1),
1758 };
1759
1760 #undef EP
1761
1762 struct platform_device *__init
at32_add_device_usba(unsigned int id,struct usba_platform_data * data)1763 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1764 {
1765 /*
1766 * pdata doesn't have room for any endpoints, so we need to
1767 * append room for the ones we need right after it.
1768 */
1769 struct {
1770 struct usba_platform_data pdata;
1771 struct usba_ep_data ep[7];
1772 } usba_data;
1773 struct platform_device *pdev;
1774
1775 if (id != 0)
1776 return NULL;
1777
1778 pdev = platform_device_alloc("atmel_usba_udc", 0);
1779 if (!pdev)
1780 return NULL;
1781
1782 if (platform_device_add_resources(pdev, usba0_resource,
1783 ARRAY_SIZE(usba0_resource)))
1784 goto out_free_pdev;
1785
1786 if (data) {
1787 usba_data.pdata.vbus_pin = data->vbus_pin;
1788 usba_data.pdata.vbus_pin_inverted = data->vbus_pin_inverted;
1789 } else {
1790 usba_data.pdata.vbus_pin = -EINVAL;
1791 usba_data.pdata.vbus_pin_inverted = -EINVAL;
1792 }
1793
1794 data = &usba_data.pdata;
1795 data->num_ep = ARRAY_SIZE(at32_usba_ep);
1796 memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1797
1798 if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1799 goto out_free_pdev;
1800
1801 if (gpio_is_valid(data->vbus_pin))
1802 at32_select_gpio(data->vbus_pin, 0);
1803
1804 usba0_pclk.dev = &pdev->dev;
1805 usba0_hclk.dev = &pdev->dev;
1806
1807 platform_device_add(pdev);
1808
1809 return pdev;
1810
1811 out_free_pdev:
1812 platform_device_put(pdev);
1813 return NULL;
1814 }
1815
1816 /* --------------------------------------------------------------------
1817 * IDE / CompactFlash
1818 * -------------------------------------------------------------------- */
1819 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1820 static struct resource at32_smc_cs4_resource[] __initdata = {
1821 {
1822 .start = 0x04000000,
1823 .end = 0x07ffffff,
1824 .flags = IORESOURCE_MEM,
1825 },
1826 IRQ(~0UL), /* Magic IRQ will be overridden */
1827 };
1828 static struct resource at32_smc_cs5_resource[] __initdata = {
1829 {
1830 .start = 0x20000000,
1831 .end = 0x23ffffff,
1832 .flags = IORESOURCE_MEM,
1833 },
1834 IRQ(~0UL), /* Magic IRQ will be overridden */
1835 };
1836
at32_init_ide_or_cf(struct platform_device * pdev,unsigned int cs,unsigned int extint)1837 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1838 unsigned int cs, unsigned int extint)
1839 {
1840 static unsigned int extint_pin_map[4] __initdata = {
1841 (1 << 25),
1842 (1 << 26),
1843 (1 << 27),
1844 (1 << 28),
1845 };
1846 static bool common_pins_initialized __initdata = false;
1847 unsigned int extint_pin;
1848 int ret;
1849 u32 pin_mask;
1850
1851 if (extint >= ARRAY_SIZE(extint_pin_map))
1852 return -EINVAL;
1853 extint_pin = extint_pin_map[extint];
1854
1855 switch (cs) {
1856 case 4:
1857 ret = platform_device_add_resources(pdev,
1858 at32_smc_cs4_resource,
1859 ARRAY_SIZE(at32_smc_cs4_resource));
1860 if (ret)
1861 return ret;
1862
1863 /* NCS4 -> OE_N */
1864 select_peripheral(PIOE, (1 << 21), PERIPH_A, 0);
1865 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
1866 break;
1867 case 5:
1868 ret = platform_device_add_resources(pdev,
1869 at32_smc_cs5_resource,
1870 ARRAY_SIZE(at32_smc_cs5_resource));
1871 if (ret)
1872 return ret;
1873
1874 /* NCS5 -> OE_N */
1875 select_peripheral(PIOE, (1 << 22), PERIPH_A, 0);
1876 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
1877 break;
1878 default:
1879 return -EINVAL;
1880 }
1881
1882 if (!common_pins_initialized) {
1883 pin_mask = (1 << 19); /* CFCE1 -> CS0_N */
1884 pin_mask |= (1 << 20); /* CFCE2 -> CS1_N */
1885 pin_mask |= (1 << 23); /* CFRNW -> DIR */
1886 pin_mask |= (1 << 24); /* NWAIT <- IORDY */
1887
1888 select_peripheral(PIOE, pin_mask, PERIPH_A, 0);
1889
1890 common_pins_initialized = true;
1891 }
1892
1893 select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH);
1894
1895 pdev->resource[1].start = EIM_IRQ_BASE + extint;
1896 pdev->resource[1].end = pdev->resource[1].start;
1897
1898 return 0;
1899 }
1900
1901 struct platform_device *__init
at32_add_device_ide(unsigned int id,unsigned int extint,struct ide_platform_data * data)1902 at32_add_device_ide(unsigned int id, unsigned int extint,
1903 struct ide_platform_data *data)
1904 {
1905 struct platform_device *pdev;
1906
1907 pdev = platform_device_alloc("at32_ide", id);
1908 if (!pdev)
1909 goto fail;
1910
1911 if (platform_device_add_data(pdev, data,
1912 sizeof(struct ide_platform_data)))
1913 goto fail;
1914
1915 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1916 goto fail;
1917
1918 platform_device_add(pdev);
1919 return pdev;
1920
1921 fail:
1922 platform_device_put(pdev);
1923 return NULL;
1924 }
1925
1926 struct platform_device *__init
at32_add_device_cf(unsigned int id,unsigned int extint,struct cf_platform_data * data)1927 at32_add_device_cf(unsigned int id, unsigned int extint,
1928 struct cf_platform_data *data)
1929 {
1930 struct platform_device *pdev;
1931
1932 pdev = platform_device_alloc("at32_cf", id);
1933 if (!pdev)
1934 goto fail;
1935
1936 if (platform_device_add_data(pdev, data,
1937 sizeof(struct cf_platform_data)))
1938 goto fail;
1939
1940 if (at32_init_ide_or_cf(pdev, data->cs, extint))
1941 goto fail;
1942
1943 if (gpio_is_valid(data->detect_pin))
1944 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1945 if (gpio_is_valid(data->reset_pin))
1946 at32_select_gpio(data->reset_pin, 0);
1947 if (gpio_is_valid(data->vcc_pin))
1948 at32_select_gpio(data->vcc_pin, 0);
1949 /* READY is used as extint, so we can't select it as gpio */
1950
1951 platform_device_add(pdev);
1952 return pdev;
1953
1954 fail:
1955 platform_device_put(pdev);
1956 return NULL;
1957 }
1958 #endif
1959
1960 /* --------------------------------------------------------------------
1961 * NAND Flash / SmartMedia
1962 * -------------------------------------------------------------------- */
1963 static struct resource smc_cs3_resource[] __initdata = {
1964 {
1965 .start = 0x0c000000,
1966 .end = 0x0fffffff,
1967 .flags = IORESOURCE_MEM,
1968 }, {
1969 .start = 0xfff03c00,
1970 .end = 0xfff03fff,
1971 .flags = IORESOURCE_MEM,
1972 },
1973 };
1974
1975 struct platform_device *__init
at32_add_device_nand(unsigned int id,struct atmel_nand_data * data)1976 at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
1977 {
1978 struct platform_device *pdev;
1979
1980 if (id != 0 || !data)
1981 return NULL;
1982
1983 pdev = platform_device_alloc("atmel_nand", id);
1984 if (!pdev)
1985 goto fail;
1986
1987 if (platform_device_add_resources(pdev, smc_cs3_resource,
1988 ARRAY_SIZE(smc_cs3_resource)))
1989 goto fail;
1990
1991 /* For at32ap7000, we use the reset workaround for nand driver */
1992 data->need_reset_workaround = true;
1993
1994 if (platform_device_add_data(pdev, data,
1995 sizeof(struct atmel_nand_data)))
1996 goto fail;
1997
1998 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
1999 if (data->enable_pin)
2000 at32_select_gpio(data->enable_pin,
2001 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
2002 if (data->rdy_pin)
2003 at32_select_gpio(data->rdy_pin, 0);
2004 if (data->det_pin)
2005 at32_select_gpio(data->det_pin, 0);
2006
2007 platform_device_add(pdev);
2008 return pdev;
2009
2010 fail:
2011 platform_device_put(pdev);
2012 return NULL;
2013 }
2014
2015 /* --------------------------------------------------------------------
2016 * AC97C
2017 * -------------------------------------------------------------------- */
2018 static struct resource atmel_ac97c0_resource[] __initdata = {
2019 PBMEM(0xfff02800),
2020 IRQ(29),
2021 };
2022 static struct clk atmel_ac97c0_pclk = {
2023 .name = "pclk",
2024 .parent = &pbb_clk,
2025 .mode = pbb_clk_mode,
2026 .get_rate = pbb_clk_get_rate,
2027 .index = 10,
2028 };
2029
2030 struct platform_device *__init
at32_add_device_ac97c(unsigned int id,struct ac97c_platform_data * data,unsigned int flags)2031 at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
2032 unsigned int flags)
2033 {
2034 struct platform_device *pdev;
2035 struct dw_dma_slave *rx_dws;
2036 struct dw_dma_slave *tx_dws;
2037 struct ac97c_platform_data _data;
2038 u32 pin_mask;
2039
2040 if (id != 0)
2041 return NULL;
2042
2043 pdev = platform_device_alloc("atmel_ac97c", id);
2044 if (!pdev)
2045 return NULL;
2046
2047 if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
2048 ARRAY_SIZE(atmel_ac97c0_resource)))
2049 goto out_free_resources;
2050
2051 if (!data) {
2052 data = &_data;
2053 memset(data, 0, sizeof(struct ac97c_platform_data));
2054 data->reset_pin = -ENODEV;
2055 }
2056
2057 rx_dws = &data->rx_dws;
2058 tx_dws = &data->tx_dws;
2059
2060 /* Check if DMA slave interface for capture should be configured. */
2061 if (flags & AC97C_CAPTURE) {
2062 rx_dws->dma_dev = &dw_dmac0_device.dev;
2063 rx_dws->src_id = 3;
2064 rx_dws->m_master = 0;
2065 rx_dws->p_master = 1;
2066 }
2067
2068 /* Check if DMA slave interface for playback should be configured. */
2069 if (flags & AC97C_PLAYBACK) {
2070 tx_dws->dma_dev = &dw_dmac0_device.dev;
2071 tx_dws->dst_id = 4;
2072 tx_dws->m_master = 0;
2073 tx_dws->p_master = 1;
2074 }
2075
2076 if (platform_device_add_data(pdev, data,
2077 sizeof(struct ac97c_platform_data)))
2078 goto out_free_resources;
2079
2080 /* SDO | SYNC | SCLK | SDI */
2081 pin_mask = (1 << 20) | (1 << 21) | (1 << 22) | (1 << 23);
2082
2083 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
2084
2085 if (gpio_is_valid(data->reset_pin))
2086 at32_select_gpio(data->reset_pin, AT32_GPIOF_OUTPUT
2087 | AT32_GPIOF_HIGH);
2088
2089 atmel_ac97c0_pclk.dev = &pdev->dev;
2090
2091 platform_device_add(pdev);
2092 return pdev;
2093
2094 out_free_resources:
2095 platform_device_put(pdev);
2096 return NULL;
2097 }
2098
2099 /* --------------------------------------------------------------------
2100 * ABDAC
2101 * -------------------------------------------------------------------- */
2102 static struct resource abdac0_resource[] __initdata = {
2103 PBMEM(0xfff02000),
2104 IRQ(27),
2105 };
2106 static struct clk abdac0_pclk = {
2107 .name = "pclk",
2108 .parent = &pbb_clk,
2109 .mode = pbb_clk_mode,
2110 .get_rate = pbb_clk_get_rate,
2111 .index = 8,
2112 };
2113 static struct clk abdac0_sample_clk = {
2114 .name = "sample_clk",
2115 .mode = genclk_mode,
2116 .get_rate = genclk_get_rate,
2117 .set_rate = genclk_set_rate,
2118 .set_parent = genclk_set_parent,
2119 .index = 6,
2120 };
2121
2122 struct platform_device *__init
at32_add_device_abdac(unsigned int id,struct atmel_abdac_pdata * data)2123 at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data)
2124 {
2125 struct platform_device *pdev;
2126 struct dw_dma_slave *dws;
2127 u32 pin_mask;
2128
2129 if (id != 0 || !data)
2130 return NULL;
2131
2132 pdev = platform_device_alloc("atmel_abdac", id);
2133 if (!pdev)
2134 return NULL;
2135
2136 if (platform_device_add_resources(pdev, abdac0_resource,
2137 ARRAY_SIZE(abdac0_resource)))
2138 goto out_free_resources;
2139
2140 dws = &data->dws;
2141
2142 dws->dma_dev = &dw_dmac0_device.dev;
2143 dws->dst_id = 2;
2144 dws->m_master = 0;
2145 dws->p_master = 1;
2146
2147 if (platform_device_add_data(pdev, data,
2148 sizeof(struct atmel_abdac_pdata)))
2149 goto out_free_resources;
2150
2151 pin_mask = (1 << 20) | (1 << 22); /* DATA1 & DATAN1 */
2152 pin_mask |= (1 << 21) | (1 << 23); /* DATA0 & DATAN0 */
2153
2154 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
2155
2156 abdac0_pclk.dev = &pdev->dev;
2157 abdac0_sample_clk.dev = &pdev->dev;
2158
2159 platform_device_add(pdev);
2160 return pdev;
2161
2162 out_free_resources:
2163 platform_device_put(pdev);
2164 return NULL;
2165 }
2166
2167 /* --------------------------------------------------------------------
2168 * GCLK
2169 * -------------------------------------------------------------------- */
2170 static struct clk gclk0 = {
2171 .name = "gclk0",
2172 .mode = genclk_mode,
2173 .get_rate = genclk_get_rate,
2174 .set_rate = genclk_set_rate,
2175 .set_parent = genclk_set_parent,
2176 .index = 0,
2177 };
2178 static struct clk gclk1 = {
2179 .name = "gclk1",
2180 .mode = genclk_mode,
2181 .get_rate = genclk_get_rate,
2182 .set_rate = genclk_set_rate,
2183 .set_parent = genclk_set_parent,
2184 .index = 1,
2185 };
2186 static struct clk gclk2 = {
2187 .name = "gclk2",
2188 .mode = genclk_mode,
2189 .get_rate = genclk_get_rate,
2190 .set_rate = genclk_set_rate,
2191 .set_parent = genclk_set_parent,
2192 .index = 2,
2193 };
2194 static struct clk gclk3 = {
2195 .name = "gclk3",
2196 .mode = genclk_mode,
2197 .get_rate = genclk_get_rate,
2198 .set_rate = genclk_set_rate,
2199 .set_parent = genclk_set_parent,
2200 .index = 3,
2201 };
2202 static struct clk gclk4 = {
2203 .name = "gclk4",
2204 .mode = genclk_mode,
2205 .get_rate = genclk_get_rate,
2206 .set_rate = genclk_set_rate,
2207 .set_parent = genclk_set_parent,
2208 .index = 4,
2209 };
2210
2211 static __initdata struct clk *init_clocks[] = {
2212 &osc32k,
2213 &osc0,
2214 &osc1,
2215 &pll0,
2216 &pll1,
2217 &cpu_clk,
2218 &hsb_clk,
2219 &pba_clk,
2220 &pbb_clk,
2221 &at32_pm_pclk,
2222 &at32_intc0_pclk,
2223 &at32_hmatrix_clk,
2224 &ebi_clk,
2225 &hramc_clk,
2226 &sdramc_clk,
2227 &smc0_pclk,
2228 &smc0_mck,
2229 &pdc_hclk,
2230 &pdc_pclk,
2231 &dw_dmac0_hclk,
2232 &pico_clk,
2233 &pio0_mck,
2234 &pio1_mck,
2235 &pio2_mck,
2236 &pio3_mck,
2237 &pio4_mck,
2238 &at32_tcb0_t0_clk,
2239 &at32_tcb1_t0_clk,
2240 &atmel_psif0_pclk,
2241 &atmel_psif1_pclk,
2242 &atmel_usart0_usart,
2243 &atmel_usart1_usart,
2244 &atmel_usart2_usart,
2245 &atmel_usart3_usart,
2246 &atmel_pwm0_mck,
2247 #if defined(CONFIG_CPU_AT32AP7000)
2248 &macb0_hclk,
2249 &macb0_pclk,
2250 &macb1_hclk,
2251 &macb1_pclk,
2252 #endif
2253 &atmel_spi0_spi_clk,
2254 &atmel_spi1_spi_clk,
2255 &atmel_twi0_pclk,
2256 &atmel_mci0_pclk,
2257 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2258 &atmel_lcdfb0_hclk,
2259 &atmel_lcdfb0_pixclk,
2260 #endif
2261 &ssc0_pclk,
2262 &ssc1_pclk,
2263 &ssc2_pclk,
2264 &usba0_hclk,
2265 &usba0_pclk,
2266 &atmel_ac97c0_pclk,
2267 &abdac0_pclk,
2268 &abdac0_sample_clk,
2269 &gclk0,
2270 &gclk1,
2271 &gclk2,
2272 &gclk3,
2273 &gclk4,
2274 };
2275
setup_platform(void)2276 void __init setup_platform(void)
2277 {
2278 u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2279 int i;
2280
2281 if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2282 main_clock = &pll0;
2283 cpu_clk.parent = &pll0;
2284 } else {
2285 main_clock = &osc0;
2286 cpu_clk.parent = &osc0;
2287 }
2288
2289 if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2290 pll0.parent = &osc1;
2291 if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2292 pll1.parent = &osc1;
2293
2294 genclk_init_parent(&gclk0);
2295 genclk_init_parent(&gclk1);
2296 genclk_init_parent(&gclk2);
2297 genclk_init_parent(&gclk3);
2298 genclk_init_parent(&gclk4);
2299 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2300 genclk_init_parent(&atmel_lcdfb0_pixclk);
2301 #endif
2302 genclk_init_parent(&abdac0_sample_clk);
2303
2304 /*
2305 * Build initial dynamic clock list by registering all clocks
2306 * from the array.
2307 * At the same time, turn on all clocks that have at least one
2308 * user already, and turn off everything else. We only do this
2309 * for module clocks, and even though it isn't particularly
2310 * pretty to check the address of the mode function, it should
2311 * do the trick...
2312 */
2313 for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
2314 struct clk *clk = init_clocks[i];
2315
2316 /* first, register clock */
2317 at32_clk_register(clk);
2318
2319 if (clk->users == 0)
2320 continue;
2321
2322 if (clk->mode == &cpu_clk_mode)
2323 cpu_mask |= 1 << clk->index;
2324 else if (clk->mode == &hsb_clk_mode)
2325 hsb_mask |= 1 << clk->index;
2326 else if (clk->mode == &pba_clk_mode)
2327 pba_mask |= 1 << clk->index;
2328 else if (clk->mode == &pbb_clk_mode)
2329 pbb_mask |= 1 << clk->index;
2330 }
2331
2332 pm_writel(CPU_MASK, cpu_mask);
2333 pm_writel(HSB_MASK, hsb_mask);
2334 pm_writel(PBA_MASK, pba_mask);
2335 pm_writel(PBB_MASK, pbb_mask);
2336
2337 /* Initialize the port muxes */
2338 at32_init_pio(&pio0_device);
2339 at32_init_pio(&pio1_device);
2340 at32_init_pio(&pio2_device);
2341 at32_init_pio(&pio3_device);
2342 at32_init_pio(&pio4_device);
2343 }
2344
2345 struct gen_pool *sram_pool;
2346
sram_init(void)2347 static int __init sram_init(void)
2348 {
2349 struct gen_pool *pool;
2350
2351 /* 1KiB granularity */
2352 pool = gen_pool_create(10, -1);
2353 if (!pool)
2354 goto fail;
2355
2356 if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2357 goto err_pool_add;
2358
2359 sram_pool = pool;
2360 return 0;
2361
2362 err_pool_add:
2363 gen_pool_destroy(pool);
2364 fail:
2365 pr_err("Failed to create SRAM pool\n");
2366 return -ENOMEM;
2367 }
2368 core_initcall(sram_init);
2369