1 /* 2 * DO NOT EDIT THIS FILE 3 * This file is under version control at 4 * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/ 5 * and can be replaced with that version at any time 6 * DO NOT EDIT THIS FILE 7 * 8 * Copyright 2004-2012 Analog Devices Inc. 9 * Licensed under the Clear BSD license. 10 */ 11 12 /* This file should be up to date with: 13 * - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List 14 */ 15 16 #if __SILICON_REVISION__ < 0 17 # error will not work on BF609 silicon version 18 #endif 19 20 #ifndef _MACH_ANOMALY_H_ 21 #define _MACH_ANOMALY_H_ 22 23 /* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */ 24 #define ANOMALY_16000003 (1) 25 /* The EPPI Data Enable (DEN) Signal is Not Functional */ 26 #define ANOMALY_16000004 (__SILICON_REVISION__ < 1) 27 /* Using L1 Instruction Cache with Parity Enabled is Unreliable */ 28 #define ANOMALY_16000005 (__SILICON_REVISION__ < 1) 29 /* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */ 30 #define ANOMALY_16000006 (__SILICON_REVISION__ < 1) 31 /* DDR2 Memory Reads May Fail Intermittently */ 32 #define ANOMALY_16000007 (1) 33 /* Instruction Memory Stalls Can Cause IFLUSH to Fail */ 34 #define ANOMALY_16000008 (1) 35 /* TestSET Instruction Cannot Be Interrupted */ 36 #define ANOMALY_16000009 (1) 37 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 38 #define ANOMALY_16000010 (1) 39 /* False Hardware Error when RETI Points to Invalid Memory */ 40 #define ANOMALY_16000011 (1) 41 /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ 42 #define ANOMALY_16000012 (1) 43 /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 44 #define ANOMALY_16000013 (1) 45 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 46 #define ANOMALY_16000014 (1) 47 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ 48 #define ANOMALY_16000015 (1) 49 /* Speculative Fetches Can Cause Undesired External FIFO Operations */ 50 #define ANOMALY_16000017 (1) 51 /* RSI Boot Cleanup Routine Does Not Clear Registers */ 52 #define ANOMALY_16000018 (__SILICON_REVISION__ < 1) 53 /* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */ 54 #define ANOMALY_16000019 (__SILICON_REVISION__ < 1) 55 /* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */ 56 #define ANOMALY_16000020 (__SILICON_REVISION__ < 1) 57 /* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hibernate/Wakeup Sequence */ 58 #define ANOMALY_16000021 (__SILICON_REVISION__ < 1) 59 /* Boot Code Fails to Enable Parity Fault Detection */ 60 #define ANOMALY_16000022 (__SILICON_REVISION__ < 1) 61 /* Rom_SysControl Does not Update CGU0_CLKOUTSEL */ 62 #define ANOMALY_16000023 (__SILICON_REVISION__ < 1) 63 /* Spurious Fault Signaled After Clearing an Externally Generated Fault */ 64 #define ANOMALY_16000024 (1) 65 /* SPORT May Drive Data Pins During Inactive Channels in Multichannel Mode */ 66 #define ANOMALY_16000025 (1) 67 /* USB DMA interrupt status do not show the DMA channel interrupt in the DMA ISR */ 68 #define ANOMALY_16000027 (__SILICON_REVISION__ < 1) 69 /* Default SPI Master Boot Mode Setting is Incorrect */ 70 #define ANOMALY_16000028 (__SILICON_REVISION__ < 1) 71 /* PPI tDFSPI Timing Does Not Meet Data Sheet Specification */ 72 #define ANOMALY_16000027 (__SILICON_REVISION__ < 1) 73 /* Interrupted Core Reads of MMRs May Cause Data Loss */ 74 #define ANOMALY_16000030 (__SILICON_REVISION__ < 1) 75 /* Incorrect Default USB_PLL_OSC.PLLM Value */ 76 #define ANOMALY_16000031 (__SILICON_REVISION__ < 1) 77 /* Core Reads of System MMRs May Cause the Core to Hang */ 78 #define ANOMALY_16000032 (__SILICON_REVISION__ < 1) 79 /* PPI Data Underflow on First Word Not Reported in Certain Modes */ 80 #define ANOMALY_16000033 (1) 81 /* CNV1 Red Pixel Substitution feature not functional in the PVP */ 82 #define ANOMALY_16000034 (__SILICON_REVISION__ < 1) 83 /* IPF0 Output Port Color Separation feature not functional */ 84 #define ANOMALY_16000035 (__SILICON_REVISION__ < 1) 85 /* Spurious USB Wake From Hibernate May Occur When USB_VBUS is Low */ 86 #define ANOMALY_16000036 (__SILICON_REVISION__ < 1) 87 /* Core RAISE 2 Instruction Not Latched When Executed at Priority Level 0, 1, or 2 */ 88 #define ANOMALY_16000037 (__SILICON_REVISION__ < 1) 89 /* Spurious Unhandled NMI or L1 Memory Parity Error Interrupt May Occur Upon Entering the NMI ISR */ 90 #define ANOMALY_16000038 (__SILICON_REVISION__ < 1) 91 /* CGU_STAT.PLOCKERR Bit May be Unreliable */ 92 #define ANOMALY_16000039 (1) 93 /* JTAG Emulator Reads of SDU_IDCODE Alter Register Contents */ 94 #define ANOMALY_16000040 (1) 95 /* IFLUSH Instruction Causes Parity Error When Parity Is Enabled */ 96 #define ANOMALY_16000041 (1) 97 /* Instruction Cache Failure When Parity Is Enabled */ 98 #define ANOMALY_16000042 (__SILICON_REVISION__ == 1) 99 100 /* Anomalies that don't exist on this proc */ 101 #define ANOMALY_05000158 (0) 102 #define ANOMALY_05000189 (0) 103 #define ANOMALY_05000198 (0) 104 #define ANOMALY_05000220 (0) 105 #define ANOMALY_05000230 (0) 106 #define ANOMALY_05000231 (0) 107 #define ANOMALY_05000244 (0) 108 #define ANOMALY_05000263 (0) 109 #define ANOMALY_05000273 (0) 110 #define ANOMALY_05000274 (0) 111 #define ANOMALY_05000278 (0) 112 #define ANOMALY_05000281 (0) 113 #define ANOMALY_05000287 (0) 114 #define ANOMALY_05000311 (0) 115 #define ANOMALY_05000312 (0) 116 #define ANOMALY_05000323 (0) 117 #define ANOMALY_05000363 (0) 118 #define ANOMALY_05000380 (0) 119 #define ANOMALY_05000448 (0) 120 #define ANOMALY_05000450 (0) 121 #define ANOMALY_05000456 (0) 122 #define ANOMALY_05000480 (0) 123 #define ANOMALY_05000481 (1) 124 125 /* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */ 126 #define ANOMALY_05000491 ANOMALY_16000008 127 #define ANOMALY_05000477 ANOMALY_16000009 128 #define ANOMALY_05000443 ANOMALY_16000010 129 #define ANOMALY_05000461 ANOMALY_16000011 130 #define ANOMALY_05000426 ANOMALY_16000012 131 #define ANOMALY_05000310 ANOMALY_16000013 132 #define ANOMALY_05000245 ANOMALY_16000014 133 #define ANOMALY_05000074 ANOMALY_16000015 134 #define ANOMALY_05000416 ANOMALY_16000017 135 136 137 #endif 138