1 /*
2 * linux/arch/cris/arch-v10/mm/init.c
3 *
4 */
5 #include <linux/mmzone.h>
6 #include <linux/init.h>
7 #include <linux/bootmem.h>
8 #include <linux/mm.h>
9 #include <asm/pgtable.h>
10 #include <asm/page.h>
11 #include <asm/types.h>
12 #include <asm/mmu.h>
13 #include <asm/io.h>
14 #include <asm/mmu_context.h>
15 #include <arch/svinto.h>
16
17 extern void tlb_init(void);
18
19 /*
20 * The kernel is already mapped with a kernel segment at kseg_c so
21 * we don't need to map it with a page table. However head.S also
22 * temporarily mapped it at kseg_4 so we should set up the ksegs again,
23 * clear the TLB and do some other paging setup stuff.
24 */
25
26 void __init
paging_init(void)27 paging_init(void)
28 {
29 int i;
30 unsigned long zones_size[MAX_NR_ZONES];
31
32 printk("Setting up paging and the MMU.\n");
33
34 /* clear out the init_mm.pgd that will contain the kernel's mappings */
35
36 for(i = 0; i < PTRS_PER_PGD; i++)
37 swapper_pg_dir[i] = __pgd(0);
38
39 /* make sure the current pgd table points to something sane
40 * (even if it is most probably not used until the next
41 * switch_mm)
42 */
43
44 per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd;
45
46 /* initialise the TLB (tlb.c) */
47
48 tlb_init();
49
50 /* see README.mm for details on the KSEG setup */
51
52 #ifdef CONFIG_CRIS_LOW_MAP
53 /* Etrax-100 LX version 1 has a bug so that we cannot map anything
54 * across the 0x80000000 boundary, so we need to shrink the user-virtual
55 * area to 0x50000000 instead of 0xb0000000 and map things slightly
56 * different. The unused areas are marked as paged so that we can catch
57 * freak kernel accesses there.
58 *
59 * The ARTPEC chip is mapped at 0xa so we pass that segment straight
60 * through. We cannot vremap it because the vmalloc area is below 0x8
61 * and Juliette needs an uncached area above 0x8.
62 *
63 * Same thing with 0xc and 0x9, which is memory-mapped I/O on some boards.
64 * We map them straight over in LOW_MAP, but use vremap in LX version 2.
65 */
66
67 #define CACHED_BOOTROM (KSEG_F | 0x08000000UL)
68
69 *R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg ) | /* bootrom */
70 IO_STATE(R_MMU_KSEG, seg_e, page ) |
71 IO_STATE(R_MMU_KSEG, seg_d, page ) |
72 IO_STATE(R_MMU_KSEG, seg_c, page ) |
73 IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */
74 IO_STATE(R_MMU_KSEG, seg_a, page ) |
75 IO_STATE(R_MMU_KSEG, seg_9, seg ) | /* LED's on some boards */
76 IO_STATE(R_MMU_KSEG, seg_8, seg ) | /* CSE0/1, flash and I/O */
77 IO_STATE(R_MMU_KSEG, seg_7, page ) | /* kernel vmalloc area */
78 IO_STATE(R_MMU_KSEG, seg_6, seg ) | /* kernel DRAM area */
79 IO_STATE(R_MMU_KSEG, seg_5, seg ) | /* cached flash */
80 IO_STATE(R_MMU_KSEG, seg_4, page ) | /* user area */
81 IO_STATE(R_MMU_KSEG, seg_3, page ) | /* user area */
82 IO_STATE(R_MMU_KSEG, seg_2, page ) | /* user area */
83 IO_STATE(R_MMU_KSEG, seg_1, page ) | /* user area */
84 IO_STATE(R_MMU_KSEG, seg_0, page ) ); /* user area */
85
86 *R_MMU_KBASE_HI = ( IO_FIELD(R_MMU_KBASE_HI, base_f, 0x3 ) |
87 IO_FIELD(R_MMU_KBASE_HI, base_e, 0x0 ) |
88 IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) |
89 IO_FIELD(R_MMU_KBASE_HI, base_c, 0x0 ) |
90 IO_FIELD(R_MMU_KBASE_HI, base_b, 0xb ) |
91 IO_FIELD(R_MMU_KBASE_HI, base_a, 0x0 ) |
92 IO_FIELD(R_MMU_KBASE_HI, base_9, 0x9 ) |
93 IO_FIELD(R_MMU_KBASE_HI, base_8, 0x8 ) );
94
95 *R_MMU_KBASE_LO = ( IO_FIELD(R_MMU_KBASE_LO, base_7, 0x0 ) |
96 IO_FIELD(R_MMU_KBASE_LO, base_6, 0x4 ) |
97 IO_FIELD(R_MMU_KBASE_LO, base_5, 0x0 ) |
98 IO_FIELD(R_MMU_KBASE_LO, base_4, 0x0 ) |
99 IO_FIELD(R_MMU_KBASE_LO, base_3, 0x0 ) |
100 IO_FIELD(R_MMU_KBASE_LO, base_2, 0x0 ) |
101 IO_FIELD(R_MMU_KBASE_LO, base_1, 0x0 ) |
102 IO_FIELD(R_MMU_KBASE_LO, base_0, 0x0 ) );
103 #else
104 /* This code is for the corrected Etrax-100 LX version 2... */
105
106 #define CACHED_BOOTROM (KSEG_A | 0x08000000UL)
107
108 *R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg ) | /* cached flash */
109 IO_STATE(R_MMU_KSEG, seg_e, seg ) | /* uncached flash */
110 IO_STATE(R_MMU_KSEG, seg_d, page ) | /* vmalloc area */
111 IO_STATE(R_MMU_KSEG, seg_c, seg ) | /* kernel area */
112 IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */
113 IO_STATE(R_MMU_KSEG, seg_a, seg ) | /* bootrom */
114 IO_STATE(R_MMU_KSEG, seg_9, page ) | /* user area */
115 IO_STATE(R_MMU_KSEG, seg_8, page ) |
116 IO_STATE(R_MMU_KSEG, seg_7, page ) |
117 IO_STATE(R_MMU_KSEG, seg_6, page ) |
118 IO_STATE(R_MMU_KSEG, seg_5, page ) |
119 IO_STATE(R_MMU_KSEG, seg_4, page ) |
120 IO_STATE(R_MMU_KSEG, seg_3, page ) |
121 IO_STATE(R_MMU_KSEG, seg_2, page ) |
122 IO_STATE(R_MMU_KSEG, seg_1, page ) |
123 IO_STATE(R_MMU_KSEG, seg_0, page ) );
124
125 *R_MMU_KBASE_HI = ( IO_FIELD(R_MMU_KBASE_HI, base_f, 0x0 ) |
126 IO_FIELD(R_MMU_KBASE_HI, base_e, 0x8 ) |
127 IO_FIELD(R_MMU_KBASE_HI, base_d, 0x0 ) |
128 IO_FIELD(R_MMU_KBASE_HI, base_c, 0x4 ) |
129 IO_FIELD(R_MMU_KBASE_HI, base_b, 0xb ) |
130 IO_FIELD(R_MMU_KBASE_HI, base_a, 0x3 ) |
131 IO_FIELD(R_MMU_KBASE_HI, base_9, 0x0 ) |
132 IO_FIELD(R_MMU_KBASE_HI, base_8, 0x0 ) );
133
134 *R_MMU_KBASE_LO = ( IO_FIELD(R_MMU_KBASE_LO, base_7, 0x0 ) |
135 IO_FIELD(R_MMU_KBASE_LO, base_6, 0x0 ) |
136 IO_FIELD(R_MMU_KBASE_LO, base_5, 0x0 ) |
137 IO_FIELD(R_MMU_KBASE_LO, base_4, 0x0 ) |
138 IO_FIELD(R_MMU_KBASE_LO, base_3, 0x0 ) |
139 IO_FIELD(R_MMU_KBASE_LO, base_2, 0x0 ) |
140 IO_FIELD(R_MMU_KBASE_LO, base_1, 0x0 ) |
141 IO_FIELD(R_MMU_KBASE_LO, base_0, 0x0 ) );
142 #endif
143
144 *R_MMU_CONTEXT = ( IO_FIELD(R_MMU_CONTEXT, page_id, 0 ) );
145
146 /* The MMU has been enabled ever since head.S but just to make
147 * it totally obvious we do it here as well.
148 */
149
150 *R_MMU_CTRL = ( IO_STATE(R_MMU_CTRL, inv_excp, enable ) |
151 IO_STATE(R_MMU_CTRL, acc_excp, enable ) |
152 IO_STATE(R_MMU_CTRL, we_excp, enable ) );
153
154 *R_MMU_ENABLE = IO_STATE(R_MMU_ENABLE, mmu_enable, enable);
155
156 /*
157 * initialize the bad page table and bad page to point
158 * to a couple of allocated pages
159 */
160
161 empty_zero_page = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
162 memset((void *)empty_zero_page, 0, PAGE_SIZE);
163
164 /* All pages are DMA'able in Etrax, so put all in the DMA'able zone */
165
166 zones_size[0] = ((unsigned long)high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
167
168 for (i = 1; i < MAX_NR_ZONES; i++)
169 zones_size[i] = 0;
170
171 /* Use free_area_init_node instead of free_area_init, because the former
172 * is designed for systems where the DRAM starts at an address substantially
173 * higher than 0, like us (we start at PAGE_OFFSET). This saves space in the
174 * mem_map page array.
175 */
176
177 free_area_init_node(0, zones_size, PAGE_OFFSET >> PAGE_SHIFT, 0);
178 }
179
180 /* Initialize remaps of some I/O-ports. It is important that this
181 * is called before any driver is initialized.
182 */
183
184 static int
init_ioremap(void)185 __init init_ioremap(void)
186 {
187
188 /* Give the external I/O-port addresses their values */
189
190 #ifdef CONFIG_CRIS_LOW_MAP
191 /* Simply a linear map (see the KSEG map above in paging_init) */
192 port_cse1_addr = (volatile unsigned long *)(MEM_CSE1_START |
193 MEM_NON_CACHEABLE);
194 port_csp0_addr = (volatile unsigned long *)(MEM_CSP0_START |
195 MEM_NON_CACHEABLE);
196 port_csp4_addr = (volatile unsigned long *)(MEM_CSP4_START |
197 MEM_NON_CACHEABLE);
198 #else
199 /* Note that nothing blows up just because we do this remapping
200 * it's ok even if the ports are not used or connected
201 * to anything (or connected to a non-I/O thing) */
202 port_cse1_addr = (volatile unsigned long *)
203 ioremap((unsigned long)(MEM_CSE1_START | MEM_NON_CACHEABLE), 16);
204 port_csp0_addr = (volatile unsigned long *)
205 ioremap((unsigned long)(MEM_CSP0_START | MEM_NON_CACHEABLE), 16);
206 port_csp4_addr = (volatile unsigned long *)
207 ioremap((unsigned long)(MEM_CSP4_START | MEM_NON_CACHEABLE), 16);
208 #endif
209 return 0;
210 }
211
212 __initcall(init_ioremap);
213
214 /* Helper function for the two below */
215
216 static inline void
flush_etrax_cacherange(void * startadr,int length)217 flush_etrax_cacherange(void *startadr, int length)
218 {
219 /* CACHED_BOOTROM is mapped to the boot-rom area (cached) which
220 * we can use to get fast dummy-reads of cachelines
221 */
222
223 volatile short *flushadr = (volatile short *)(((unsigned long)startadr & ~PAGE_MASK) |
224 CACHED_BOOTROM);
225
226 length = length > 8192 ? 8192 : length; /* No need to flush more than cache size */
227
228 while(length > 0) {
229 *flushadr; /* dummy read to flush */
230 flushadr += (32/sizeof(short)); /* a cacheline is 32 bytes */
231 length -= 32;
232 }
233 }
234
235 /* Due to a bug in Etrax100(LX) all versions, receiving DMA buffers
236 * will occasionally corrupt certain CPU writes if the DMA buffers
237 * happen to be hot in the cache.
238 *
239 * As a workaround, we have to flush the relevant parts of the cache
240 * before (re) inserting any receiving descriptor into the DMA HW.
241 */
242
243 void
prepare_rx_descriptor(struct etrax_dma_descr * desc)244 prepare_rx_descriptor(struct etrax_dma_descr *desc)
245 {
246 flush_etrax_cacherange((void *)desc->buf, desc->sw_len ? desc->sw_len : 65536);
247 }
248
249 /* Do the same thing but flush the entire cache */
250
251 void
flush_etrax_cache(void)252 flush_etrax_cache(void)
253 {
254 flush_etrax_cacherange(0, 8192);
255 }
256