1 /* 2 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 3 * Author: Chanwoo Choi <cw00.choi@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * Device Tree binding constants for Samsung Exynos4415 clock controllers. 10 */ 11 12 #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H 13 #define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H 14 15 /* 16 * Let each exported clock get a unique index, which is used on DT-enabled 17 * platforms to lookup the clock from a clock specifier. These indices are 18 * therefore considered an ABI and so must not be changed. This implies 19 * that new clocks should be added either in free spaces between clock groups 20 * or at the end. 21 */ 22 23 /* 24 * Main CMU 25 */ 26 27 #define CLK_OSCSEL 1 28 #define CLK_FIN_PLL 2 29 #define CLK_FOUT_APLL 3 30 #define CLK_FOUT_MPLL 4 31 #define CLK_FOUT_EPLL 5 32 #define CLK_FOUT_G3D_PLL 6 33 #define CLK_FOUT_ISP_PLL 7 34 #define CLK_FOUT_DISP_PLL 8 35 36 /* Muxes */ 37 #define CLK_MOUT_MPLL_USER_L 16 38 #define CLK_MOUT_GDL 17 39 #define CLK_MOUT_MPLL_USER_R 18 40 #define CLK_MOUT_GDR 19 41 #define CLK_MOUT_EBI 20 42 #define CLK_MOUT_ACLK_200 21 43 #define CLK_MOUT_ACLK_160 22 44 #define CLK_MOUT_ACLK_100 23 45 #define CLK_MOUT_ACLK_266 24 46 #define CLK_MOUT_G3D_PLL 25 47 #define CLK_MOUT_EPLL 26 48 #define CLK_MOUT_EBI_1 27 49 #define CLK_MOUT_ISP_PLL 28 50 #define CLK_MOUT_DISP_PLL 29 51 #define CLK_MOUT_MPLL_USER_T 30 52 #define CLK_MOUT_ACLK_400_MCUISP 31 53 #define CLK_MOUT_G3D_PLLSRC 32 54 #define CLK_MOUT_CSIS1 33 55 #define CLK_MOUT_CSIS0 34 56 #define CLK_MOUT_CAM1 35 57 #define CLK_MOUT_FIMC3_LCLK 36 58 #define CLK_MOUT_FIMC2_LCLK 37 59 #define CLK_MOUT_FIMC1_LCLK 38 60 #define CLK_MOUT_FIMC0_LCLK 39 61 #define CLK_MOUT_MFC 40 62 #define CLK_MOUT_MFC_1 41 63 #define CLK_MOUT_MFC_0 42 64 #define CLK_MOUT_G3D 43 65 #define CLK_MOUT_G3D_1 44 66 #define CLK_MOUT_G3D_0 45 67 #define CLK_MOUT_MIPI0 46 68 #define CLK_MOUT_FIMD0 47 69 #define CLK_MOUT_TSADC_ISP 48 70 #define CLK_MOUT_UART_ISP 49 71 #define CLK_MOUT_SPI1_ISP 50 72 #define CLK_MOUT_SPI0_ISP 51 73 #define CLK_MOUT_PWM_ISP 52 74 #define CLK_MOUT_AUDIO0 53 75 #define CLK_MOUT_TSADC 54 76 #define CLK_MOUT_MMC2 55 77 #define CLK_MOUT_MMC1 56 78 #define CLK_MOUT_MMC0 57 79 #define CLK_MOUT_UART3 58 80 #define CLK_MOUT_UART2 59 81 #define CLK_MOUT_UART1 60 82 #define CLK_MOUT_UART0 61 83 #define CLK_MOUT_SPI2 62 84 #define CLK_MOUT_SPI1 63 85 #define CLK_MOUT_SPI0 64 86 #define CLK_MOUT_SPDIF 65 87 #define CLK_MOUT_AUDIO2 66 88 #define CLK_MOUT_AUDIO1 67 89 #define CLK_MOUT_MPLL_USER_C 68 90 #define CLK_MOUT_HPM 69 91 #define CLK_MOUT_CORE 70 92 #define CLK_MOUT_APLL 71 93 #define CLK_MOUT_PXLASYNC_CSIS1_FIMC 72 94 #define CLK_MOUT_PXLASYNC_CSIS0_FIMC 73 95 #define CLK_MOUT_JPEG 74 96 #define CLK_MOUT_JPEG1 75 97 #define CLK_MOUT_JPEG0 76 98 #define CLK_MOUT_ACLK_ISP0_300 77 99 #define CLK_MOUT_ACLK_ISP0_400 78 100 #define CLK_MOUT_ACLK_ISP0_300_USER 79 101 #define CLK_MOUT_ACLK_ISP1_300 80 102 #define CLK_MOUT_ACLK_ISP1_300_USER 81 103 #define CLK_MOUT_HDMI 82 104 105 /* Dividers */ 106 #define CLK_DIV_GPL 90 107 #define CLK_DIV_GDL 91 108 #define CLK_DIV_GPR 92 109 #define CLK_DIV_GDR 93 110 #define CLK_DIV_ACLK_400_MCUISP 94 111 #define CLK_DIV_EBI 95 112 #define CLK_DIV_ACLK_200 96 113 #define CLK_DIV_ACLK_160 97 114 #define CLK_DIV_ACLK_100 98 115 #define CLK_DIV_ACLK_266 99 116 #define CLK_DIV_CSIS1 100 117 #define CLK_DIV_CSIS0 101 118 #define CLK_DIV_CAM1 102 119 #define CLK_DIV_FIMC3_LCLK 103 120 #define CLK_DIV_FIMC2_LCLK 104 121 #define CLK_DIV_FIMC1_LCLK 105 122 #define CLK_DIV_FIMC0_LCLK 106 123 #define CLK_DIV_TV_BLK 107 124 #define CLK_DIV_MFC 108 125 #define CLK_DIV_G3D 109 126 #define CLK_DIV_MIPI0_PRE 110 127 #define CLK_DIV_MIPI0 111 128 #define CLK_DIV_FIMD0 112 129 #define CLK_DIV_UART_ISP 113 130 #define CLK_DIV_SPI1_ISP_PRE 114 131 #define CLK_DIV_SPI1_ISP 115 132 #define CLK_DIV_SPI0_ISP_PRE 116 133 #define CLK_DIV_SPI0_ISP 117 134 #define CLK_DIV_PWM_ISP 118 135 #define CLK_DIV_PCM0 119 136 #define CLK_DIV_AUDIO0 120 137 #define CLK_DIV_TSADC_PRE 121 138 #define CLK_DIV_TSADC 122 139 #define CLK_DIV_MMC1_PRE 123 140 #define CLK_DIV_MMC1 124 141 #define CLK_DIV_MMC0_PRE 125 142 #define CLK_DIV_MMC0 126 143 #define CLK_DIV_MMC2_PRE 127 144 #define CLK_DIV_MMC2 128 145 #define CLK_DIV_UART3 129 146 #define CLK_DIV_UART2 130 147 #define CLK_DIV_UART1 131 148 #define CLK_DIV_UART0 132 149 #define CLK_DIV_SPI1_PRE 133 150 #define CLK_DIV_SPI1 134 151 #define CLK_DIV_SPI0_PRE 135 152 #define CLK_DIV_SPI0 136 153 #define CLK_DIV_SPI2_PRE 137 154 #define CLK_DIV_SPI2 138 155 #define CLK_DIV_PCM2 139 156 #define CLK_DIV_AUDIO2 140 157 #define CLK_DIV_PCM1 141 158 #define CLK_DIV_AUDIO1 142 159 #define CLK_DIV_I2S1 143 160 #define CLK_DIV_PXLASYNC_CSIS1_FIMC 144 161 #define CLK_DIV_PXLASYNC_CSIS0_FIMC 145 162 #define CLK_DIV_JPEG 146 163 #define CLK_DIV_CORE2 147 164 #define CLK_DIV_APLL 148 165 #define CLK_DIV_PCLK_DBG 149 166 #define CLK_DIV_ATB 150 167 #define CLK_DIV_PERIPH 151 168 #define CLK_DIV_COREM1 152 169 #define CLK_DIV_COREM0 153 170 #define CLK_DIV_CORE 154 171 #define CLK_DIV_HPM 155 172 #define CLK_DIV_COPY 156 173 174 /* Gates */ 175 #define CLK_ASYNC_G3D 180 176 #define CLK_ASYNC_MFCL 181 177 #define CLK_ASYNC_TVX 182 178 #define CLK_PPMULEFT 183 179 #define CLK_GPIO_LEFT 184 180 #define CLK_PPMUIMAGE 185 181 #define CLK_QEMDMA2 186 182 #define CLK_QEROTATOR 187 183 #define CLK_SMMUMDMA2 188 184 #define CLK_SMMUROTATOR 189 185 #define CLK_MDMA2 190 186 #define CLK_ROTATOR 191 187 #define CLK_ASYNC_ISPMX 192 188 #define CLK_ASYNC_MAUDIOX 193 189 #define CLK_ASYNC_MFCR 194 190 #define CLK_ASYNC_FSYSD 195 191 #define CLK_ASYNC_LCD0X 196 192 #define CLK_ASYNC_CAMX 197 193 #define CLK_PPMURIGHT 198 194 #define CLK_GPIO_RIGHT 199 195 #define CLK_ANTIRBK_APBIF 200 196 #define CLK_EFUSE_WRITER_APBIF 201 197 #define CLK_MONOCNT 202 198 #define CLK_TZPC6 203 199 #define CLK_PROVISIONKEY1 204 200 #define CLK_PROVISIONKEY0 205 201 #define CLK_CMU_ISPPART 206 202 #define CLK_TMU_APBIF 207 203 #define CLK_KEYIF 208 204 #define CLK_RTC 209 205 #define CLK_WDT 210 206 #define CLK_MCT 211 207 #define CLK_SECKEY 212 208 #define CLK_HDMI_CEC 213 209 #define CLK_TZPC5 214 210 #define CLK_TZPC4 215 211 #define CLK_TZPC3 216 212 #define CLK_TZPC2 217 213 #define CLK_TZPC1 218 214 #define CLK_TZPC0 219 215 #define CLK_CMU_COREPART 220 216 #define CLK_CMU_TOPPART 221 217 #define CLK_PMU_APBIF 222 218 #define CLK_SYSREG 223 219 #define CLK_CHIP_ID 224 220 #define CLK_SMMUFIMC_LITE2 225 221 #define CLK_FIMC_LITE2 226 222 #define CLK_PIXELASYNCM1 227 223 #define CLK_PIXELASYNCM0 228 224 #define CLK_PPMUCAMIF 229 225 #define CLK_SMMUJPEG 230 226 #define CLK_SMMUFIMC3 231 227 #define CLK_SMMUFIMC2 232 228 #define CLK_SMMUFIMC1 233 229 #define CLK_SMMUFIMC0 234 230 #define CLK_JPEG 235 231 #define CLK_CSIS1 236 232 #define CLK_CSIS0 237 233 #define CLK_FIMC3 238 234 #define CLK_FIMC2 239 235 #define CLK_FIMC1 240 236 #define CLK_FIMC0 241 237 #define CLK_PPMUTV 242 238 #define CLK_SMMUTV 243 239 #define CLK_HDMI 244 240 #define CLK_MIXER 245 241 #define CLK_VP 246 242 #define CLK_PPMUMFC_R 247 243 #define CLK_PPMUMFC_L 248 244 #define CLK_SMMUMFC_R 249 245 #define CLK_SMMUMFC_L 250 246 #define CLK_MFC 251 247 #define CLK_PPMUG3D 252 248 #define CLK_G3D 253 249 #define CLK_PPMULCD0 254 250 #define CLK_SMMUFIMD0 255 251 #define CLK_DSIM0 256 252 #define CLK_SMIES 257 253 #define CLK_MIE0 258 254 #define CLK_FIMD0 259 255 #define CLK_TSADC 260 256 #define CLK_PPMUFILE 261 257 #define CLK_NFCON 262 258 #define CLK_USBDEVICE 263 259 #define CLK_USBHOST 264 260 #define CLK_SROMC 265 261 #define CLK_SDMMC2 266 262 #define CLK_SDMMC1 267 263 #define CLK_SDMMC0 268 264 #define CLK_PDMA1 269 265 #define CLK_PDMA0 270 266 #define CLK_SPDIF 271 267 #define CLK_PWM 272 268 #define CLK_PCM2 273 269 #define CLK_PCM1 274 270 #define CLK_I2S1 275 271 #define CLK_SPI2 276 272 #define CLK_SPI1 277 273 #define CLK_SPI0 278 274 #define CLK_I2CHDMI 279 275 #define CLK_I2C7 280 276 #define CLK_I2C6 281 277 #define CLK_I2C5 282 278 #define CLK_I2C4 283 279 #define CLK_I2C3 284 280 #define CLK_I2C2 285 281 #define CLK_I2C1 286 282 #define CLK_I2C0 287 283 #define CLK_UART3 288 284 #define CLK_UART2 289 285 #define CLK_UART1 290 286 #define CLK_UART0 291 287 288 /* Special clocks */ 289 #define CLK_SCLK_PXLAYSNC_CSIS1_FIMC 330 290 #define CLK_SCLK_PXLAYSNC_CSIS0_FIMC 331 291 #define CLK_SCLK_JPEG 332 292 #define CLK_SCLK_CSIS1 333 293 #define CLK_SCLK_CSIS0 334 294 #define CLK_SCLK_CAM1 335 295 #define CLK_SCLK_FIMC3_LCLK 336 296 #define CLK_SCLK_FIMC2_LCLK 337 297 #define CLK_SCLK_FIMC1_LCLK 338 298 #define CLK_SCLK_FIMC0_LCLK 339 299 #define CLK_SCLK_PIXEL 340 300 #define CLK_SCLK_HDMI 341 301 #define CLK_SCLK_MIXER 342 302 #define CLK_SCLK_MFC 343 303 #define CLK_SCLK_G3D 344 304 #define CLK_SCLK_MIPIDPHY4L 345 305 #define CLK_SCLK_MIPI0 346 306 #define CLK_SCLK_MDNIE0 347 307 #define CLK_SCLK_FIMD0 348 308 #define CLK_SCLK_PCM0 349 309 #define CLK_SCLK_AUDIO0 350 310 #define CLK_SCLK_TSADC 351 311 #define CLK_SCLK_EBI 352 312 #define CLK_SCLK_MMC2 353 313 #define CLK_SCLK_MMC1 354 314 #define CLK_SCLK_MMC0 355 315 #define CLK_SCLK_I2S 356 316 #define CLK_SCLK_PCM2 357 317 #define CLK_SCLK_PCM1 358 318 #define CLK_SCLK_AUDIO2 359 319 #define CLK_SCLK_AUDIO1 360 320 #define CLK_SCLK_SPDIF 361 321 #define CLK_SCLK_SPI2 362 322 #define CLK_SCLK_SPI1 363 323 #define CLK_SCLK_SPI0 364 324 #define CLK_SCLK_UART3 365 325 #define CLK_SCLK_UART2 366 326 #define CLK_SCLK_UART1 367 327 #define CLK_SCLK_UART0 368 328 #define CLK_SCLK_HDMIPHY 369 329 330 /* 331 * Total number of clocks of main CMU. 332 * NOTE: Must be equal to last clock ID increased by one. 333 */ 334 #define CLK_NR_CLKS 370 335 336 /* 337 * CMU DMC 338 */ 339 #define CLK_DMC_FOUT_MPLL 1 340 #define CLK_DMC_FOUT_BPLL 2 341 342 #define CLK_DMC_MOUT_MPLL 3 343 #define CLK_DMC_MOUT_BPLL 4 344 #define CLK_DMC_MOUT_DPHY 5 345 #define CLK_DMC_MOUT_DMC_BUS 6 346 347 #define CLK_DMC_DIV_DMC 7 348 #define CLK_DMC_DIV_DPHY 8 349 #define CLK_DMC_DIV_DMC_PRE 9 350 #define CLK_DMC_DIV_DMCP 10 351 #define CLK_DMC_DIV_DMCD 11 352 #define CLK_DMC_DIV_MPLL_PRE 12 353 354 /* 355 * Total number of clocks of CMU_DMC. 356 * NOTE: Must be equal to highest clock ID increased by one. 357 */ 358 #define NR_CLKS_DMC 13 359 360 #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H */ 361