1 /* 2 * This header provides clock numbers for the ingenic,jz4780-cgu DT binding. 3 * 4 * They are roughly ordered as: 5 * - external clocks 6 * - PLLs 7 * - muxes/dividers in the order they appear in the jz4780 programmers manual 8 * - gates in order of their bit in the CLKGR* registers 9 */ 10 11 #ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ 12 #define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ 13 14 #define JZ4780_CLK_EXCLK 0 15 #define JZ4780_CLK_RTCLK 1 16 #define JZ4780_CLK_APLL 2 17 #define JZ4780_CLK_MPLL 3 18 #define JZ4780_CLK_EPLL 4 19 #define JZ4780_CLK_VPLL 5 20 #define JZ4780_CLK_OTGPHY 6 21 #define JZ4780_CLK_SCLKA 7 22 #define JZ4780_CLK_CPUMUX 8 23 #define JZ4780_CLK_CPU 9 24 #define JZ4780_CLK_L2CACHE 10 25 #define JZ4780_CLK_AHB0 11 26 #define JZ4780_CLK_AHB2PMUX 12 27 #define JZ4780_CLK_AHB2 13 28 #define JZ4780_CLK_PCLK 14 29 #define JZ4780_CLK_DDR 15 30 #define JZ4780_CLK_VPU 16 31 #define JZ4780_CLK_I2SPLL 17 32 #define JZ4780_CLK_I2S 18 33 #define JZ4780_CLK_LCD0PIXCLK 19 34 #define JZ4780_CLK_LCD1PIXCLK 20 35 #define JZ4780_CLK_MSCMUX 21 36 #define JZ4780_CLK_MSC0 22 37 #define JZ4780_CLK_MSC1 23 38 #define JZ4780_CLK_MSC2 24 39 #define JZ4780_CLK_UHC 25 40 #define JZ4780_CLK_SSIPLL 26 41 #define JZ4780_CLK_SSI 27 42 #define JZ4780_CLK_CIMMCLK 28 43 #define JZ4780_CLK_PCMPLL 29 44 #define JZ4780_CLK_PCM 30 45 #define JZ4780_CLK_GPU 31 46 #define JZ4780_CLK_HDMI 32 47 #define JZ4780_CLK_BCH 33 48 #define JZ4780_CLK_NEMC 34 49 #define JZ4780_CLK_OTG0 35 50 #define JZ4780_CLK_SSI0 36 51 #define JZ4780_CLK_SMB0 37 52 #define JZ4780_CLK_SMB1 38 53 #define JZ4780_CLK_SCC 39 54 #define JZ4780_CLK_AIC 40 55 #define JZ4780_CLK_TSSI0 41 56 #define JZ4780_CLK_OWI 42 57 #define JZ4780_CLK_KBC 43 58 #define JZ4780_CLK_SADC 44 59 #define JZ4780_CLK_UART0 45 60 #define JZ4780_CLK_UART1 46 61 #define JZ4780_CLK_UART2 47 62 #define JZ4780_CLK_UART3 48 63 #define JZ4780_CLK_SSI1 49 64 #define JZ4780_CLK_SSI2 50 65 #define JZ4780_CLK_PDMA 51 66 #define JZ4780_CLK_GPS 52 67 #define JZ4780_CLK_MAC 53 68 #define JZ4780_CLK_SMB2 54 69 #define JZ4780_CLK_CIM 55 70 #define JZ4780_CLK_LCD 56 71 #define JZ4780_CLK_TVE 57 72 #define JZ4780_CLK_IPU 58 73 #define JZ4780_CLK_DDR0 59 74 #define JZ4780_CLK_DDR1 60 75 #define JZ4780_CLK_SMB3 61 76 #define JZ4780_CLK_TSSI1 62 77 #define JZ4780_CLK_COMPRESS 63 78 #define JZ4780_CLK_AIC1 64 79 #define JZ4780_CLK_GPVLC 65 80 #define JZ4780_CLK_OTG1 66 81 #define JZ4780_CLK_UART4 67 82 #define JZ4780_CLK_AHBMON 68 83 #define JZ4780_CLK_SMB4 69 84 #define JZ4780_CLK_DES 70 85 #define JZ4780_CLK_X2D 71 86 #define JZ4780_CLK_CORE1 72 87 88 #endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */ 89