1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
7 */
8 #include <linux/cpu.h>
9 #include <linux/delay.h>
10 #include <linux/smp.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/sched.h>
14 #include <linux/module.h>
15
16 #include <asm/mmu_context.h>
17 #include <asm/time.h>
18 #include <asm/setup.h>
19
20 #include <asm/octeon/octeon.h>
21
22 #include "octeon_boot.h"
23
24 volatile unsigned long octeon_processor_boot = 0xff;
25 volatile unsigned long octeon_processor_sp;
26 volatile unsigned long octeon_processor_gp;
27
28 #ifdef CONFIG_HOTPLUG_CPU
29 uint64_t octeon_bootloader_entry_addr;
30 EXPORT_SYMBOL(octeon_bootloader_entry_addr);
31 #endif
32
octeon_icache_flush(void)33 static void octeon_icache_flush(void)
34 {
35 asm volatile ("synci 0($0)\n");
36 }
37
38 static void (*octeon_message_functions[8])(void) = {
39 scheduler_ipi,
40 generic_smp_call_function_interrupt,
41 octeon_icache_flush,
42 };
43
mailbox_interrupt(int irq,void * dev_id)44 static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
45 {
46 u64 mbox_clrx = CVMX_CIU_MBOX_CLRX(cvmx_get_core_num());
47 u64 action;
48 int i;
49
50 /*
51 * Make sure the function array initialization remains
52 * correct.
53 */
54 BUILD_BUG_ON(SMP_RESCHEDULE_YOURSELF != (1 << 0));
55 BUILD_BUG_ON(SMP_CALL_FUNCTION != (1 << 1));
56 BUILD_BUG_ON(SMP_ICACHE_FLUSH != (1 << 2));
57
58 /*
59 * Load the mailbox register to figure out what we're supposed
60 * to do.
61 */
62 action = cvmx_read_csr(mbox_clrx);
63
64 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
65 action &= 0xff;
66 else
67 action &= 0xffff;
68
69 /* Clear the mailbox to clear the interrupt */
70 cvmx_write_csr(mbox_clrx, action);
71
72 for (i = 0; i < ARRAY_SIZE(octeon_message_functions) && action;) {
73 if (action & 1) {
74 void (*fn)(void) = octeon_message_functions[i];
75
76 if (fn)
77 fn();
78 }
79 action >>= 1;
80 i++;
81 }
82 return IRQ_HANDLED;
83 }
84
85 /**
86 * Cause the function described by call_data to be executed on the passed
87 * cpu. When the function has finished, increment the finished field of
88 * call_data.
89 */
octeon_send_ipi_single(int cpu,unsigned int action)90 void octeon_send_ipi_single(int cpu, unsigned int action)
91 {
92 int coreid = cpu_logical_map(cpu);
93 /*
94 pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
95 coreid, action);
96 */
97 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
98 }
99
octeon_send_ipi_mask(const struct cpumask * mask,unsigned int action)100 static inline void octeon_send_ipi_mask(const struct cpumask *mask,
101 unsigned int action)
102 {
103 unsigned int i;
104
105 for_each_cpu(i, mask)
106 octeon_send_ipi_single(i, action);
107 }
108
109 /**
110 * Detect available CPUs, populate cpu_possible_mask
111 */
octeon_smp_hotplug_setup(void)112 static void octeon_smp_hotplug_setup(void)
113 {
114 #ifdef CONFIG_HOTPLUG_CPU
115 struct linux_app_boot_info *labi;
116
117 if (!setup_max_cpus)
118 return;
119
120 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
121 if (labi->labi_signature != LABI_SIGNATURE) {
122 pr_info("The bootloader on this board does not support HOTPLUG_CPU.");
123 return;
124 }
125
126 octeon_bootloader_entry_addr = labi->InitTLBStart_addr;
127 #endif
128 }
129
octeon_smp_setup(void)130 static void __init octeon_smp_setup(void)
131 {
132 const int coreid = cvmx_get_core_num();
133 int cpus;
134 int id;
135 struct cvmx_sysinfo *sysinfo = cvmx_sysinfo_get();
136
137 #ifdef CONFIG_HOTPLUG_CPU
138 int core_mask = octeon_get_boot_coremask();
139 unsigned int num_cores = cvmx_octeon_num_cores();
140 #endif
141
142 /* The present CPUs are initially just the boot cpu (CPU 0). */
143 for (id = 0; id < NR_CPUS; id++) {
144 set_cpu_possible(id, id == 0);
145 set_cpu_present(id, id == 0);
146 }
147
148 __cpu_number_map[coreid] = 0;
149 __cpu_logical_map[0] = coreid;
150
151 /* The present CPUs get the lowest CPU numbers. */
152 cpus = 1;
153 for (id = 0; id < NR_CPUS; id++) {
154 if ((id != coreid) && cvmx_coremask_is_core_set(&sysinfo->core_mask, id)) {
155 set_cpu_possible(cpus, true);
156 set_cpu_present(cpus, true);
157 __cpu_number_map[id] = cpus;
158 __cpu_logical_map[cpus] = id;
159 cpus++;
160 }
161 }
162
163 #ifdef CONFIG_HOTPLUG_CPU
164 /*
165 * The possible CPUs are all those present on the chip. We
166 * will assign CPU numbers for possible cores as well. Cores
167 * are always consecutively numberd from 0.
168 */
169 for (id = 0; setup_max_cpus && octeon_bootloader_entry_addr &&
170 id < num_cores && id < NR_CPUS; id++) {
171 if (!(core_mask & (1 << id))) {
172 set_cpu_possible(cpus, true);
173 __cpu_number_map[id] = cpus;
174 __cpu_logical_map[cpus] = id;
175 cpus++;
176 }
177 }
178 #endif
179
180 octeon_smp_hotplug_setup();
181 }
182
183 /**
184 * Firmware CPU startup hook
185 *
186 */
octeon_boot_secondary(int cpu,struct task_struct * idle)187 static void octeon_boot_secondary(int cpu, struct task_struct *idle)
188 {
189 int count;
190
191 pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
192 cpu_logical_map(cpu));
193
194 octeon_processor_sp = __KSTK_TOS(idle);
195 octeon_processor_gp = (unsigned long)(task_thread_info(idle));
196 octeon_processor_boot = cpu_logical_map(cpu);
197 mb();
198
199 count = 10000;
200 while (octeon_processor_sp && count) {
201 /* Waiting for processor to get the SP and GP */
202 udelay(1);
203 count--;
204 }
205 if (count == 0)
206 pr_err("Secondary boot timeout\n");
207 }
208
209 /**
210 * After we've done initial boot, this function is called to allow the
211 * board code to clean up state, if needed
212 */
octeon_init_secondary(void)213 static void octeon_init_secondary(void)
214 {
215 unsigned int sr;
216
217 sr = set_c0_status(ST0_BEV);
218 write_c0_ebase((u32)ebase);
219 write_c0_status(sr);
220
221 octeon_check_cpu_bist();
222 octeon_init_cvmcount();
223
224 octeon_irq_setup_secondary();
225 }
226
227 /**
228 * Callout to firmware before smp_init
229 *
230 */
octeon_prepare_cpus(unsigned int max_cpus)231 static void __init octeon_prepare_cpus(unsigned int max_cpus)
232 {
233 /*
234 * Only the low order mailbox bits are used for IPIs, leave
235 * the other bits alone.
236 */
237 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffff);
238 if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt,
239 IRQF_PERCPU | IRQF_NO_THREAD, "SMP-IPI",
240 mailbox_interrupt)) {
241 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)");
242 }
243 }
244
245 /**
246 * Last chance for the board code to finish SMP initialization before
247 * the CPU is "online".
248 */
octeon_smp_finish(void)249 static void octeon_smp_finish(void)
250 {
251 octeon_user_io_init();
252
253 /* to generate the first CPU timer interrupt */
254 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
255 local_irq_enable();
256 }
257
258 #ifdef CONFIG_HOTPLUG_CPU
259
260 /* State of each CPU. */
261 DEFINE_PER_CPU(int, cpu_state);
262
octeon_cpu_disable(void)263 static int octeon_cpu_disable(void)
264 {
265 unsigned int cpu = smp_processor_id();
266
267 if (cpu == 0)
268 return -EBUSY;
269
270 if (!octeon_bootloader_entry_addr)
271 return -ENOTSUPP;
272
273 set_cpu_online(cpu, false);
274 calculate_cpu_foreign_map();
275 cpumask_clear_cpu(cpu, &cpu_callin_map);
276 octeon_fixup_irqs();
277
278 __flush_cache_all();
279 local_flush_tlb_all();
280
281 return 0;
282 }
283
octeon_cpu_die(unsigned int cpu)284 static void octeon_cpu_die(unsigned int cpu)
285 {
286 int coreid = cpu_logical_map(cpu);
287 uint32_t mask, new_mask;
288 const struct cvmx_bootmem_named_block_desc *block_desc;
289
290 while (per_cpu(cpu_state, cpu) != CPU_DEAD)
291 cpu_relax();
292
293 /*
294 * This is a bit complicated strategics of getting/settig available
295 * cores mask, copied from bootloader
296 */
297
298 mask = 1 << coreid;
299 /* LINUX_APP_BOOT_BLOCK is initialized in bootoct binary */
300 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
301
302 if (!block_desc) {
303 struct linux_app_boot_info *labi;
304
305 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
306
307 labi->avail_coremask |= mask;
308 new_mask = labi->avail_coremask;
309 } else { /* alternative, already initialized */
310 uint32_t *p = (uint32_t *)PHYS_TO_XKSEG_CACHED(block_desc->base_addr +
311 AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
312 *p |= mask;
313 new_mask = *p;
314 }
315
316 pr_info("Reset core %d. Available Coremask = 0x%x \n", coreid, new_mask);
317 mb();
318 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
319 cvmx_write_csr(CVMX_CIU_PP_RST, 0);
320 }
321
play_dead(void)322 void play_dead(void)
323 {
324 int cpu = cpu_number_map(cvmx_get_core_num());
325
326 idle_task_exit();
327 octeon_processor_boot = 0xff;
328 per_cpu(cpu_state, cpu) = CPU_DEAD;
329
330 mb();
331
332 while (1) /* core will be reset here */
333 ;
334 }
335
336 extern void kernel_entry(unsigned long arg1, ...);
337
start_after_reset(void)338 static void start_after_reset(void)
339 {
340 kernel_entry(0, 0, 0); /* set a2 = 0 for secondary core */
341 }
342
octeon_update_boot_vector(unsigned int cpu)343 static int octeon_update_boot_vector(unsigned int cpu)
344 {
345
346 int coreid = cpu_logical_map(cpu);
347 uint32_t avail_coremask;
348 const struct cvmx_bootmem_named_block_desc *block_desc;
349 struct boot_init_vector *boot_vect =
350 (struct boot_init_vector *)PHYS_TO_XKSEG_CACHED(BOOTLOADER_BOOT_VECTOR);
351
352 block_desc = cvmx_bootmem_find_named_block(LINUX_APP_BOOT_BLOCK_NAME);
353
354 if (!block_desc) {
355 struct linux_app_boot_info *labi;
356
357 labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
358
359 avail_coremask = labi->avail_coremask;
360 labi->avail_coremask &= ~(1 << coreid);
361 } else { /* alternative, already initialized */
362 avail_coremask = *(uint32_t *)PHYS_TO_XKSEG_CACHED(
363 block_desc->base_addr + AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK);
364 }
365
366 if (!(avail_coremask & (1 << coreid))) {
367 /* core not available, assume, that caught by simple-executive */
368 cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
369 cvmx_write_csr(CVMX_CIU_PP_RST, 0);
370 }
371
372 boot_vect[coreid].app_start_func_addr =
373 (uint32_t) (unsigned long) start_after_reset;
374 boot_vect[coreid].code_addr = octeon_bootloader_entry_addr;
375
376 mb();
377
378 cvmx_write_csr(CVMX_CIU_NMI, (1 << coreid) & avail_coremask);
379
380 return 0;
381 }
382
register_cavium_notifier(void)383 static int register_cavium_notifier(void)
384 {
385 return cpuhp_setup_state_nocalls(CPUHP_MIPS_SOC_PREPARE,
386 "mips/cavium:prepare",
387 octeon_update_boot_vector, NULL);
388 }
389 late_initcall(register_cavium_notifier);
390
391 #endif /* CONFIG_HOTPLUG_CPU */
392
393 struct plat_smp_ops octeon_smp_ops = {
394 .send_ipi_single = octeon_send_ipi_single,
395 .send_ipi_mask = octeon_send_ipi_mask,
396 .init_secondary = octeon_init_secondary,
397 .smp_finish = octeon_smp_finish,
398 .boot_secondary = octeon_boot_secondary,
399 .smp_setup = octeon_smp_setup,
400 .prepare_cpus = octeon_prepare_cpus,
401 #ifdef CONFIG_HOTPLUG_CPU
402 .cpu_disable = octeon_cpu_disable,
403 .cpu_die = octeon_cpu_die,
404 #endif
405 };
406
octeon_78xx_reched_interrupt(int irq,void * dev_id)407 static irqreturn_t octeon_78xx_reched_interrupt(int irq, void *dev_id)
408 {
409 scheduler_ipi();
410 return IRQ_HANDLED;
411 }
412
octeon_78xx_call_function_interrupt(int irq,void * dev_id)413 static irqreturn_t octeon_78xx_call_function_interrupt(int irq, void *dev_id)
414 {
415 generic_smp_call_function_interrupt();
416 return IRQ_HANDLED;
417 }
418
octeon_78xx_icache_flush_interrupt(int irq,void * dev_id)419 static irqreturn_t octeon_78xx_icache_flush_interrupt(int irq, void *dev_id)
420 {
421 octeon_icache_flush();
422 return IRQ_HANDLED;
423 }
424
425 /*
426 * Callout to firmware before smp_init
427 */
octeon_78xx_prepare_cpus(unsigned int max_cpus)428 static void octeon_78xx_prepare_cpus(unsigned int max_cpus)
429 {
430 if (request_irq(OCTEON_IRQ_MBOX0 + 0,
431 octeon_78xx_reched_interrupt,
432 IRQF_PERCPU | IRQF_NO_THREAD, "Scheduler",
433 octeon_78xx_reched_interrupt)) {
434 panic("Cannot request_irq for SchedulerIPI");
435 }
436 if (request_irq(OCTEON_IRQ_MBOX0 + 1,
437 octeon_78xx_call_function_interrupt,
438 IRQF_PERCPU | IRQF_NO_THREAD, "SMP-Call",
439 octeon_78xx_call_function_interrupt)) {
440 panic("Cannot request_irq for SMP-Call");
441 }
442 if (request_irq(OCTEON_IRQ_MBOX0 + 2,
443 octeon_78xx_icache_flush_interrupt,
444 IRQF_PERCPU | IRQF_NO_THREAD, "ICache-Flush",
445 octeon_78xx_icache_flush_interrupt)) {
446 panic("Cannot request_irq for ICache-Flush");
447 }
448 }
449
octeon_78xx_send_ipi_single(int cpu,unsigned int action)450 static void octeon_78xx_send_ipi_single(int cpu, unsigned int action)
451 {
452 int i;
453
454 for (i = 0; i < 8; i++) {
455 if (action & 1)
456 octeon_ciu3_mbox_send(cpu, i);
457 action >>= 1;
458 }
459 }
460
octeon_78xx_send_ipi_mask(const struct cpumask * mask,unsigned int action)461 static void octeon_78xx_send_ipi_mask(const struct cpumask *mask,
462 unsigned int action)
463 {
464 unsigned int cpu;
465
466 for_each_cpu(cpu, mask)
467 octeon_78xx_send_ipi_single(cpu, action);
468 }
469
470 static struct plat_smp_ops octeon_78xx_smp_ops = {
471 .send_ipi_single = octeon_78xx_send_ipi_single,
472 .send_ipi_mask = octeon_78xx_send_ipi_mask,
473 .init_secondary = octeon_init_secondary,
474 .smp_finish = octeon_smp_finish,
475 .boot_secondary = octeon_boot_secondary,
476 .smp_setup = octeon_smp_setup,
477 .prepare_cpus = octeon_78xx_prepare_cpus,
478 #ifdef CONFIG_HOTPLUG_CPU
479 .cpu_disable = octeon_cpu_disable,
480 .cpu_die = octeon_cpu_die,
481 #endif
482 };
483
octeon_setup_smp(void)484 void __init octeon_setup_smp(void)
485 {
486 struct plat_smp_ops *ops;
487
488 if (octeon_has_feature(OCTEON_FEATURE_CIU3))
489 ops = &octeon_78xx_smp_ops;
490 else
491 ops = &octeon_smp_ops;
492
493 register_smp_ops(ops);
494 }
495