1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
7 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
8 */
9 #ifndef _ASM_PGTABLE_32_H
10 #define _ASM_PGTABLE_32_H
11
12 #include <asm/addrspace.h>
13 #include <asm/page.h>
14
15 #include <linux/linkage.h>
16 #include <asm/cachectl.h>
17 #include <asm/fixmap.h>
18
19 #include <asm-generic/pgtable-nopmd.h>
20
21 #ifdef CONFIG_HIGHMEM
22 #include <asm/highmem.h>
23 #endif
24
25 extern int temp_tlb_entry;
26
27 /*
28 * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
29 * starting at the top and working down. This is for populating the
30 * TLB before trap_init() puts the TLB miss handler in place. It
31 * should be used only for entries matching the actual page tables,
32 * to prevent inconsistencies.
33 */
34 extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
35 unsigned long entryhi, unsigned long pagemask);
36
37 /*
38 * Basically we have the same two-level (which is the logical three level
39 * Linux page table layout folded) page tables as the i386. Some day
40 * when we have proper page coloring support we can have a 1% quicker
41 * tlb refill handling mechanism, but for now it is a bit slower but
42 * works even with the cache aliasing problem the R4k and above have.
43 */
44
45 /* PGDIR_SHIFT determines what a third-level page table entry can map */
46 #define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
47 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
48 #define PGDIR_MASK (~(PGDIR_SIZE-1))
49
50 /*
51 * Entries per page directory level: we use two-level, so
52 * we don't really have any PUD/PMD directory physically.
53 */
54 #define __PGD_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
55 #define PGD_ORDER (__PGD_ORDER >= 0 ? __PGD_ORDER : 0)
56 #define PUD_ORDER aieeee_attempt_to_allocate_pud
57 #define PMD_ORDER 1
58 #define PTE_ORDER 0
59
60 #define PTRS_PER_PGD (USER_PTRS_PER_PGD * 2)
61 #define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
62
63 #define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
64 #define FIRST_USER_ADDRESS 0UL
65
66 #define VMALLOC_START MAP_BASE
67
68 #define PKMAP_END ((FIXADDR_START) & ~((LAST_PKMAP << PAGE_SHIFT)-1))
69 #define PKMAP_BASE (PKMAP_END - PAGE_SIZE * LAST_PKMAP)
70
71 #ifdef CONFIG_HIGHMEM
72 # define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
73 #else
74 # define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
75 #endif
76
77 #ifdef CONFIG_PHYS_ADDR_T_64BIT
78 #define pte_ERROR(e) \
79 printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
80 #else
81 #define pte_ERROR(e) \
82 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
83 #endif
84 #define pgd_ERROR(e) \
85 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
86
87 extern void load_pgd(unsigned long pg_dir);
88
89 extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
90
91 /*
92 * Empty pgd/pmd entries point to the invalid_pte_table.
93 */
pmd_none(pmd_t pmd)94 static inline int pmd_none(pmd_t pmd)
95 {
96 return pmd_val(pmd) == (unsigned long) invalid_pte_table;
97 }
98
99 #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
100
pmd_present(pmd_t pmd)101 static inline int pmd_present(pmd_t pmd)
102 {
103 return pmd_val(pmd) != (unsigned long) invalid_pte_table;
104 }
105
pmd_clear(pmd_t * pmdp)106 static inline void pmd_clear(pmd_t *pmdp)
107 {
108 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
109 }
110
111 #if defined(CONFIG_XPA)
112
113 #define pte_pfn(x) (((unsigned long)((x).pte_high >> _PFN_SHIFT)) | (unsigned long)((x).pte_low << _PAGE_PRESENT_SHIFT))
114 static inline pte_t
pfn_pte(unsigned long pfn,pgprot_t prot)115 pfn_pte(unsigned long pfn, pgprot_t prot)
116 {
117 pte_t pte;
118
119 pte.pte_low = (pfn >> _PAGE_PRESENT_SHIFT) |
120 (pgprot_val(prot) & ~_PFNX_MASK);
121 pte.pte_high = (pfn << _PFN_SHIFT) |
122 (pgprot_val(prot) & ~_PFN_MASK);
123 return pte;
124 }
125
126 #elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
127
128 #define pte_pfn(x) ((unsigned long)((x).pte_high >> 6))
129
pfn_pte(unsigned long pfn,pgprot_t prot)130 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
131 {
132 pte_t pte;
133
134 pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
135 pte.pte_low = pgprot_val(prot);
136
137 return pte;
138 }
139
140 #else
141
142 #ifdef CONFIG_CPU_VR41XX
143 #define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
144 #define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
145 #else
146 #define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT))
147 #define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))
148 #endif
149 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
150
151 #define pte_page(x) pfn_to_page(pte_pfn(x))
152
153 #define __pgd_offset(address) pgd_index(address)
154 #define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
155 #define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
156
157 /* to find an entry in a kernel page-table-directory */
158 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
159
160 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
161
162 /* to find an entry in a page-table-directory */
163 #define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
164
165 /* Find an entry in the third-level page table.. */
166 #define __pte_offset(address) \
167 (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
168 #define pte_offset(dir, address) \
169 ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
170 #define pte_offset_kernel(dir, address) \
171 ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
172
173 #define pte_offset_map(dir, address) \
174 ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
175 #define pte_unmap(pte) ((void)(pte))
176
177 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
178
179 /* Swap entries must have VALID bit cleared. */
180 #define __swp_type(x) (((x).val >> 10) & 0x1f)
181 #define __swp_offset(x) ((x).val >> 15)
182 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
183 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
184 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
185
186 #else
187
188 #if defined(CONFIG_XPA)
189
190 /* Swap entries must have VALID and GLOBAL bits cleared. */
191 #define __swp_type(x) (((x).val >> 4) & 0x1f)
192 #define __swp_offset(x) ((x).val >> 9)
193 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 4) | ((offset) << 9) })
194 #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
195 #define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
196
197 #elif defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
198
199 /* Swap entries must have VALID and GLOBAL bits cleared. */
200 #define __swp_type(x) (((x).val >> 2) & 0x1f)
201 #define __swp_offset(x) ((x).val >> 7)
202 #define __swp_entry(type, offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 7) })
203 #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
204 #define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
205
206 #else
207 /*
208 * Constraints:
209 * _PAGE_PRESENT at bit 0
210 * _PAGE_MODIFIED at bit 4
211 * _PAGE_GLOBAL at bit 6
212 * _PAGE_VALID at bit 7
213 */
214 #define __swp_type(x) (((x).val >> 8) & 0x1f)
215 #define __swp_offset(x) ((x).val >> 13)
216 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
217 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
218 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
219
220 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */
221
222 #endif /* defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) */
223
224 #endif /* _ASM_PGTABLE_32_H */
225