1 /* 2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> 3 */ 4 #ifndef _ASM_POWERPC_BARRIER_H 5 #define _ASM_POWERPC_BARRIER_H 6 7 /* 8 * Memory barrier. 9 * The sync instruction guarantees that all memory accesses initiated 10 * by this processor have been performed (with respect to all other 11 * mechanisms that access memory). The eieio instruction is a barrier 12 * providing an ordering (separately) for (a) cacheable stores and (b) 13 * loads and stores to non-cacheable memory (e.g. I/O devices). 14 * 15 * mb() prevents loads and stores being reordered across this point. 16 * rmb() prevents loads being reordered across this point. 17 * wmb() prevents stores being reordered across this point. 18 * read_barrier_depends() prevents data-dependent loads being reordered 19 * across this point (nop on PPC). 20 * 21 * *mb() variants without smp_ prefix must order all types of memory 22 * operations with one another. sync is the only instruction sufficient 23 * to do this. 24 * 25 * For the smp_ barriers, ordering is for cacheable memory operations 26 * only. We have to use the sync instruction for smp_mb(), since lwsync 27 * doesn't order loads with respect to previous stores. Lwsync can be 28 * used for smp_rmb() and smp_wmb(). 29 * 30 * However, on CPUs that don't support lwsync, lwsync actually maps to a 31 * heavy-weight sync, so smp_wmb() can be a lighter-weight eieio. 32 */ 33 #define mb() __asm__ __volatile__ ("sync" : : : "memory") 34 #define rmb() __asm__ __volatile__ ("sync" : : : "memory") 35 #define wmb() __asm__ __volatile__ ("sync" : : : "memory") 36 37 /* The sub-arch has lwsync */ 38 #if defined(__powerpc64__) || defined(CONFIG_PPC_E500MC) 39 # define SMPWMB LWSYNC 40 #else 41 # define SMPWMB eieio 42 #endif 43 44 #define __lwsync() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory") 45 #define dma_rmb() __lwsync() 46 #define dma_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory") 47 48 #define __smp_lwsync() __lwsync() 49 50 #define __smp_mb() mb() 51 #define __smp_rmb() __lwsync() 52 #define __smp_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory") 53 54 /* 55 * This is a barrier which prevents following instructions from being 56 * started until the value of the argument x is known. For example, if 57 * x is a variable loaded from memory, this prevents following 58 * instructions from being executed until the load has been performed. 59 */ 60 #define data_barrier(x) \ 61 asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory"); 62 63 #define __smp_store_release(p, v) \ 64 do { \ 65 compiletime_assert_atomic_type(*p); \ 66 __smp_lwsync(); \ 67 WRITE_ONCE(*p, v); \ 68 } while (0) 69 70 #define __smp_load_acquire(p) \ 71 ({ \ 72 typeof(*p) ___p1 = READ_ONCE(*p); \ 73 compiletime_assert_atomic_type(*p); \ 74 __smp_lwsync(); \ 75 ___p1; \ 76 }) 77 78 #define smp_mb__before_spinlock() smp_mb() 79 80 #include <asm-generic/barrier.h> 81 82 #endif /* _ASM_POWERPC_BARRIER_H */ 83