1 #ifndef _ASM_POWERPC_EXCEPTION_H 2 #define _ASM_POWERPC_EXCEPTION_H 3 /* 4 * Extracted from head_64.S 5 * 6 * PowerPC version 7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 8 * 9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP 10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu> 11 * Adapted for Power Macintosh by Paul Mackerras. 12 * Low-level exception handlers and MMU support 13 * rewritten by Paul Mackerras. 14 * Copyright (C) 1996 Paul Mackerras. 15 * 16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and 17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com 18 * 19 * This file contains the low-level support and setup for the 20 * PowerPC-64 platform, including trap and interrupt dispatch. 21 * 22 * This program is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU General Public License 24 * as published by the Free Software Foundation; either version 25 * 2 of the License, or (at your option) any later version. 26 */ 27 /* 28 * The following macros define the code that appears as 29 * the prologue to each of the exception handlers. They 30 * are split into two parts to allow a single kernel binary 31 * to be used for pSeries and iSeries. 32 * 33 * We make as much of the exception code common between native 34 * exception handlers (including pSeries LPAR) and iSeries LPAR 35 * implementations as possible. 36 */ 37 #include <asm/head-64.h> 38 39 #define EX_R9 0 40 #define EX_R10 8 41 #define EX_R11 16 42 #define EX_R12 24 43 #define EX_R13 32 44 #define EX_SRR0 40 45 #define EX_DAR 48 46 #define EX_DSISR 56 47 #define EX_CCR 60 48 #define EX_R3 64 49 #define EX_LR 72 50 #define EX_CFAR 80 51 #define EX_PPR 88 /* SMT thread status register (priority) */ 52 #define EX_CTR 96 53 54 /* 55 * Macros for annotating the expected destination of (h)rfid 56 * 57 * The nop instructions allow us to insert one or more instructions to flush the 58 * L1-D cache when returning to userspace or a guest. 59 */ 60 #define RFI_FLUSH_SLOT \ 61 RFI_FLUSH_FIXUP_SECTION; \ 62 nop; \ 63 nop; \ 64 nop 65 66 #define RFI_TO_KERNEL \ 67 rfid 68 69 #define RFI_TO_USER \ 70 RFI_FLUSH_SLOT; \ 71 rfid; \ 72 b rfi_flush_fallback 73 74 #define RFI_TO_USER_OR_KERNEL \ 75 RFI_FLUSH_SLOT; \ 76 rfid; \ 77 b rfi_flush_fallback 78 79 #define RFI_TO_GUEST \ 80 RFI_FLUSH_SLOT; \ 81 rfid; \ 82 b rfi_flush_fallback 83 84 #define HRFI_TO_KERNEL \ 85 hrfid 86 87 #define HRFI_TO_USER \ 88 RFI_FLUSH_SLOT; \ 89 hrfid; \ 90 b hrfi_flush_fallback 91 92 #define HRFI_TO_USER_OR_KERNEL \ 93 RFI_FLUSH_SLOT; \ 94 hrfid; \ 95 b hrfi_flush_fallback 96 97 #define HRFI_TO_GUEST \ 98 RFI_FLUSH_SLOT; \ 99 hrfid; \ 100 b hrfi_flush_fallback 101 102 #define HRFI_TO_UNKNOWN \ 103 RFI_FLUSH_SLOT; \ 104 hrfid; \ 105 b hrfi_flush_fallback 106 107 #ifdef CONFIG_RELOCATABLE 108 #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 109 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 110 LOAD_HANDLER(r12,label); \ 111 mtctr r12; \ 112 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 113 li r10,MSR_RI; \ 114 mtmsrd r10,1; /* Set RI (EE=0) */ \ 115 bctr; 116 #else 117 /* If not relocatable, we can jump directly -- and save messing with LR */ 118 #define __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 119 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 120 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 121 li r10,MSR_RI; \ 122 mtmsrd r10,1; /* Set RI (EE=0) */ \ 123 b label; 124 #endif 125 #define EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 126 __EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) \ 127 128 /* 129 * As EXCEPTION_PROLOG_PSERIES(), except we've already got relocation on 130 * so no need to rfid. Save lr in case we're CONFIG_RELOCATABLE, in which 131 * case EXCEPTION_RELON_PROLOG_PSERIES_1 will be using lr. 132 */ 133 #define EXCEPTION_RELON_PROLOG_PSERIES(area, label, h, extra, vec) \ 134 EXCEPTION_PROLOG_0(area); \ 135 EXCEPTION_PROLOG_1(area, extra, vec); \ 136 EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) 137 138 /* 139 * We're short on space and time in the exception prolog, so we can't 140 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label. 141 * Instead we get the base of the kernel from paca->kernelbase and or in the low 142 * part of label. This requires that the label be within 64KB of kernelbase, and 143 * that kernelbase be 64K aligned. 144 */ 145 #define LOAD_HANDLER(reg, label) \ 146 ld reg,PACAKBASE(r13); /* get high part of &label */ \ 147 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label); 148 149 #define __LOAD_HANDLER(reg, label) \ 150 ld reg,PACAKBASE(r13); \ 151 ori reg,reg,(ABS_ADDR(label))@l; 152 153 /* Exception register prefixes */ 154 #define EXC_HV H 155 #define EXC_STD 156 157 #if defined(CONFIG_RELOCATABLE) 158 /* 159 * If we support interrupts with relocation on AND we're a relocatable kernel, 160 * we need to use CTR to get to the 2nd level handler. So, save/restore it 161 * when required. 162 */ 163 #define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13) 164 #define GET_CTR(reg, area) ld reg,area+EX_CTR(r13) 165 #define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg 166 #else 167 /* ...else CTR is unused and in register. */ 168 #define SAVE_CTR(reg, area) 169 #define GET_CTR(reg, area) mfctr reg 170 #define RESTORE_CTR(reg, area) 171 #endif 172 173 /* 174 * PPR save/restore macros used in exceptions_64s.S 175 * Used for P7 or later processors 176 */ 177 #define SAVE_PPR(area, ra, rb) \ 178 BEGIN_FTR_SECTION_NESTED(940) \ 179 ld ra,PACACURRENT(r13); \ 180 ld rb,area+EX_PPR(r13); /* Read PPR from paca */ \ 181 std rb,TASKTHREADPPR(ra); \ 182 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940) 183 184 #define RESTORE_PPR_PACA(area, ra) \ 185 BEGIN_FTR_SECTION_NESTED(941) \ 186 ld ra,area+EX_PPR(r13); \ 187 mtspr SPRN_PPR,ra; \ 188 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941) 189 190 /* 191 * Get an SPR into a register if the CPU has the given feature 192 */ 193 #define OPT_GET_SPR(ra, spr, ftr) \ 194 BEGIN_FTR_SECTION_NESTED(943) \ 195 mfspr ra,spr; \ 196 END_FTR_SECTION_NESTED(ftr,ftr,943) 197 198 /* 199 * Set an SPR from a register if the CPU has the given feature 200 */ 201 #define OPT_SET_SPR(ra, spr, ftr) \ 202 BEGIN_FTR_SECTION_NESTED(943) \ 203 mtspr spr,ra; \ 204 END_FTR_SECTION_NESTED(ftr,ftr,943) 205 206 /* 207 * Save a register to the PACA if the CPU has the given feature 208 */ 209 #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \ 210 BEGIN_FTR_SECTION_NESTED(943) \ 211 std ra,offset(r13); \ 212 END_FTR_SECTION_NESTED(ftr,ftr,943) 213 214 #define EXCEPTION_PROLOG_0_PACA(area) \ 215 std r9,area+EX_R9(r13); /* save r9 */ \ 216 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \ 217 HMT_MEDIUM; \ 218 std r10,area+EX_R10(r13); /* save r10 - r12 */ \ 219 OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR) 220 221 #define EXCEPTION_PROLOG_0(area) \ 222 GET_PACA(r13); \ 223 EXCEPTION_PROLOG_0_PACA(area) 224 225 #define __EXCEPTION_PROLOG_1(area, extra, vec) \ 226 OPT_SAVE_REG_TO_PACA(area+EX_PPR, r9, CPU_FTR_HAS_PPR); \ 227 OPT_SAVE_REG_TO_PACA(area+EX_CFAR, r10, CPU_FTR_CFAR); \ 228 SAVE_CTR(r10, area); \ 229 mfcr r9; \ 230 extra(vec); \ 231 std r11,area+EX_R11(r13); \ 232 std r12,area+EX_R12(r13); \ 233 GET_SCRATCH0(r10); \ 234 std r10,area+EX_R13(r13) 235 #define EXCEPTION_PROLOG_1(area, extra, vec) \ 236 __EXCEPTION_PROLOG_1(area, extra, vec) 237 238 #define __EXCEPTION_PROLOG_PSERIES_1(label, h) \ 239 ld r10,PACAKMSR(r13); /* get MSR value for kernel */ \ 240 mfspr r11,SPRN_##h##SRR0; /* save SRR0 */ \ 241 LOAD_HANDLER(r12,label) \ 242 mtspr SPRN_##h##SRR0,r12; \ 243 mfspr r12,SPRN_##h##SRR1; /* and SRR1 */ \ 244 mtspr SPRN_##h##SRR1,r10; \ 245 h##RFI_TO_KERNEL; \ 246 b . /* prevent speculative execution */ 247 #define EXCEPTION_PROLOG_PSERIES_1(label, h) \ 248 __EXCEPTION_PROLOG_PSERIES_1(label, h) 249 250 #define EXCEPTION_PROLOG_PSERIES(area, label, h, extra, vec) \ 251 EXCEPTION_PROLOG_0(area); \ 252 EXCEPTION_PROLOG_1(area, extra, vec); \ 253 EXCEPTION_PROLOG_PSERIES_1(label, h); 254 255 /* Have the PACA in r13 already */ 256 #define EXCEPTION_PROLOG_PSERIES_PACA(area, label, h, extra, vec) \ 257 EXCEPTION_PROLOG_0_PACA(area); \ 258 EXCEPTION_PROLOG_1(area, extra, vec); \ 259 EXCEPTION_PROLOG_PSERIES_1(label, h); 260 261 #define __KVMTEST(h, n) \ 262 lbz r10,HSTATE_IN_GUEST(r13); \ 263 cmpwi r10,0; \ 264 bne do_kvm_##h##n 265 266 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE 267 /* 268 * If hv is possible, interrupts come into to the hv version 269 * of the kvmppc_interrupt code, which then jumps to the PR handler, 270 * kvmppc_interrupt_pr, if the guest is a PR guest. 271 */ 272 #define kvmppc_interrupt kvmppc_interrupt_hv 273 #else 274 #define kvmppc_interrupt kvmppc_interrupt_pr 275 #endif 276 277 #ifdef CONFIG_RELOCATABLE 278 #define BRANCH_TO_COMMON(reg, label) \ 279 __LOAD_HANDLER(reg, label); \ 280 mtctr reg; \ 281 bctr 282 283 #else 284 #define BRANCH_TO_COMMON(reg, label) \ 285 b label 286 287 #endif 288 289 #define __KVM_HANDLER_PROLOG(area, n) \ 290 BEGIN_FTR_SECTION_NESTED(947) \ 291 ld r10,area+EX_CFAR(r13); \ 292 std r10,HSTATE_CFAR(r13); \ 293 END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947); \ 294 BEGIN_FTR_SECTION_NESTED(948) \ 295 ld r10,area+EX_PPR(r13); \ 296 std r10,HSTATE_PPR(r13); \ 297 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ 298 ld r10,area+EX_R10(r13); \ 299 stw r9,HSTATE_SCRATCH1(r13); \ 300 ld r9,area+EX_R9(r13); \ 301 std r12,HSTATE_SCRATCH0(r13); \ 302 303 #define __KVM_HANDLER(area, h, n) \ 304 __KVM_HANDLER_PROLOG(area, n) \ 305 li r12,n; \ 306 b kvmppc_interrupt 307 308 #define __KVM_HANDLER_SKIP(area, h, n) \ 309 cmpwi r10,KVM_GUEST_MODE_SKIP; \ 310 ld r10,area+EX_R10(r13); \ 311 beq 89f; \ 312 stw r9,HSTATE_SCRATCH1(r13); \ 313 BEGIN_FTR_SECTION_NESTED(948) \ 314 ld r9,area+EX_PPR(r13); \ 315 std r9,HSTATE_PPR(r13); \ 316 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948); \ 317 ld r9,area+EX_R9(r13); \ 318 std r12,HSTATE_SCRATCH0(r13); \ 319 li r12,n; \ 320 b kvmppc_interrupt; \ 321 89: mtocrf 0x80,r9; \ 322 ld r9,area+EX_R9(r13); \ 323 b kvmppc_skip_##h##interrupt 324 325 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER 326 #define KVMTEST(h, n) __KVMTEST(h, n) 327 #define KVM_HANDLER(area, h, n) __KVM_HANDLER(area, h, n) 328 #define KVM_HANDLER_SKIP(area, h, n) __KVM_HANDLER_SKIP(area, h, n) 329 330 #else 331 #define KVMTEST(h, n) 332 #define KVM_HANDLER(area, h, n) 333 #define KVM_HANDLER_SKIP(area, h, n) 334 #endif 335 336 #define NOTEST(n) 337 338 /* 339 * The common exception prolog is used for all except a few exceptions 340 * such as a segment miss on a kernel address. We have to be prepared 341 * to take another exception from the point where we first touch the 342 * kernel stack onwards. 343 * 344 * On entry r13 points to the paca, r9-r13 are saved in the paca, 345 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and 346 * SRR1, and relocation is on. 347 */ 348 #define EXCEPTION_PROLOG_COMMON(n, area) \ 349 andi. r10,r12,MSR_PR; /* See if coming from user */ \ 350 mr r10,r1; /* Save r1 */ \ 351 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \ 352 beq- 1f; \ 353 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \ 354 1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \ 355 blt+ cr1,3f; /* abort if it is */ \ 356 li r1,(n); /* will be reloaded later */ \ 357 sth r1,PACA_TRAP_SAVE(r13); \ 358 std r3,area+EX_R3(r13); \ 359 addi r3,r13,area; /* r3 -> where regs are saved*/ \ 360 RESTORE_CTR(r1, area); \ 361 b bad_stack; \ 362 3: std r9,_CCR(r1); /* save CR in stackframe */ \ 363 std r11,_NIP(r1); /* save SRR0 in stackframe */ \ 364 std r12,_MSR(r1); /* save SRR1 in stackframe */ \ 365 std r10,0(r1); /* make stack chain pointer */ \ 366 std r0,GPR0(r1); /* save r0 in stackframe */ \ 367 std r10,GPR1(r1); /* save r1 in stackframe */ \ 368 beq 4f; /* if from kernel mode */ \ 369 ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \ 370 SAVE_PPR(area, r9, r10); \ 371 4: EXCEPTION_PROLOG_COMMON_2(area) \ 372 EXCEPTION_PROLOG_COMMON_3(n) \ 373 ACCOUNT_STOLEN_TIME 374 375 /* Save original regs values from save area to stack frame. */ 376 #define EXCEPTION_PROLOG_COMMON_2(area) \ 377 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \ 378 ld r10,area+EX_R10(r13); \ 379 std r9,GPR9(r1); \ 380 std r10,GPR10(r1); \ 381 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \ 382 ld r10,area+EX_R12(r13); \ 383 ld r11,area+EX_R13(r13); \ 384 std r9,GPR11(r1); \ 385 std r10,GPR12(r1); \ 386 std r11,GPR13(r1); \ 387 BEGIN_FTR_SECTION_NESTED(66); \ 388 ld r10,area+EX_CFAR(r13); \ 389 std r10,ORIG_GPR3(r1); \ 390 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \ 391 GET_CTR(r10, area); \ 392 std r10,_CTR(r1); 393 394 #define EXCEPTION_PROLOG_COMMON_3(n) \ 395 std r2,GPR2(r1); /* save r2 in stackframe */ \ 396 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ 397 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ 398 mflr r9; /* Get LR, later save to stack */ \ 399 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \ 400 std r9,_LINK(r1); \ 401 lbz r10,PACASOFTIRQEN(r13); \ 402 mfspr r11,SPRN_XER; /* save XER in stackframe */ \ 403 std r10,SOFTE(r1); \ 404 std r11,_XER(r1); \ 405 li r9,(n)+1; \ 406 std r9,_TRAP(r1); /* set trap number */ \ 407 li r10,0; \ 408 ld r11,exception_marker@toc(r2); \ 409 std r10,RESULT(r1); /* clear regs->result */ \ 410 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ 411 412 /* 413 * Exception vectors. 414 */ 415 #define STD_EXCEPTION_PSERIES(vec, label) \ 416 SET_SCRATCH0(r13); /* save r13 */ \ 417 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label, \ 418 EXC_STD, KVMTEST_PR, vec); \ 419 420 /* Version of above for when we have to branch out-of-line */ 421 #define __OOL_EXCEPTION(vec, label, hdlr) \ 422 SET_SCRATCH0(r13) \ 423 EXCEPTION_PROLOG_0(PACA_EXGEN) \ 424 b hdlr; 425 426 #define STD_EXCEPTION_PSERIES_OOL(vec, label) \ 427 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_PR, vec); \ 428 EXCEPTION_PROLOG_PSERIES_1(label, EXC_STD) 429 430 #define STD_EXCEPTION_HV(loc, vec, label) \ 431 SET_SCRATCH0(r13); /* save r13 */ \ 432 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label, \ 433 EXC_HV, KVMTEST_HV, vec); 434 435 #define STD_EXCEPTION_HV_OOL(vec, label) \ 436 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, vec); \ 437 EXCEPTION_PROLOG_PSERIES_1(label, EXC_HV) 438 439 #define STD_RELON_EXCEPTION_PSERIES(loc, vec, label) \ 440 /* No guest interrupts come through here */ \ 441 SET_SCRATCH0(r13); /* save r13 */ \ 442 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label, EXC_STD, NOTEST, vec); 443 444 #define STD_RELON_EXCEPTION_PSERIES_OOL(vec, label) \ 445 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec); \ 446 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_STD) 447 448 #define STD_RELON_EXCEPTION_HV(loc, vec, label) \ 449 /* No guest interrupts come through here */ \ 450 SET_SCRATCH0(r13); /* save r13 */ \ 451 EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label, EXC_HV, NOTEST, vec); 452 453 #define STD_RELON_EXCEPTION_HV_OOL(vec, label) \ 454 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec); \ 455 EXCEPTION_RELON_PROLOG_PSERIES_1(label, EXC_HV) 456 457 /* This associate vector numbers with bits in paca->irq_happened */ 458 #define SOFTEN_VALUE_0x500 PACA_IRQ_EE 459 #define SOFTEN_VALUE_0x900 PACA_IRQ_DEC 460 #define SOFTEN_VALUE_0x980 PACA_IRQ_DEC 461 #define SOFTEN_VALUE_0xa00 PACA_IRQ_DBELL 462 #define SOFTEN_VALUE_0xe80 PACA_IRQ_DBELL 463 #define SOFTEN_VALUE_0xe60 PACA_IRQ_HMI 464 #define SOFTEN_VALUE_0xea0 PACA_IRQ_EE 465 466 #define __SOFTEN_TEST(h, vec) \ 467 lbz r10,PACASOFTIRQEN(r13); \ 468 cmpwi r10,0; \ 469 li r10,SOFTEN_VALUE_##vec; \ 470 beq masked_##h##interrupt 471 472 #define _SOFTEN_TEST(h, vec) __SOFTEN_TEST(h, vec) 473 474 #define SOFTEN_TEST_PR(vec) \ 475 KVMTEST(EXC_STD, vec); \ 476 _SOFTEN_TEST(EXC_STD, vec) 477 478 #define SOFTEN_TEST_HV(vec) \ 479 KVMTEST(EXC_HV, vec); \ 480 _SOFTEN_TEST(EXC_HV, vec) 481 482 #define KVMTEST_PR(vec) \ 483 KVMTEST(EXC_STD, vec) 484 485 #define KVMTEST_HV(vec) \ 486 KVMTEST(EXC_HV, vec) 487 488 #define SOFTEN_NOTEST_PR(vec) _SOFTEN_TEST(EXC_STD, vec) 489 #define SOFTEN_NOTEST_HV(vec) _SOFTEN_TEST(EXC_HV, vec) 490 491 #define __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \ 492 SET_SCRATCH0(r13); /* save r13 */ \ 493 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 494 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \ 495 EXCEPTION_PROLOG_PSERIES_1(label, h); 496 497 #define _MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) \ 498 __MASKABLE_EXCEPTION_PSERIES(vec, label, h, extra) 499 500 #define MASKABLE_EXCEPTION_PSERIES(loc, vec, label) \ 501 _MASKABLE_EXCEPTION_PSERIES(vec, label, \ 502 EXC_STD, SOFTEN_TEST_PR) 503 504 #define MASKABLE_EXCEPTION_PSERIES_OOL(vec, label) \ 505 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_PR, vec); \ 506 EXCEPTION_PROLOG_PSERIES_1(label, EXC_STD) 507 508 #define MASKABLE_EXCEPTION_HV(loc, vec, label) \ 509 _MASKABLE_EXCEPTION_PSERIES(vec, label, \ 510 EXC_HV, SOFTEN_TEST_HV) 511 512 #define MASKABLE_EXCEPTION_HV_OOL(vec, label) \ 513 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_TEST_HV, vec); \ 514 EXCEPTION_PROLOG_PSERIES_1(label, EXC_HV) 515 516 #define __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \ 517 SET_SCRATCH0(r13); /* save r13 */ \ 518 EXCEPTION_PROLOG_0(PACA_EXGEN); \ 519 __EXCEPTION_PROLOG_1(PACA_EXGEN, extra, vec); \ 520 EXCEPTION_RELON_PROLOG_PSERIES_1(label, h) 521 522 #define _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) \ 523 __MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, h, extra) 524 525 #define MASKABLE_RELON_EXCEPTION_PSERIES(loc, vec, label) \ 526 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ 527 EXC_STD, SOFTEN_NOTEST_PR) 528 529 #define MASKABLE_RELON_EXCEPTION_HV(loc, vec, label) \ 530 _MASKABLE_RELON_EXCEPTION_PSERIES(vec, label, \ 531 EXC_HV, SOFTEN_NOTEST_HV) 532 533 #define MASKABLE_RELON_EXCEPTION_HV_OOL(vec, label) \ 534 EXCEPTION_PROLOG_1(PACA_EXGEN, SOFTEN_NOTEST_HV, vec); \ 535 EXCEPTION_PROLOG_PSERIES_1(label, EXC_HV) 536 537 /* 538 * Our exception common code can be passed various "additions" 539 * to specify the behaviour of interrupts, whether to kick the 540 * runlatch, etc... 541 */ 542 543 /* 544 * This addition reconciles our actual IRQ state with the various software 545 * flags that track it. This may call C code. 546 */ 547 #define ADD_RECONCILE RECONCILE_IRQ_STATE(r10,r11) 548 549 #define ADD_NVGPRS \ 550 bl save_nvgprs 551 552 #define RUNLATCH_ON \ 553 BEGIN_FTR_SECTION \ 554 CURRENT_THREAD_INFO(r3, r1); \ 555 ld r4,TI_LOCAL_FLAGS(r3); \ 556 andi. r0,r4,_TLF_RUNLATCH; \ 557 beql ppc64_runlatch_on_trampoline; \ 558 END_FTR_SECTION_IFSET(CPU_FTR_CTRL) 559 560 #define EXCEPTION_COMMON(trap, label, hdlr, ret, additions) \ 561 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \ 562 /* Volatile regs are potentially clobbered here */ \ 563 additions; \ 564 addi r3,r1,STACK_FRAME_OVERHEAD; \ 565 bl hdlr; \ 566 b ret 567 568 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \ 569 EXCEPTION_COMMON(trap, label, hdlr, ret_from_except, \ 570 ADD_NVGPRS;ADD_RECONCILE) 571 572 /* 573 * Like STD_EXCEPTION_COMMON, but for exceptions that can occur 574 * in the idle task and therefore need the special idle handling 575 * (finish nap and runlatch) 576 */ 577 #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \ 578 EXCEPTION_COMMON(trap, label, hdlr, ret_from_except_lite, \ 579 FINISH_NAP;ADD_RECONCILE;RUNLATCH_ON) 580 581 /* 582 * When the idle code in power4_idle puts the CPU into NAP mode, 583 * it has to do so in a loop, and relies on the external interrupt 584 * and decrementer interrupt entry code to get it out of the loop. 585 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags 586 * to signal that it is in the loop and needs help to get out. 587 */ 588 #ifdef CONFIG_PPC_970_NAP 589 #define FINISH_NAP \ 590 BEGIN_FTR_SECTION \ 591 CURRENT_THREAD_INFO(r11, r1); \ 592 ld r9,TI_LOCAL_FLAGS(r11); \ 593 andi. r10,r9,_TLF_NAPPING; \ 594 bnel power4_fixup_nap; \ 595 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) 596 #else 597 #define FINISH_NAP 598 #endif 599 600 #endif /* _ASM_POWERPC_EXCEPTION_H */ 601