1 /*
2 * native hashtable management.
3 *
4 * SMP scalability work:
5 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13 #undef DEBUG_LOW
14
15 #include <linux/spinlock.h>
16 #include <linux/bitops.h>
17 #include <linux/of.h>
18 #include <linux/threads.h>
19 #include <linux/smp.h>
20
21 #include <asm/machdep.h>
22 #include <asm/mmu.h>
23 #include <asm/mmu_context.h>
24 #include <asm/pgtable.h>
25 #include <asm/tlbflush.h>
26 #include <asm/tlb.h>
27 #include <asm/cputable.h>
28 #include <asm/udbg.h>
29 #include <asm/kexec.h>
30 #include <asm/ppc-opcode.h>
31
32 #include <misc/cxl-base.h>
33
34 #ifdef DEBUG_LOW
35 #define DBG_LOW(fmt...) udbg_printf(fmt)
36 #else
37 #define DBG_LOW(fmt...)
38 #endif
39
40 #ifdef __BIG_ENDIAN__
41 #define HPTE_LOCK_BIT 3
42 #else
43 #define HPTE_LOCK_BIT (56+3)
44 #endif
45
46 DEFINE_RAW_SPINLOCK(native_tlbie_lock);
47
__tlbie(unsigned long vpn,int psize,int apsize,int ssize)48 static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
49 {
50 unsigned long va;
51 unsigned int penc;
52 unsigned long sllp;
53
54 /*
55 * We need 14 to 65 bits of va for a tlibe of 4K page
56 * With vpn we ignore the lower VPN_SHIFT bits already.
57 * And top two bits are already ignored because we can
58 * only accomodate 76 bits in a 64 bit vpn with a VPN_SHIFT
59 * of 12.
60 */
61 va = vpn << VPN_SHIFT;
62 /*
63 * clear top 16 bits of 64bit va, non SLS segment
64 * Older versions of the architecture (2.02 and earler) require the
65 * masking of the top 16 bits.
66 */
67 if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))
68 va &= ~(0xffffULL << 48);
69
70 switch (psize) {
71 case MMU_PAGE_4K:
72 /* clear out bits after (52) [0....52.....63] */
73 va &= ~((1ul << (64 - 52)) - 1);
74 va |= ssize << 8;
75 sllp = get_sllp_encoding(apsize);
76 va |= sllp << 5;
77 asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
78 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
79 : "memory");
80 break;
81 default:
82 /* We need 14 to 14 + i bits of va */
83 penc = mmu_psize_defs[psize].penc[apsize];
84 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
85 va |= penc << 12;
86 va |= ssize << 8;
87 /*
88 * AVAL bits:
89 * We don't need all the bits, but rest of the bits
90 * must be ignored by the processor.
91 * vpn cover upto 65 bits of va. (0...65) and we need
92 * 58..64 bits of va.
93 */
94 va |= (vpn & 0xfe); /* AVAL */
95 va |= 1; /* L */
96 asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
97 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
98 : "memory");
99 break;
100 }
101 }
102
__tlbiel(unsigned long vpn,int psize,int apsize,int ssize)103 static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
104 {
105 unsigned long va;
106 unsigned int penc;
107 unsigned long sllp;
108
109 /* VPN_SHIFT can be atmost 12 */
110 va = vpn << VPN_SHIFT;
111 /*
112 * clear top 16 bits of 64 bit va, non SLS segment
113 * Older versions of the architecture (2.02 and earler) require the
114 * masking of the top 16 bits.
115 */
116 if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))
117 va &= ~(0xffffULL << 48);
118
119 switch (psize) {
120 case MMU_PAGE_4K:
121 /* clear out bits after(52) [0....52.....63] */
122 va &= ~((1ul << (64 - 52)) - 1);
123 va |= ssize << 8;
124 sllp = get_sllp_encoding(apsize);
125 va |= sllp << 5;
126 asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)"
127 : : "r"(va) : "memory");
128 break;
129 default:
130 /* We need 14 to 14 + i bits of va */
131 penc = mmu_psize_defs[psize].penc[apsize];
132 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
133 va |= penc << 12;
134 va |= ssize << 8;
135 /*
136 * AVAL bits:
137 * We don't need all the bits, but rest of the bits
138 * must be ignored by the processor.
139 * vpn cover upto 65 bits of va. (0...65) and we need
140 * 58..64 bits of va.
141 */
142 va |= (vpn & 0xfe);
143 va |= 1; /* L */
144 asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)"
145 : : "r"(va) : "memory");
146 break;
147 }
148
149 }
150
tlbie(unsigned long vpn,int psize,int apsize,int ssize,int local)151 static inline void tlbie(unsigned long vpn, int psize, int apsize,
152 int ssize, int local)
153 {
154 unsigned int use_local;
155 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
156
157 use_local = local && mmu_has_feature(MMU_FTR_TLBIEL) && !cxl_ctx_in_use();
158
159 if (use_local)
160 use_local = mmu_psize_defs[psize].tlbiel;
161 if (lock_tlbie && !use_local)
162 raw_spin_lock(&native_tlbie_lock);
163 asm volatile("ptesync": : :"memory");
164 if (use_local) {
165 __tlbiel(vpn, psize, apsize, ssize);
166 asm volatile("ptesync": : :"memory");
167 } else {
168 __tlbie(vpn, psize, apsize, ssize);
169 asm volatile("eieio; tlbsync; ptesync": : :"memory");
170 }
171 if (lock_tlbie && !use_local)
172 raw_spin_unlock(&native_tlbie_lock);
173 }
174
native_lock_hpte(struct hash_pte * hptep)175 static inline void native_lock_hpte(struct hash_pte *hptep)
176 {
177 unsigned long *word = (unsigned long *)&hptep->v;
178
179 while (1) {
180 if (!test_and_set_bit_lock(HPTE_LOCK_BIT, word))
181 break;
182 while(test_bit(HPTE_LOCK_BIT, word))
183 cpu_relax();
184 }
185 }
186
native_unlock_hpte(struct hash_pte * hptep)187 static inline void native_unlock_hpte(struct hash_pte *hptep)
188 {
189 unsigned long *word = (unsigned long *)&hptep->v;
190
191 clear_bit_unlock(HPTE_LOCK_BIT, word);
192 }
193
native_hpte_insert(unsigned long hpte_group,unsigned long vpn,unsigned long pa,unsigned long rflags,unsigned long vflags,int psize,int apsize,int ssize)194 static long native_hpte_insert(unsigned long hpte_group, unsigned long vpn,
195 unsigned long pa, unsigned long rflags,
196 unsigned long vflags, int psize, int apsize, int ssize)
197 {
198 struct hash_pte *hptep = htab_address + hpte_group;
199 unsigned long hpte_v, hpte_r;
200 int i;
201
202 if (!(vflags & HPTE_V_BOLTED)) {
203 DBG_LOW(" insert(group=%lx, vpn=%016lx, pa=%016lx,"
204 " rflags=%lx, vflags=%lx, psize=%d)\n",
205 hpte_group, vpn, pa, rflags, vflags, psize);
206 }
207
208 for (i = 0; i < HPTES_PER_GROUP; i++) {
209 if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID)) {
210 /* retry with lock held */
211 native_lock_hpte(hptep);
212 if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID))
213 break;
214 native_unlock_hpte(hptep);
215 }
216
217 hptep++;
218 }
219
220 if (i == HPTES_PER_GROUP)
221 return -1;
222
223 hpte_v = hpte_encode_v(vpn, psize, apsize, ssize) | vflags | HPTE_V_VALID;
224 hpte_r = hpte_encode_r(pa, psize, apsize) | rflags;
225
226 if (!(vflags & HPTE_V_BOLTED)) {
227 DBG_LOW(" i=%x hpte_v=%016lx, hpte_r=%016lx\n",
228 i, hpte_v, hpte_r);
229 }
230
231 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
232 hpte_r = hpte_old_to_new_r(hpte_v, hpte_r);
233 hpte_v = hpte_old_to_new_v(hpte_v);
234 }
235
236 hptep->r = cpu_to_be64(hpte_r);
237 /* Guarantee the second dword is visible before the valid bit */
238 eieio();
239 /*
240 * Now set the first dword including the valid bit
241 * NOTE: this also unlocks the hpte
242 */
243 hptep->v = cpu_to_be64(hpte_v);
244
245 __asm__ __volatile__ ("ptesync" : : : "memory");
246
247 return i | (!!(vflags & HPTE_V_SECONDARY) << 3);
248 }
249
native_hpte_remove(unsigned long hpte_group)250 static long native_hpte_remove(unsigned long hpte_group)
251 {
252 struct hash_pte *hptep;
253 int i;
254 int slot_offset;
255 unsigned long hpte_v;
256
257 DBG_LOW(" remove(group=%lx)\n", hpte_group);
258
259 /* pick a random entry to start at */
260 slot_offset = mftb() & 0x7;
261
262 for (i = 0; i < HPTES_PER_GROUP; i++) {
263 hptep = htab_address + hpte_group + slot_offset;
264 hpte_v = be64_to_cpu(hptep->v);
265
266 if ((hpte_v & HPTE_V_VALID) && !(hpte_v & HPTE_V_BOLTED)) {
267 /* retry with lock held */
268 native_lock_hpte(hptep);
269 hpte_v = be64_to_cpu(hptep->v);
270 if ((hpte_v & HPTE_V_VALID)
271 && !(hpte_v & HPTE_V_BOLTED))
272 break;
273 native_unlock_hpte(hptep);
274 }
275
276 slot_offset++;
277 slot_offset &= 0x7;
278 }
279
280 if (i == HPTES_PER_GROUP)
281 return -1;
282
283 /* Invalidate the hpte. NOTE: this also unlocks it */
284 hptep->v = 0;
285
286 return i;
287 }
288
native_hpte_updatepp(unsigned long slot,unsigned long newpp,unsigned long vpn,int bpsize,int apsize,int ssize,unsigned long flags)289 static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
290 unsigned long vpn, int bpsize,
291 int apsize, int ssize, unsigned long flags)
292 {
293 struct hash_pte *hptep = htab_address + slot;
294 unsigned long hpte_v, want_v;
295 int ret = 0, local = 0;
296
297 want_v = hpte_encode_avpn(vpn, bpsize, ssize);
298
299 DBG_LOW(" update(vpn=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)",
300 vpn, want_v & HPTE_V_AVPN, slot, newpp);
301
302 hpte_v = be64_to_cpu(hptep->v);
303 if (cpu_has_feature(CPU_FTR_ARCH_300))
304 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
305 /*
306 * We need to invalidate the TLB always because hpte_remove doesn't do
307 * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
308 * random entry from it. When we do that we don't invalidate the TLB
309 * (hpte_remove) because we assume the old translation is still
310 * technically "valid".
311 */
312 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) {
313 DBG_LOW(" -> miss\n");
314 ret = -1;
315 } else {
316 native_lock_hpte(hptep);
317 /* recheck with locks held */
318 hpte_v = be64_to_cpu(hptep->v);
319 if (cpu_has_feature(CPU_FTR_ARCH_300))
320 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
321 if (unlikely(!HPTE_V_COMPARE(hpte_v, want_v) ||
322 !(hpte_v & HPTE_V_VALID))) {
323 ret = -1;
324 } else {
325 DBG_LOW(" -> hit\n");
326 /* Update the HPTE */
327 hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) &
328 ~(HPTE_R_PPP | HPTE_R_N)) |
329 (newpp & (HPTE_R_PPP | HPTE_R_N |
330 HPTE_R_C)));
331 }
332 native_unlock_hpte(hptep);
333 }
334
335 if (flags & HPTE_LOCAL_UPDATE)
336 local = 1;
337 /*
338 * Ensure it is out of the tlb too if it is not a nohpte fault
339 */
340 if (!(flags & HPTE_NOHPTE_UPDATE))
341 tlbie(vpn, bpsize, apsize, ssize, local);
342
343 return ret;
344 }
345
native_hpte_find(unsigned long vpn,int psize,int ssize)346 static long native_hpte_find(unsigned long vpn, int psize, int ssize)
347 {
348 struct hash_pte *hptep;
349 unsigned long hash;
350 unsigned long i;
351 long slot;
352 unsigned long want_v, hpte_v;
353
354 hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, ssize);
355 want_v = hpte_encode_avpn(vpn, psize, ssize);
356
357 /* Bolted mappings are only ever in the primary group */
358 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
359 for (i = 0; i < HPTES_PER_GROUP; i++) {
360 hptep = htab_address + slot;
361 hpte_v = be64_to_cpu(hptep->v);
362 if (cpu_has_feature(CPU_FTR_ARCH_300))
363 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
364
365 if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID))
366 /* HPTE matches */
367 return slot;
368 ++slot;
369 }
370
371 return -1;
372 }
373
374 /*
375 * Update the page protection bits. Intended to be used to create
376 * guard pages for kernel data structures on pages which are bolted
377 * in the HPT. Assumes pages being operated on will not be stolen.
378 *
379 * No need to lock here because we should be the only user.
380 */
native_hpte_updateboltedpp(unsigned long newpp,unsigned long ea,int psize,int ssize)381 static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
382 int psize, int ssize)
383 {
384 unsigned long vpn;
385 unsigned long vsid;
386 long slot;
387 struct hash_pte *hptep;
388
389 vsid = get_kernel_vsid(ea, ssize);
390 vpn = hpt_vpn(ea, vsid, ssize);
391
392 slot = native_hpte_find(vpn, psize, ssize);
393 if (slot == -1)
394 panic("could not find page to bolt\n");
395 hptep = htab_address + slot;
396
397 /* Update the HPTE */
398 hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) &
399 ~(HPTE_R_PPP | HPTE_R_N)) |
400 (newpp & (HPTE_R_PPP | HPTE_R_N)));
401 /*
402 * Ensure it is out of the tlb too. Bolted entries base and
403 * actual page size will be same.
404 */
405 tlbie(vpn, psize, psize, ssize, 0);
406 }
407
native_hpte_invalidate(unsigned long slot,unsigned long vpn,int bpsize,int apsize,int ssize,int local)408 static void native_hpte_invalidate(unsigned long slot, unsigned long vpn,
409 int bpsize, int apsize, int ssize, int local)
410 {
411 struct hash_pte *hptep = htab_address + slot;
412 unsigned long hpte_v;
413 unsigned long want_v;
414 unsigned long flags;
415
416 local_irq_save(flags);
417
418 DBG_LOW(" invalidate(vpn=%016lx, hash: %lx)\n", vpn, slot);
419
420 want_v = hpte_encode_avpn(vpn, bpsize, ssize);
421 native_lock_hpte(hptep);
422 hpte_v = be64_to_cpu(hptep->v);
423 if (cpu_has_feature(CPU_FTR_ARCH_300))
424 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
425
426 /*
427 * We need to invalidate the TLB always because hpte_remove doesn't do
428 * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
429 * random entry from it. When we do that we don't invalidate the TLB
430 * (hpte_remove) because we assume the old translation is still
431 * technically "valid".
432 */
433 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
434 native_unlock_hpte(hptep);
435 else
436 /* Invalidate the hpte. NOTE: this also unlocks it */
437 hptep->v = 0;
438
439 /* Invalidate the TLB */
440 tlbie(vpn, bpsize, apsize, ssize, local);
441
442 local_irq_restore(flags);
443 }
444
445 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
native_hugepage_invalidate(unsigned long vsid,unsigned long addr,unsigned char * hpte_slot_array,int psize,int ssize,int local)446 static void native_hugepage_invalidate(unsigned long vsid,
447 unsigned long addr,
448 unsigned char *hpte_slot_array,
449 int psize, int ssize, int local)
450 {
451 int i;
452 struct hash_pte *hptep;
453 int actual_psize = MMU_PAGE_16M;
454 unsigned int max_hpte_count, valid;
455 unsigned long flags, s_addr = addr;
456 unsigned long hpte_v, want_v, shift;
457 unsigned long hidx, vpn = 0, hash, slot;
458
459 shift = mmu_psize_defs[psize].shift;
460 max_hpte_count = 1U << (PMD_SHIFT - shift);
461
462 local_irq_save(flags);
463 for (i = 0; i < max_hpte_count; i++) {
464 valid = hpte_valid(hpte_slot_array, i);
465 if (!valid)
466 continue;
467 hidx = hpte_hash_index(hpte_slot_array, i);
468
469 /* get the vpn */
470 addr = s_addr + (i * (1ul << shift));
471 vpn = hpt_vpn(addr, vsid, ssize);
472 hash = hpt_hash(vpn, shift, ssize);
473 if (hidx & _PTEIDX_SECONDARY)
474 hash = ~hash;
475
476 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
477 slot += hidx & _PTEIDX_GROUP_IX;
478
479 hptep = htab_address + slot;
480 want_v = hpte_encode_avpn(vpn, psize, ssize);
481 native_lock_hpte(hptep);
482 hpte_v = be64_to_cpu(hptep->v);
483 if (cpu_has_feature(CPU_FTR_ARCH_300))
484 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
485
486 /* Even if we miss, we need to invalidate the TLB */
487 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
488 native_unlock_hpte(hptep);
489 else
490 /* Invalidate the hpte. NOTE: this also unlocks it */
491 hptep->v = 0;
492 /*
493 * We need to do tlb invalidate for all the address, tlbie
494 * instruction compares entry_VA in tlb with the VA specified
495 * here
496 */
497 tlbie(vpn, psize, actual_psize, ssize, local);
498 }
499 local_irq_restore(flags);
500 }
501 #else
native_hugepage_invalidate(unsigned long vsid,unsigned long addr,unsigned char * hpte_slot_array,int psize,int ssize,int local)502 static void native_hugepage_invalidate(unsigned long vsid,
503 unsigned long addr,
504 unsigned char *hpte_slot_array,
505 int psize, int ssize, int local)
506 {
507 WARN(1, "%s called without THP support\n", __func__);
508 }
509 #endif
510
hpte_decode(struct hash_pte * hpte,unsigned long slot,int * psize,int * apsize,int * ssize,unsigned long * vpn)511 static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
512 int *psize, int *apsize, int *ssize, unsigned long *vpn)
513 {
514 unsigned long avpn, pteg, vpi;
515 unsigned long hpte_v = be64_to_cpu(hpte->v);
516 unsigned long hpte_r = be64_to_cpu(hpte->r);
517 unsigned long vsid, seg_off;
518 int size, a_size, shift;
519 /* Look at the 8 bit LP value */
520 unsigned int lp = (hpte_r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
521
522 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
523 hpte_v = hpte_new_to_old_v(hpte_v, hpte_r);
524 hpte_r = hpte_new_to_old_r(hpte_r);
525 }
526 if (!(hpte_v & HPTE_V_LARGE)) {
527 size = MMU_PAGE_4K;
528 a_size = MMU_PAGE_4K;
529 } else {
530 size = hpte_page_sizes[lp] & 0xf;
531 a_size = hpte_page_sizes[lp] >> 4;
532 }
533 /* This works for all page sizes, and for 256M and 1T segments */
534 *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT;
535 shift = mmu_psize_defs[size].shift;
536
537 avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm);
538 pteg = slot / HPTES_PER_GROUP;
539 if (hpte_v & HPTE_V_SECONDARY)
540 pteg = ~pteg;
541
542 switch (*ssize) {
543 case MMU_SEGSIZE_256M:
544 /* We only have 28 - 23 bits of seg_off in avpn */
545 seg_off = (avpn & 0x1f) << 23;
546 vsid = avpn >> 5;
547 /* We can find more bits from the pteg value */
548 if (shift < 23) {
549 vpi = (vsid ^ pteg) & htab_hash_mask;
550 seg_off |= vpi << shift;
551 }
552 *vpn = vsid << (SID_SHIFT - VPN_SHIFT) | seg_off >> VPN_SHIFT;
553 break;
554 case MMU_SEGSIZE_1T:
555 /* We only have 40 - 23 bits of seg_off in avpn */
556 seg_off = (avpn & 0x1ffff) << 23;
557 vsid = avpn >> 17;
558 if (shift < 23) {
559 vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask;
560 seg_off |= vpi << shift;
561 }
562 *vpn = vsid << (SID_SHIFT_1T - VPN_SHIFT) | seg_off >> VPN_SHIFT;
563 break;
564 default:
565 *vpn = size = 0;
566 }
567 *psize = size;
568 *apsize = a_size;
569 }
570
571 /*
572 * clear all mappings on kexec. All cpus are in real mode (or they will
573 * be when they isi), and we are the only one left. We rely on our kernel
574 * mapping being 0xC0's and the hardware ignoring those two real bits.
575 *
576 * This must be called with interrupts disabled.
577 *
578 * Taking the native_tlbie_lock is unsafe here due to the possibility of
579 * lockdep being on. On pre POWER5 hardware, not taking the lock could
580 * cause deadlock. POWER5 and newer not taking the lock is fine. This only
581 * gets called during boot before secondary CPUs have come up and during
582 * crashdump and all bets are off anyway.
583 *
584 * TODO: add batching support when enabled. remember, no dynamic memory here,
585 * although there is the control page available...
586 */
native_hpte_clear(void)587 static void native_hpte_clear(void)
588 {
589 unsigned long vpn = 0;
590 unsigned long slot, slots;
591 struct hash_pte *hptep = htab_address;
592 unsigned long hpte_v;
593 unsigned long pteg_count;
594 int psize, apsize, ssize;
595
596 pteg_count = htab_hash_mask + 1;
597
598 slots = pteg_count * HPTES_PER_GROUP;
599
600 for (slot = 0; slot < slots; slot++, hptep++) {
601 /*
602 * we could lock the pte here, but we are the only cpu
603 * running, right? and for crash dump, we probably
604 * don't want to wait for a maybe bad cpu.
605 */
606 hpte_v = be64_to_cpu(hptep->v);
607
608 /*
609 * Call __tlbie() here rather than tlbie() since we can't take the
610 * native_tlbie_lock.
611 */
612 if (hpte_v & HPTE_V_VALID) {
613 hpte_decode(hptep, slot, &psize, &apsize, &ssize, &vpn);
614 hptep->v = 0;
615 __tlbie(vpn, psize, apsize, ssize);
616 }
617 }
618
619 asm volatile("eieio; tlbsync; ptesync":::"memory");
620 }
621
622 /*
623 * Batched hash table flush, we batch the tlbie's to avoid taking/releasing
624 * the lock all the time
625 */
native_flush_hash_range(unsigned long number,int local)626 static void native_flush_hash_range(unsigned long number, int local)
627 {
628 unsigned long vpn;
629 unsigned long hash, index, hidx, shift, slot;
630 struct hash_pte *hptep;
631 unsigned long hpte_v;
632 unsigned long want_v;
633 unsigned long flags;
634 real_pte_t pte;
635 struct ppc64_tlb_batch *batch = this_cpu_ptr(&ppc64_tlb_batch);
636 unsigned long psize = batch->psize;
637 int ssize = batch->ssize;
638 int i;
639 unsigned int use_local;
640
641 use_local = local && mmu_has_feature(MMU_FTR_TLBIEL) &&
642 mmu_psize_defs[psize].tlbiel && !cxl_ctx_in_use();
643
644 local_irq_save(flags);
645
646 for (i = 0; i < number; i++) {
647 vpn = batch->vpn[i];
648 pte = batch->pte[i];
649
650 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
651 hash = hpt_hash(vpn, shift, ssize);
652 hidx = __rpte_to_hidx(pte, index);
653 if (hidx & _PTEIDX_SECONDARY)
654 hash = ~hash;
655 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
656 slot += hidx & _PTEIDX_GROUP_IX;
657 hptep = htab_address + slot;
658 want_v = hpte_encode_avpn(vpn, psize, ssize);
659 native_lock_hpte(hptep);
660 hpte_v = be64_to_cpu(hptep->v);
661 if (cpu_has_feature(CPU_FTR_ARCH_300))
662 hpte_v = hpte_new_to_old_v(hpte_v,
663 be64_to_cpu(hptep->r));
664 if (!HPTE_V_COMPARE(hpte_v, want_v) ||
665 !(hpte_v & HPTE_V_VALID))
666 native_unlock_hpte(hptep);
667 else
668 hptep->v = 0;
669 } pte_iterate_hashed_end();
670 }
671
672 if (use_local) {
673 asm volatile("ptesync":::"memory");
674 for (i = 0; i < number; i++) {
675 vpn = batch->vpn[i];
676 pte = batch->pte[i];
677
678 pte_iterate_hashed_subpages(pte, psize,
679 vpn, index, shift) {
680 __tlbiel(vpn, psize, psize, ssize);
681 } pte_iterate_hashed_end();
682 }
683 asm volatile("ptesync":::"memory");
684 } else {
685 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
686
687 if (lock_tlbie)
688 raw_spin_lock(&native_tlbie_lock);
689
690 asm volatile("ptesync":::"memory");
691 for (i = 0; i < number; i++) {
692 vpn = batch->vpn[i];
693 pte = batch->pte[i];
694
695 pte_iterate_hashed_subpages(pte, psize,
696 vpn, index, shift) {
697 __tlbie(vpn, psize, psize, ssize);
698 } pte_iterate_hashed_end();
699 }
700 asm volatile("eieio; tlbsync; ptesync":::"memory");
701
702 if (lock_tlbie)
703 raw_spin_unlock(&native_tlbie_lock);
704 }
705
706 local_irq_restore(flags);
707 }
708
native_register_proc_table(unsigned long base,unsigned long page_size,unsigned long table_size)709 static int native_register_proc_table(unsigned long base, unsigned long page_size,
710 unsigned long table_size)
711 {
712 unsigned long patb1 = base << 25; /* VSID */
713
714 patb1 |= (page_size << 5); /* sllp */
715 patb1 |= table_size;
716
717 partition_tb->patb1 = cpu_to_be64(patb1);
718 return 0;
719 }
720
hpte_init_native(void)721 void __init hpte_init_native(void)
722 {
723 mmu_hash_ops.hpte_invalidate = native_hpte_invalidate;
724 mmu_hash_ops.hpte_updatepp = native_hpte_updatepp;
725 mmu_hash_ops.hpte_updateboltedpp = native_hpte_updateboltedpp;
726 mmu_hash_ops.hpte_insert = native_hpte_insert;
727 mmu_hash_ops.hpte_remove = native_hpte_remove;
728 mmu_hash_ops.hpte_clear_all = native_hpte_clear;
729 mmu_hash_ops.flush_hash_range = native_flush_hash_range;
730 mmu_hash_ops.hugepage_invalidate = native_hugepage_invalidate;
731
732 if (cpu_has_feature(CPU_FTR_ARCH_300))
733 register_process_table = native_register_proc_table;
734 }
735