1 /*
2 * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 * Moved from arch/x86/kernel/apic/io_apic.c.
6 * Jiang Liu <jiang.liu@linux.intel.com>
7 * Enable support of hierarchical irqdomains
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13 #include <linux/interrupt.h>
14 #include <linux/init.h>
15 #include <linux/compiler.h>
16 #include <linux/slab.h>
17 #include <asm/irqdomain.h>
18 #include <asm/hw_irq.h>
19 #include <asm/apic.h>
20 #include <asm/i8259.h>
21 #include <asm/desc.h>
22 #include <asm/irq_remapping.h>
23
24 struct apic_chip_data {
25 struct irq_cfg cfg;
26 cpumask_var_t domain;
27 cpumask_var_t old_domain;
28 u8 move_in_progress : 1;
29 };
30
31 struct irq_domain *x86_vector_domain;
32 EXPORT_SYMBOL_GPL(x86_vector_domain);
33 static DEFINE_RAW_SPINLOCK(vector_lock);
34 static cpumask_var_t vector_cpumask, vector_searchmask, searched_cpumask;
35 static struct irq_chip lapic_controller;
36 #ifdef CONFIG_X86_IO_APIC
37 static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY];
38 #endif
39
lock_vector_lock(void)40 void lock_vector_lock(void)
41 {
42 /* Used to the online set of cpus does not change
43 * during assign_irq_vector.
44 */
45 raw_spin_lock(&vector_lock);
46 }
47
unlock_vector_lock(void)48 void unlock_vector_lock(void)
49 {
50 raw_spin_unlock(&vector_lock);
51 }
52
apic_chip_data(struct irq_data * irq_data)53 static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data)
54 {
55 if (!irq_data)
56 return NULL;
57
58 while (irq_data->parent_data)
59 irq_data = irq_data->parent_data;
60
61 return irq_data->chip_data;
62 }
63
irqd_cfg(struct irq_data * irq_data)64 struct irq_cfg *irqd_cfg(struct irq_data *irq_data)
65 {
66 struct apic_chip_data *data = apic_chip_data(irq_data);
67
68 return data ? &data->cfg : NULL;
69 }
70 EXPORT_SYMBOL_GPL(irqd_cfg);
71
irq_cfg(unsigned int irq)72 struct irq_cfg *irq_cfg(unsigned int irq)
73 {
74 return irqd_cfg(irq_get_irq_data(irq));
75 }
76
alloc_apic_chip_data(int node)77 static struct apic_chip_data *alloc_apic_chip_data(int node)
78 {
79 struct apic_chip_data *data;
80
81 data = kzalloc_node(sizeof(*data), GFP_KERNEL, node);
82 if (!data)
83 return NULL;
84 if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node))
85 goto out_data;
86 if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node))
87 goto out_domain;
88 return data;
89 out_domain:
90 free_cpumask_var(data->domain);
91 out_data:
92 kfree(data);
93 return NULL;
94 }
95
free_apic_chip_data(unsigned int virq,struct apic_chip_data * data)96 static void free_apic_chip_data(unsigned int virq, struct apic_chip_data *data)
97 {
98 #ifdef CONFIG_X86_IO_APIC
99 if (virq < nr_legacy_irqs())
100 legacy_irq_data[virq] = NULL;
101 #endif
102 if (data) {
103 free_cpumask_var(data->domain);
104 free_cpumask_var(data->old_domain);
105 kfree(data);
106 }
107 }
108
__assign_irq_vector(int irq,struct apic_chip_data * d,const struct cpumask * mask)109 static int __assign_irq_vector(int irq, struct apic_chip_data *d,
110 const struct cpumask *mask)
111 {
112 /*
113 * NOTE! The local APIC isn't very good at handling
114 * multiple interrupts at the same interrupt level.
115 * As the interrupt level is determined by taking the
116 * vector number and shifting that right by 4, we
117 * want to spread these out a bit so that they don't
118 * all fall in the same interrupt level.
119 *
120 * Also, we've got to be careful not to trash gate
121 * 0x80, because int 0x80 is hm, kind of importantish. ;)
122 */
123 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
124 static int current_offset = VECTOR_OFFSET_START % 16;
125 int cpu, vector;
126
127 /*
128 * If there is still a move in progress or the previous move has not
129 * been cleaned up completely, tell the caller to come back later.
130 */
131 if (d->move_in_progress ||
132 cpumask_intersects(d->old_domain, cpu_online_mask))
133 return -EBUSY;
134
135 /* Only try and allocate irqs on cpus that are present */
136 cpumask_clear(d->old_domain);
137 cpumask_clear(searched_cpumask);
138 cpu = cpumask_first_and(mask, cpu_online_mask);
139 while (cpu < nr_cpu_ids) {
140 int new_cpu, offset;
141
142 /* Get the possible target cpus for @mask/@cpu from the apic */
143 apic->vector_allocation_domain(cpu, vector_cpumask, mask);
144
145 /*
146 * Clear the offline cpus from @vector_cpumask for searching
147 * and verify whether the result overlaps with @mask. If true,
148 * then the call to apic->cpu_mask_to_apicid_and() will
149 * succeed as well. If not, no point in trying to find a
150 * vector in this mask.
151 */
152 cpumask_and(vector_searchmask, vector_cpumask, cpu_online_mask);
153 if (!cpumask_intersects(vector_searchmask, mask))
154 goto next_cpu;
155
156 if (cpumask_subset(vector_cpumask, d->domain)) {
157 if (cpumask_equal(vector_cpumask, d->domain))
158 goto success;
159 /*
160 * Mark the cpus which are not longer in the mask for
161 * cleanup.
162 */
163 cpumask_andnot(d->old_domain, d->domain, vector_cpumask);
164 vector = d->cfg.vector;
165 goto update;
166 }
167
168 vector = current_vector;
169 offset = current_offset;
170 next:
171 vector += 16;
172 if (vector >= first_system_vector) {
173 offset = (offset + 1) % 16;
174 vector = FIRST_EXTERNAL_VECTOR + offset;
175 }
176
177 /* If the search wrapped around, try the next cpu */
178 if (unlikely(current_vector == vector))
179 goto next_cpu;
180
181 if (test_bit(vector, used_vectors))
182 goto next;
183
184 for_each_cpu(new_cpu, vector_searchmask) {
185 if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector]))
186 goto next;
187 }
188 /* Found one! */
189 current_vector = vector;
190 current_offset = offset;
191 /* Schedule the old vector for cleanup on all cpus */
192 if (d->cfg.vector)
193 cpumask_copy(d->old_domain, d->domain);
194 for_each_cpu(new_cpu, vector_searchmask)
195 per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq);
196 goto update;
197
198 next_cpu:
199 /*
200 * We exclude the current @vector_cpumask from the requested
201 * @mask and try again with the next online cpu in the
202 * result. We cannot modify @mask, so we use @vector_cpumask
203 * as a temporary buffer here as it will be reassigned when
204 * calling apic->vector_allocation_domain() above.
205 */
206 cpumask_or(searched_cpumask, searched_cpumask, vector_cpumask);
207 cpumask_andnot(vector_cpumask, mask, searched_cpumask);
208 cpu = cpumask_first_and(vector_cpumask, cpu_online_mask);
209 continue;
210 }
211 return -ENOSPC;
212
213 update:
214 /*
215 * Exclude offline cpus from the cleanup mask and set the
216 * move_in_progress flag when the result is not empty.
217 */
218 cpumask_and(d->old_domain, d->old_domain, cpu_online_mask);
219 d->move_in_progress = !cpumask_empty(d->old_domain);
220 d->cfg.old_vector = d->move_in_progress ? d->cfg.vector : 0;
221 d->cfg.vector = vector;
222 cpumask_copy(d->domain, vector_cpumask);
223 success:
224 /*
225 * Cache destination APIC IDs into cfg->dest_apicid. This cannot fail
226 * as we already established, that mask & d->domain & cpu_online_mask
227 * is not empty.
228 */
229 BUG_ON(apic->cpu_mask_to_apicid_and(mask, d->domain,
230 &d->cfg.dest_apicid));
231 return 0;
232 }
233
assign_irq_vector(int irq,struct apic_chip_data * data,const struct cpumask * mask)234 static int assign_irq_vector(int irq, struct apic_chip_data *data,
235 const struct cpumask *mask)
236 {
237 int err;
238 unsigned long flags;
239
240 raw_spin_lock_irqsave(&vector_lock, flags);
241 err = __assign_irq_vector(irq, data, mask);
242 raw_spin_unlock_irqrestore(&vector_lock, flags);
243 return err;
244 }
245
assign_irq_vector_policy(int irq,int node,struct apic_chip_data * data,struct irq_alloc_info * info)246 static int assign_irq_vector_policy(int irq, int node,
247 struct apic_chip_data *data,
248 struct irq_alloc_info *info)
249 {
250 if (info && info->mask)
251 return assign_irq_vector(irq, data, info->mask);
252 if (node != NUMA_NO_NODE &&
253 assign_irq_vector(irq, data, cpumask_of_node(node)) == 0)
254 return 0;
255 return assign_irq_vector(irq, data, apic->target_cpus());
256 }
257
clear_irq_vector(int irq,struct apic_chip_data * data)258 static void clear_irq_vector(int irq, struct apic_chip_data *data)
259 {
260 struct irq_desc *desc;
261 int cpu, vector;
262
263 if (!data->cfg.vector)
264 return;
265
266 vector = data->cfg.vector;
267 for_each_cpu_and(cpu, data->domain, cpu_online_mask)
268 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
269
270 data->cfg.vector = 0;
271 cpumask_clear(data->domain);
272
273 /*
274 * If move is in progress or the old_domain mask is not empty,
275 * i.e. the cleanup IPI has not been processed yet, we need to remove
276 * the old references to desc from all cpus vector tables.
277 */
278 if (!data->move_in_progress && cpumask_empty(data->old_domain))
279 return;
280
281 desc = irq_to_desc(irq);
282 for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) {
283 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
284 vector++) {
285 if (per_cpu(vector_irq, cpu)[vector] != desc)
286 continue;
287 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
288 break;
289 }
290 }
291 data->move_in_progress = 0;
292 }
293
init_irq_alloc_info(struct irq_alloc_info * info,const struct cpumask * mask)294 void init_irq_alloc_info(struct irq_alloc_info *info,
295 const struct cpumask *mask)
296 {
297 memset(info, 0, sizeof(*info));
298 info->mask = mask;
299 }
300
copy_irq_alloc_info(struct irq_alloc_info * dst,struct irq_alloc_info * src)301 void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
302 {
303 if (src)
304 *dst = *src;
305 else
306 memset(dst, 0, sizeof(*dst));
307 }
308
x86_vector_free_irqs(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)309 static void x86_vector_free_irqs(struct irq_domain *domain,
310 unsigned int virq, unsigned int nr_irqs)
311 {
312 struct apic_chip_data *apic_data;
313 struct irq_data *irq_data;
314 unsigned long flags;
315 int i;
316
317 for (i = 0; i < nr_irqs; i++) {
318 irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i);
319 if (irq_data && irq_data->chip_data) {
320 raw_spin_lock_irqsave(&vector_lock, flags);
321 clear_irq_vector(virq + i, irq_data->chip_data);
322 apic_data = irq_data->chip_data;
323 irq_domain_reset_irq_data(irq_data);
324 raw_spin_unlock_irqrestore(&vector_lock, flags);
325 free_apic_chip_data(virq + i, apic_data);
326 }
327 }
328 }
329
x86_vector_alloc_irqs(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)330 static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
331 unsigned int nr_irqs, void *arg)
332 {
333 struct irq_alloc_info *info = arg;
334 struct apic_chip_data *data;
335 struct irq_data *irq_data;
336 int i, err, node;
337
338 if (disable_apic)
339 return -ENXIO;
340
341 /* Currently vector allocator can't guarantee contiguous allocations */
342 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
343 return -ENOSYS;
344
345 for (i = 0; i < nr_irqs; i++) {
346 irq_data = irq_domain_get_irq_data(domain, virq + i);
347 BUG_ON(!irq_data);
348 node = irq_data_get_node(irq_data);
349 #ifdef CONFIG_X86_IO_APIC
350 if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i])
351 data = legacy_irq_data[virq + i];
352 else
353 #endif
354 data = alloc_apic_chip_data(node);
355 if (!data) {
356 err = -ENOMEM;
357 goto error;
358 }
359
360 irq_data->chip = &lapic_controller;
361 irq_data->chip_data = data;
362 irq_data->hwirq = virq + i;
363 err = assign_irq_vector_policy(virq + i, node, data, info);
364 if (err) {
365 irq_data->chip_data = NULL;
366 free_apic_chip_data(virq + i, data);
367 goto error;
368 }
369 }
370
371 return 0;
372
373 error:
374 x86_vector_free_irqs(domain, virq, i);
375 return err;
376 }
377
378 static const struct irq_domain_ops x86_vector_domain_ops = {
379 .alloc = x86_vector_alloc_irqs,
380 .free = x86_vector_free_irqs,
381 };
382
arch_probe_nr_irqs(void)383 int __init arch_probe_nr_irqs(void)
384 {
385 int nr;
386
387 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
388 nr_irqs = NR_VECTORS * nr_cpu_ids;
389
390 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
391 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
392 /*
393 * for MSI and HT dyn irq
394 */
395 if (gsi_top <= NR_IRQS_LEGACY)
396 nr += 8 * nr_cpu_ids;
397 else
398 nr += gsi_top * 16;
399 #endif
400 if (nr < nr_irqs)
401 nr_irqs = nr;
402
403 /*
404 * We don't know if PIC is present at this point so we need to do
405 * probe() to get the right number of legacy IRQs.
406 */
407 return legacy_pic->probe();
408 }
409
410 #ifdef CONFIG_X86_IO_APIC
init_legacy_irqs(void)411 static void init_legacy_irqs(void)
412 {
413 int i, node = cpu_to_node(0);
414 struct apic_chip_data *data;
415
416 /*
417 * For legacy IRQ's, start with assigning irq0 to irq15 to
418 * ISA_IRQ_VECTOR(i) for all cpu's.
419 */
420 for (i = 0; i < nr_legacy_irqs(); i++) {
421 data = legacy_irq_data[i] = alloc_apic_chip_data(node);
422 BUG_ON(!data);
423
424 data->cfg.vector = ISA_IRQ_VECTOR(i);
425 cpumask_setall(data->domain);
426 irq_set_chip_data(i, data);
427 }
428 }
429 #else
init_legacy_irqs(void)430 static void init_legacy_irqs(void) { }
431 #endif
432
arch_early_irq_init(void)433 int __init arch_early_irq_init(void)
434 {
435 init_legacy_irqs();
436
437 x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops,
438 NULL);
439 BUG_ON(x86_vector_domain == NULL);
440 irq_set_default_host(x86_vector_domain);
441
442 arch_init_msi_domain(x86_vector_domain);
443 arch_init_htirq_domain(x86_vector_domain);
444
445 BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL));
446 BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL));
447 BUG_ON(!alloc_cpumask_var(&searched_cpumask, GFP_KERNEL));
448
449 return arch_early_ioapic_init();
450 }
451
452 /* Initialize vector_irq on a new cpu */
__setup_vector_irq(int cpu)453 static void __setup_vector_irq(int cpu)
454 {
455 struct apic_chip_data *data;
456 struct irq_desc *desc;
457 int irq, vector;
458
459 /* Mark the inuse vectors */
460 for_each_irq_desc(irq, desc) {
461 struct irq_data *idata = irq_desc_get_irq_data(desc);
462
463 data = apic_chip_data(idata);
464 if (!data || !cpumask_test_cpu(cpu, data->domain))
465 continue;
466 vector = data->cfg.vector;
467 per_cpu(vector_irq, cpu)[vector] = desc;
468 }
469 /* Mark the free vectors */
470 for (vector = 0; vector < NR_VECTORS; ++vector) {
471 desc = per_cpu(vector_irq, cpu)[vector];
472 if (IS_ERR_OR_NULL(desc))
473 continue;
474
475 data = apic_chip_data(irq_desc_get_irq_data(desc));
476 if (!cpumask_test_cpu(cpu, data->domain))
477 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
478 }
479 }
480
481 /*
482 * Setup the vector to irq mappings. Must be called with vector_lock held.
483 */
setup_vector_irq(int cpu)484 void setup_vector_irq(int cpu)
485 {
486 int irq;
487
488 lockdep_assert_held(&vector_lock);
489 /*
490 * On most of the platforms, legacy PIC delivers the interrupts on the
491 * boot cpu. But there are certain platforms where PIC interrupts are
492 * delivered to multiple cpu's. If the legacy IRQ is handled by the
493 * legacy PIC, for the new cpu that is coming online, setup the static
494 * legacy vector to irq mapping:
495 */
496 for (irq = 0; irq < nr_legacy_irqs(); irq++)
497 per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq_to_desc(irq);
498
499 __setup_vector_irq(cpu);
500 }
501
apic_retrigger_irq(struct irq_data * irq_data)502 static int apic_retrigger_irq(struct irq_data *irq_data)
503 {
504 struct apic_chip_data *data = apic_chip_data(irq_data);
505 unsigned long flags;
506 int cpu;
507
508 raw_spin_lock_irqsave(&vector_lock, flags);
509 cpu = cpumask_first_and(data->domain, cpu_online_mask);
510 apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector);
511 raw_spin_unlock_irqrestore(&vector_lock, flags);
512
513 return 1;
514 }
515
apic_ack_edge(struct irq_data * data)516 void apic_ack_edge(struct irq_data *data)
517 {
518 irq_complete_move(irqd_cfg(data));
519 irq_move_irq(data);
520 ack_APIC_irq();
521 }
522
apic_set_affinity(struct irq_data * irq_data,const struct cpumask * dest,bool force)523 static int apic_set_affinity(struct irq_data *irq_data,
524 const struct cpumask *dest, bool force)
525 {
526 struct apic_chip_data *data = irq_data->chip_data;
527 int err, irq = irq_data->irq;
528
529 if (!IS_ENABLED(CONFIG_SMP))
530 return -EPERM;
531
532 if (!cpumask_intersects(dest, cpu_online_mask))
533 return -EINVAL;
534
535 err = assign_irq_vector(irq, data, dest);
536 return err ? err : IRQ_SET_MASK_OK;
537 }
538
539 static struct irq_chip lapic_controller = {
540 .irq_ack = apic_ack_edge,
541 .irq_set_affinity = apic_set_affinity,
542 .irq_retrigger = apic_retrigger_irq,
543 };
544
545 #ifdef CONFIG_SMP
__send_cleanup_vector(struct apic_chip_data * data)546 static void __send_cleanup_vector(struct apic_chip_data *data)
547 {
548 raw_spin_lock(&vector_lock);
549 cpumask_and(data->old_domain, data->old_domain, cpu_online_mask);
550 data->move_in_progress = 0;
551 if (!cpumask_empty(data->old_domain))
552 apic->send_IPI_mask(data->old_domain, IRQ_MOVE_CLEANUP_VECTOR);
553 raw_spin_unlock(&vector_lock);
554 }
555
send_cleanup_vector(struct irq_cfg * cfg)556 void send_cleanup_vector(struct irq_cfg *cfg)
557 {
558 struct apic_chip_data *data;
559
560 data = container_of(cfg, struct apic_chip_data, cfg);
561 if (data->move_in_progress)
562 __send_cleanup_vector(data);
563 }
564
smp_irq_move_cleanup_interrupt(void)565 asmlinkage __visible void __irq_entry smp_irq_move_cleanup_interrupt(void)
566 {
567 unsigned vector, me;
568
569 entering_ack_irq();
570
571 /* Prevent vectors vanishing under us */
572 raw_spin_lock(&vector_lock);
573
574 me = smp_processor_id();
575 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
576 struct apic_chip_data *data;
577 struct irq_desc *desc;
578 unsigned int irr;
579
580 retry:
581 desc = __this_cpu_read(vector_irq[vector]);
582 if (IS_ERR_OR_NULL(desc))
583 continue;
584
585 if (!raw_spin_trylock(&desc->lock)) {
586 raw_spin_unlock(&vector_lock);
587 cpu_relax();
588 raw_spin_lock(&vector_lock);
589 goto retry;
590 }
591
592 data = apic_chip_data(irq_desc_get_irq_data(desc));
593 if (!data)
594 goto unlock;
595
596 /*
597 * Nothing to cleanup if irq migration is in progress
598 * or this cpu is not set in the cleanup mask.
599 */
600 if (data->move_in_progress ||
601 !cpumask_test_cpu(me, data->old_domain))
602 goto unlock;
603
604 /*
605 * We have two cases to handle here:
606 * 1) vector is unchanged but the target mask got reduced
607 * 2) vector and the target mask has changed
608 *
609 * #1 is obvious, but in #2 we have two vectors with the same
610 * irq descriptor: the old and the new vector. So we need to
611 * make sure that we only cleanup the old vector. The new
612 * vector has the current @vector number in the config and
613 * this cpu is part of the target mask. We better leave that
614 * one alone.
615 */
616 if (vector == data->cfg.vector &&
617 cpumask_test_cpu(me, data->domain))
618 goto unlock;
619
620 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
621 /*
622 * Check if the vector that needs to be cleanedup is
623 * registered at the cpu's IRR. If so, then this is not
624 * the best time to clean it up. Lets clean it up in the
625 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
626 * to myself.
627 */
628 if (irr & (1 << (vector % 32))) {
629 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
630 goto unlock;
631 }
632 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
633 cpumask_clear_cpu(me, data->old_domain);
634 unlock:
635 raw_spin_unlock(&desc->lock);
636 }
637
638 raw_spin_unlock(&vector_lock);
639
640 exiting_irq();
641 }
642
__irq_complete_move(struct irq_cfg * cfg,unsigned vector)643 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
644 {
645 unsigned me;
646 struct apic_chip_data *data;
647
648 data = container_of(cfg, struct apic_chip_data, cfg);
649 if (likely(!data->move_in_progress))
650 return;
651
652 me = smp_processor_id();
653 if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain))
654 __send_cleanup_vector(data);
655 }
656
irq_complete_move(struct irq_cfg * cfg)657 void irq_complete_move(struct irq_cfg *cfg)
658 {
659 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
660 }
661
662 /*
663 * Called from fixup_irqs() with @desc->lock held and interrupts disabled.
664 */
irq_force_complete_move(struct irq_desc * desc)665 void irq_force_complete_move(struct irq_desc *desc)
666 {
667 struct irq_data *irqdata;
668 struct apic_chip_data *data;
669 struct irq_cfg *cfg;
670 unsigned int cpu;
671
672 /*
673 * The function is called for all descriptors regardless of which
674 * irqdomain they belong to. For example if an IRQ is provided by
675 * an irq_chip as part of a GPIO driver, the chip data for that
676 * descriptor is specific to the irq_chip in question.
677 *
678 * Check first that the chip_data is what we expect
679 * (apic_chip_data) before touching it any further.
680 */
681 irqdata = irq_domain_get_irq_data(x86_vector_domain,
682 irq_desc_get_irq(desc));
683 if (!irqdata)
684 return;
685
686 data = apic_chip_data(irqdata);
687 cfg = data ? &data->cfg : NULL;
688
689 if (!cfg)
690 return;
691
692 /*
693 * This is tricky. If the cleanup of @data->old_domain has not been
694 * done yet, then the following setaffinity call will fail with
695 * -EBUSY. This can leave the interrupt in a stale state.
696 *
697 * All CPUs are stuck in stop machine with interrupts disabled so
698 * calling __irq_complete_move() would be completely pointless.
699 */
700 raw_spin_lock(&vector_lock);
701 /*
702 * Clean out all offline cpus (including the outgoing one) from the
703 * old_domain mask.
704 */
705 cpumask_and(data->old_domain, data->old_domain, cpu_online_mask);
706
707 /*
708 * If move_in_progress is cleared and the old_domain mask is empty,
709 * then there is nothing to cleanup. fixup_irqs() will take care of
710 * the stale vectors on the outgoing cpu.
711 */
712 if (!data->move_in_progress && cpumask_empty(data->old_domain)) {
713 raw_spin_unlock(&vector_lock);
714 return;
715 }
716
717 /*
718 * 1) The interrupt is in move_in_progress state. That means that we
719 * have not seen an interrupt since the io_apic was reprogrammed to
720 * the new vector.
721 *
722 * 2) The interrupt has fired on the new vector, but the cleanup IPIs
723 * have not been processed yet.
724 */
725 if (data->move_in_progress) {
726 /*
727 * In theory there is a race:
728 *
729 * set_ioapic(new_vector) <-- Interrupt is raised before update
730 * is effective, i.e. it's raised on
731 * the old vector.
732 *
733 * So if the target cpu cannot handle that interrupt before
734 * the old vector is cleaned up, we get a spurious interrupt
735 * and in the worst case the ioapic irq line becomes stale.
736 *
737 * But in case of cpu hotplug this should be a non issue
738 * because if the affinity update happens right before all
739 * cpus rendevouz in stop machine, there is no way that the
740 * interrupt can be blocked on the target cpu because all cpus
741 * loops first with interrupts enabled in stop machine, so the
742 * old vector is not yet cleaned up when the interrupt fires.
743 *
744 * So the only way to run into this issue is if the delivery
745 * of the interrupt on the apic/system bus would be delayed
746 * beyond the point where the target cpu disables interrupts
747 * in stop machine. I doubt that it can happen, but at least
748 * there is a theroretical chance. Virtualization might be
749 * able to expose this, but AFAICT the IOAPIC emulation is not
750 * as stupid as the real hardware.
751 *
752 * Anyway, there is nothing we can do about that at this point
753 * w/o refactoring the whole fixup_irq() business completely.
754 * We print at least the irq number and the old vector number,
755 * so we have the necessary information when a problem in that
756 * area arises.
757 */
758 pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n",
759 irqdata->irq, cfg->old_vector);
760 }
761 /*
762 * If old_domain is not empty, then other cpus still have the irq
763 * descriptor set in their vector array. Clean it up.
764 */
765 for_each_cpu(cpu, data->old_domain)
766 per_cpu(vector_irq, cpu)[cfg->old_vector] = VECTOR_UNUSED;
767
768 /* Cleanup the left overs of the (half finished) move */
769 cpumask_clear(data->old_domain);
770 data->move_in_progress = 0;
771 raw_spin_unlock(&vector_lock);
772 }
773 #endif
774
print_APIC_field(int base)775 static void __init print_APIC_field(int base)
776 {
777 int i;
778
779 printk(KERN_DEBUG);
780
781 for (i = 0; i < 8; i++)
782 pr_cont("%08x", apic_read(base + i*0x10));
783
784 pr_cont("\n");
785 }
786
print_local_APIC(void * dummy)787 static void __init print_local_APIC(void *dummy)
788 {
789 unsigned int i, v, ver, maxlvt;
790 u64 icr;
791
792 pr_debug("printing local APIC contents on CPU#%d/%d:\n",
793 smp_processor_id(), hard_smp_processor_id());
794 v = apic_read(APIC_ID);
795 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id());
796 v = apic_read(APIC_LVR);
797 pr_info("... APIC VERSION: %08x\n", v);
798 ver = GET_APIC_VERSION(v);
799 maxlvt = lapic_get_maxlvt();
800
801 v = apic_read(APIC_TASKPRI);
802 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
803
804 /* !82489DX */
805 if (APIC_INTEGRATED(ver)) {
806 if (!APIC_XAPIC(ver)) {
807 v = apic_read(APIC_ARBPRI);
808 pr_debug("... APIC ARBPRI: %08x (%02x)\n",
809 v, v & APIC_ARBPRI_MASK);
810 }
811 v = apic_read(APIC_PROCPRI);
812 pr_debug("... APIC PROCPRI: %08x\n", v);
813 }
814
815 /*
816 * Remote read supported only in the 82489DX and local APIC for
817 * Pentium processors.
818 */
819 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
820 v = apic_read(APIC_RRR);
821 pr_debug("... APIC RRR: %08x\n", v);
822 }
823
824 v = apic_read(APIC_LDR);
825 pr_debug("... APIC LDR: %08x\n", v);
826 if (!x2apic_enabled()) {
827 v = apic_read(APIC_DFR);
828 pr_debug("... APIC DFR: %08x\n", v);
829 }
830 v = apic_read(APIC_SPIV);
831 pr_debug("... APIC SPIV: %08x\n", v);
832
833 pr_debug("... APIC ISR field:\n");
834 print_APIC_field(APIC_ISR);
835 pr_debug("... APIC TMR field:\n");
836 print_APIC_field(APIC_TMR);
837 pr_debug("... APIC IRR field:\n");
838 print_APIC_field(APIC_IRR);
839
840 /* !82489DX */
841 if (APIC_INTEGRATED(ver)) {
842 /* Due to the Pentium erratum 3AP. */
843 if (maxlvt > 3)
844 apic_write(APIC_ESR, 0);
845
846 v = apic_read(APIC_ESR);
847 pr_debug("... APIC ESR: %08x\n", v);
848 }
849
850 icr = apic_icr_read();
851 pr_debug("... APIC ICR: %08x\n", (u32)icr);
852 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
853
854 v = apic_read(APIC_LVTT);
855 pr_debug("... APIC LVTT: %08x\n", v);
856
857 if (maxlvt > 3) {
858 /* PC is LVT#4. */
859 v = apic_read(APIC_LVTPC);
860 pr_debug("... APIC LVTPC: %08x\n", v);
861 }
862 v = apic_read(APIC_LVT0);
863 pr_debug("... APIC LVT0: %08x\n", v);
864 v = apic_read(APIC_LVT1);
865 pr_debug("... APIC LVT1: %08x\n", v);
866
867 if (maxlvt > 2) {
868 /* ERR is LVT#3. */
869 v = apic_read(APIC_LVTERR);
870 pr_debug("... APIC LVTERR: %08x\n", v);
871 }
872
873 v = apic_read(APIC_TMICT);
874 pr_debug("... APIC TMICT: %08x\n", v);
875 v = apic_read(APIC_TMCCT);
876 pr_debug("... APIC TMCCT: %08x\n", v);
877 v = apic_read(APIC_TDCR);
878 pr_debug("... APIC TDCR: %08x\n", v);
879
880 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
881 v = apic_read(APIC_EFEAT);
882 maxlvt = (v >> 16) & 0xff;
883 pr_debug("... APIC EFEAT: %08x\n", v);
884 v = apic_read(APIC_ECTRL);
885 pr_debug("... APIC ECTRL: %08x\n", v);
886 for (i = 0; i < maxlvt; i++) {
887 v = apic_read(APIC_EILVTn(i));
888 pr_debug("... APIC EILVT%d: %08x\n", i, v);
889 }
890 }
891 pr_cont("\n");
892 }
893
print_local_APICs(int maxcpu)894 static void __init print_local_APICs(int maxcpu)
895 {
896 int cpu;
897
898 if (!maxcpu)
899 return;
900
901 preempt_disable();
902 for_each_online_cpu(cpu) {
903 if (cpu >= maxcpu)
904 break;
905 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
906 }
907 preempt_enable();
908 }
909
print_PIC(void)910 static void __init print_PIC(void)
911 {
912 unsigned int v;
913 unsigned long flags;
914
915 if (!nr_legacy_irqs())
916 return;
917
918 pr_debug("\nprinting PIC contents\n");
919
920 raw_spin_lock_irqsave(&i8259A_lock, flags);
921
922 v = inb(0xa1) << 8 | inb(0x21);
923 pr_debug("... PIC IMR: %04x\n", v);
924
925 v = inb(0xa0) << 8 | inb(0x20);
926 pr_debug("... PIC IRR: %04x\n", v);
927
928 outb(0x0b, 0xa0);
929 outb(0x0b, 0x20);
930 v = inb(0xa0) << 8 | inb(0x20);
931 outb(0x0a, 0xa0);
932 outb(0x0a, 0x20);
933
934 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
935
936 pr_debug("... PIC ISR: %04x\n", v);
937
938 v = inb(0x4d1) << 8 | inb(0x4d0);
939 pr_debug("... PIC ELCR: %04x\n", v);
940 }
941
942 static int show_lapic __initdata = 1;
setup_show_lapic(char * arg)943 static __init int setup_show_lapic(char *arg)
944 {
945 int num = -1;
946
947 if (strcmp(arg, "all") == 0) {
948 show_lapic = CONFIG_NR_CPUS;
949 } else {
950 get_option(&arg, &num);
951 if (num >= 0)
952 show_lapic = num;
953 }
954
955 return 1;
956 }
957 __setup("show_lapic=", setup_show_lapic);
958
print_ICs(void)959 static int __init print_ICs(void)
960 {
961 if (apic_verbosity == APIC_QUIET)
962 return 0;
963
964 print_PIC();
965
966 /* don't print out if apic is not there */
967 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
968 return 0;
969
970 print_local_APICs(show_lapic);
971 print_IO_APICs();
972
973 return 0;
974 }
975
976 late_initcall(print_ICs);
977