1 /*
2 * intel_pmic_crc.c - Intel CrystalCove PMIC operation region driver
3 *
4 * Copyright (C) 2014 Intel Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/init.h>
17 #include <linux/acpi.h>
18 #include <linux/mfd/intel_soc_pmic.h>
19 #include <linux/regmap.h>
20 #include <linux/platform_device.h>
21 #include "intel_pmic.h"
22
23 #define PWR_SOURCE_SELECT BIT(1)
24
25 #define PMIC_A0LOCK_REG 0xc5
26
27 static struct pmic_table power_table[] = {
28 {
29 .address = 0x24,
30 .reg = 0x66,
31 .bit = 0x00,
32 },
33 {
34 .address = 0x48,
35 .reg = 0x5d,
36 .bit = 0x00,
37 },
38 };
39
40 static struct pmic_table thermal_table[] = {
41 {
42 .address = 0x00,
43 .reg = 0x75
44 },
45 {
46 .address = 0x04,
47 .reg = 0x95
48 },
49 {
50 .address = 0x08,
51 .reg = 0x97
52 },
53 {
54 .address = 0x0c,
55 .reg = 0x77
56 },
57 {
58 .address = 0x10,
59 .reg = 0x9a
60 },
61 {
62 .address = 0x14,
63 .reg = 0x9c
64 },
65 {
66 .address = 0x18,
67 .reg = 0x79
68 },
69 {
70 .address = 0x1c,
71 .reg = 0x9f
72 },
73 {
74 .address = 0x20,
75 .reg = 0xa1
76 },
77 {
78 .address = 0x48,
79 .reg = 0x94
80 },
81 {
82 .address = 0x4c,
83 .reg = 0x99
84 },
85 {
86 .address = 0x50,
87 .reg = 0x9e
88 },
89 };
90
intel_crc_pmic_get_power(struct regmap * regmap,int reg,int bit,u64 * value)91 static int intel_crc_pmic_get_power(struct regmap *regmap, int reg,
92 int bit, u64 *value)
93 {
94 int data;
95
96 if (regmap_read(regmap, reg, &data))
97 return -EIO;
98
99 *value = (data & PWR_SOURCE_SELECT) && (data & BIT(bit)) ? 1 : 0;
100 return 0;
101 }
102
intel_crc_pmic_update_power(struct regmap * regmap,int reg,int bit,bool on)103 static int intel_crc_pmic_update_power(struct regmap *regmap, int reg,
104 int bit, bool on)
105 {
106 int data;
107
108 if (regmap_read(regmap, reg, &data))
109 return -EIO;
110
111 if (on) {
112 data |= PWR_SOURCE_SELECT | BIT(bit);
113 } else {
114 data &= ~BIT(bit);
115 data |= PWR_SOURCE_SELECT;
116 }
117
118 if (regmap_write(regmap, reg, data))
119 return -EIO;
120 return 0;
121 }
122
intel_crc_pmic_get_raw_temp(struct regmap * regmap,int reg)123 static int intel_crc_pmic_get_raw_temp(struct regmap *regmap, int reg)
124 {
125 int temp_l, temp_h;
126
127 /*
128 * Raw temperature value is 10bits: 8bits in reg
129 * and 2bits in reg-1: bit0,1
130 */
131 if (regmap_read(regmap, reg, &temp_l) ||
132 regmap_read(regmap, reg - 1, &temp_h))
133 return -EIO;
134
135 return temp_l | (temp_h & 0x3) << 8;
136 }
137
intel_crc_pmic_update_aux(struct regmap * regmap,int reg,int raw)138 static int intel_crc_pmic_update_aux(struct regmap *regmap, int reg, int raw)
139 {
140 return regmap_write(regmap, reg, raw) ||
141 regmap_update_bits(regmap, reg - 1, 0x3, raw >> 8) ? -EIO : 0;
142 }
143
intel_crc_pmic_get_policy(struct regmap * regmap,int reg,int bit,u64 * value)144 static int intel_crc_pmic_get_policy(struct regmap *regmap,
145 int reg, int bit, u64 *value)
146 {
147 int pen;
148
149 if (regmap_read(regmap, reg, &pen))
150 return -EIO;
151 *value = pen >> 7;
152 return 0;
153 }
154
intel_crc_pmic_update_policy(struct regmap * regmap,int reg,int bit,int enable)155 static int intel_crc_pmic_update_policy(struct regmap *regmap,
156 int reg, int bit, int enable)
157 {
158 int alert0;
159
160 /* Update to policy enable bit requires unlocking a0lock */
161 if (regmap_read(regmap, PMIC_A0LOCK_REG, &alert0))
162 return -EIO;
163
164 if (regmap_update_bits(regmap, PMIC_A0LOCK_REG, 0x01, 0))
165 return -EIO;
166
167 if (regmap_update_bits(regmap, reg, 0x80, enable << 7))
168 return -EIO;
169
170 /* restore alert0 */
171 if (regmap_write(regmap, PMIC_A0LOCK_REG, alert0))
172 return -EIO;
173
174 return 0;
175 }
176
177 static struct intel_pmic_opregion_data intel_crc_pmic_opregion_data = {
178 .get_power = intel_crc_pmic_get_power,
179 .update_power = intel_crc_pmic_update_power,
180 .get_raw_temp = intel_crc_pmic_get_raw_temp,
181 .update_aux = intel_crc_pmic_update_aux,
182 .get_policy = intel_crc_pmic_get_policy,
183 .update_policy = intel_crc_pmic_update_policy,
184 .power_table = power_table,
185 .power_table_count= ARRAY_SIZE(power_table),
186 .thermal_table = thermal_table,
187 .thermal_table_count = ARRAY_SIZE(thermal_table),
188 };
189
intel_crc_pmic_opregion_probe(struct platform_device * pdev)190 static int intel_crc_pmic_opregion_probe(struct platform_device *pdev)
191 {
192 struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
193 return intel_pmic_install_opregion_handler(&pdev->dev,
194 ACPI_HANDLE(pdev->dev.parent), pmic->regmap,
195 &intel_crc_pmic_opregion_data);
196 }
197
198 static struct platform_driver intel_crc_pmic_opregion_driver = {
199 .probe = intel_crc_pmic_opregion_probe,
200 .driver = {
201 .name = "crystal_cove_pmic",
202 },
203 };
204
intel_crc_pmic_opregion_driver_init(void)205 static int __init intel_crc_pmic_opregion_driver_init(void)
206 {
207 return platform_driver_register(&intel_crc_pmic_opregion_driver);
208 }
209 device_initcall(intel_crc_pmic_opregion_driver_init);
210