1 /*
2 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/export.h>
15 #include <linux/module.h>
16 #include <linux/regmap.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk-provider.h>
19 #include <linux/reset-controller.h>
20 #include <linux/of.h>
21
22 #include "common.h"
23 #include "clk-rcg.h"
24 #include "clk-regmap.h"
25 #include "reset.h"
26 #include "gdsc.h"
27
28 struct qcom_cc {
29 struct qcom_reset_controller reset;
30 struct clk_regmap **rclks;
31 size_t num_rclks;
32 };
33
34 const
qcom_find_freq(const struct freq_tbl * f,unsigned long rate)35 struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
36 {
37 if (!f)
38 return NULL;
39
40 for (; f->freq; f++)
41 if (rate <= f->freq)
42 return f;
43
44 /* Default to our fastest rate */
45 return f - 1;
46 }
47 EXPORT_SYMBOL_GPL(qcom_find_freq);
48
qcom_find_src_index(struct clk_hw * hw,const struct parent_map * map,u8 src)49 int qcom_find_src_index(struct clk_hw *hw, const struct parent_map *map, u8 src)
50 {
51 int i, num_parents = clk_hw_get_num_parents(hw);
52
53 for (i = 0; i < num_parents; i++)
54 if (src == map[i].src)
55 return i;
56
57 return -ENOENT;
58 }
59 EXPORT_SYMBOL_GPL(qcom_find_src_index);
60
61 struct regmap *
qcom_cc_map(struct platform_device * pdev,const struct qcom_cc_desc * desc)62 qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
63 {
64 void __iomem *base;
65 struct resource *res;
66 struct device *dev = &pdev->dev;
67
68 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
69 base = devm_ioremap_resource(dev, res);
70 if (IS_ERR(base))
71 return ERR_CAST(base);
72
73 return devm_regmap_init_mmio(dev, base, desc->config);
74 }
75 EXPORT_SYMBOL_GPL(qcom_cc_map);
76
qcom_cc_del_clk_provider(void * data)77 static void qcom_cc_del_clk_provider(void *data)
78 {
79 of_clk_del_provider(data);
80 }
81
qcom_cc_reset_unregister(void * data)82 static void qcom_cc_reset_unregister(void *data)
83 {
84 reset_controller_unregister(data);
85 }
86
qcom_cc_gdsc_unregister(void * data)87 static void qcom_cc_gdsc_unregister(void *data)
88 {
89 gdsc_unregister(data);
90 }
91
92 /*
93 * Backwards compatibility with old DTs. Register a pass-through factor 1/1
94 * clock to translate 'path' clk into 'name' clk and regsiter the 'path'
95 * clk as a fixed rate clock if it isn't present.
96 */
_qcom_cc_register_board_clk(struct device * dev,const char * path,const char * name,unsigned long rate,bool add_factor)97 static int _qcom_cc_register_board_clk(struct device *dev, const char *path,
98 const char *name, unsigned long rate,
99 bool add_factor)
100 {
101 struct device_node *node = NULL;
102 struct device_node *clocks_node;
103 struct clk_fixed_factor *factor;
104 struct clk_fixed_rate *fixed;
105 struct clk_init_data init_data = { };
106 int ret;
107
108 clocks_node = of_find_node_by_path("/clocks");
109 if (clocks_node)
110 node = of_find_node_by_name(clocks_node, path);
111 of_node_put(clocks_node);
112
113 if (!node) {
114 fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
115 if (!fixed)
116 return -EINVAL;
117
118 fixed->fixed_rate = rate;
119 fixed->hw.init = &init_data;
120
121 init_data.name = path;
122 init_data.ops = &clk_fixed_rate_ops;
123
124 ret = devm_clk_hw_register(dev, &fixed->hw);
125 if (ret)
126 return ret;
127 }
128 of_node_put(node);
129
130 if (add_factor) {
131 factor = devm_kzalloc(dev, sizeof(*factor), GFP_KERNEL);
132 if (!factor)
133 return -EINVAL;
134
135 factor->mult = factor->div = 1;
136 factor->hw.init = &init_data;
137
138 init_data.name = name;
139 init_data.parent_names = &path;
140 init_data.num_parents = 1;
141 init_data.flags = 0;
142 init_data.ops = &clk_fixed_factor_ops;
143
144 ret = devm_clk_hw_register(dev, &factor->hw);
145 if (ret)
146 return ret;
147 }
148
149 return 0;
150 }
151
qcom_cc_register_board_clk(struct device * dev,const char * path,const char * name,unsigned long rate)152 int qcom_cc_register_board_clk(struct device *dev, const char *path,
153 const char *name, unsigned long rate)
154 {
155 bool add_factor = true;
156 struct device_node *node;
157
158 /* The RPM clock driver will add the factor clock if present */
159 if (IS_ENABLED(CONFIG_QCOM_RPMCC)) {
160 node = of_find_compatible_node(NULL, NULL, "qcom,rpmcc");
161 if (of_device_is_available(node))
162 add_factor = false;
163 of_node_put(node);
164 }
165
166 return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor);
167 }
168 EXPORT_SYMBOL_GPL(qcom_cc_register_board_clk);
169
qcom_cc_register_sleep_clk(struct device * dev)170 int qcom_cc_register_sleep_clk(struct device *dev)
171 {
172 return _qcom_cc_register_board_clk(dev, "sleep_clk", "sleep_clk_src",
173 32768, true);
174 }
175 EXPORT_SYMBOL_GPL(qcom_cc_register_sleep_clk);
176
qcom_cc_clk_hw_get(struct of_phandle_args * clkspec,void * data)177 static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec,
178 void *data)
179 {
180 struct qcom_cc *cc = data;
181 unsigned int idx = clkspec->args[0];
182
183 if (idx >= cc->num_rclks) {
184 pr_err("%s: invalid index %u\n", __func__, idx);
185 return ERR_PTR(-EINVAL);
186 }
187
188 return cc->rclks[idx] ? &cc->rclks[idx]->hw : ERR_PTR(-ENOENT);
189 }
190
qcom_cc_really_probe(struct platform_device * pdev,const struct qcom_cc_desc * desc,struct regmap * regmap)191 int qcom_cc_really_probe(struct platform_device *pdev,
192 const struct qcom_cc_desc *desc, struct regmap *regmap)
193 {
194 int i, ret;
195 struct device *dev = &pdev->dev;
196 struct qcom_reset_controller *reset;
197 struct qcom_cc *cc;
198 struct gdsc_desc *scd;
199 size_t num_clks = desc->num_clks;
200 struct clk_regmap **rclks = desc->clks;
201
202 cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);
203 if (!cc)
204 return -ENOMEM;
205
206 cc->rclks = rclks;
207 cc->num_rclks = num_clks;
208
209 for (i = 0; i < num_clks; i++) {
210 if (!rclks[i])
211 continue;
212
213 ret = devm_clk_register_regmap(dev, rclks[i]);
214 if (ret)
215 return ret;
216 }
217
218 ret = of_clk_add_hw_provider(dev->of_node, qcom_cc_clk_hw_get, cc);
219 if (ret)
220 return ret;
221
222 ret = devm_add_action_or_reset(dev, qcom_cc_del_clk_provider,
223 pdev->dev.of_node);
224
225 if (ret)
226 return ret;
227
228 reset = &cc->reset;
229 reset->rcdev.of_node = dev->of_node;
230 reset->rcdev.ops = &qcom_reset_ops;
231 reset->rcdev.owner = dev->driver->owner;
232 reset->rcdev.nr_resets = desc->num_resets;
233 reset->regmap = regmap;
234 reset->reset_map = desc->resets;
235
236 ret = reset_controller_register(&reset->rcdev);
237 if (ret)
238 return ret;
239
240 ret = devm_add_action_or_reset(dev, qcom_cc_reset_unregister,
241 &reset->rcdev);
242
243 if (ret)
244 return ret;
245
246 if (desc->gdscs && desc->num_gdscs) {
247 scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL);
248 if (!scd)
249 return -ENOMEM;
250 scd->dev = dev;
251 scd->scs = desc->gdscs;
252 scd->num = desc->num_gdscs;
253 ret = gdsc_register(scd, &reset->rcdev, regmap);
254 if (ret)
255 return ret;
256 ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister,
257 scd);
258 if (ret)
259 return ret;
260 }
261
262 return 0;
263 }
264 EXPORT_SYMBOL_GPL(qcom_cc_really_probe);
265
qcom_cc_probe(struct platform_device * pdev,const struct qcom_cc_desc * desc)266 int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
267 {
268 struct regmap *regmap;
269
270 regmap = qcom_cc_map(pdev, desc);
271 if (IS_ERR(regmap))
272 return PTR_ERR(regmap);
273
274 return qcom_cc_really_probe(pdev, desc, regmap);
275 }
276 EXPORT_SYMBOL_GPL(qcom_cc_probe);
277
278 MODULE_LICENSE("GPL v2");
279