1 /*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/bitops.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/jiffies.h>
18 #include <linux/kernel.h>
19 #include <linux/ktime.h>
20 #include <linux/pm_domain.h>
21 #include <linux/regmap.h>
22 #include <linux/reset-controller.h>
23 #include <linux/slab.h>
24 #include "gdsc.h"
25
26 #define PWR_ON_MASK BIT(31)
27 #define EN_REST_WAIT_MASK GENMASK_ULL(23, 20)
28 #define EN_FEW_WAIT_MASK GENMASK_ULL(19, 16)
29 #define CLK_DIS_WAIT_MASK GENMASK_ULL(15, 12)
30 #define SW_OVERRIDE_MASK BIT(2)
31 #define HW_CONTROL_MASK BIT(1)
32 #define SW_COLLAPSE_MASK BIT(0)
33
34 /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
35 #define EN_REST_WAIT_VAL (0x2 << 20)
36 #define EN_FEW_WAIT_VAL (0x8 << 16)
37 #define CLK_DIS_WAIT_VAL (0x2 << 12)
38
39 #define RETAIN_MEM BIT(14)
40 #define RETAIN_PERIPH BIT(13)
41
42 #define TIMEOUT_US 100
43
44 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
45
gdsc_is_enabled(struct gdsc * sc,unsigned int reg)46 static int gdsc_is_enabled(struct gdsc *sc, unsigned int reg)
47 {
48 u32 val;
49 int ret;
50
51 ret = regmap_read(sc->regmap, reg, &val);
52 if (ret)
53 return ret;
54
55 return !!(val & PWR_ON_MASK);
56 }
57
gdsc_toggle_logic(struct gdsc * sc,bool en)58 static int gdsc_toggle_logic(struct gdsc *sc, bool en)
59 {
60 int ret;
61 u32 val = en ? 0 : SW_COLLAPSE_MASK;
62 ktime_t start;
63 unsigned int status_reg = sc->gdscr;
64
65 ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
66 if (ret)
67 return ret;
68
69 /* If disabling votable gdscs, don't poll on status */
70 if ((sc->flags & VOTABLE) && !en) {
71 /*
72 * Add a short delay here to ensure that an enable
73 * right after it was disabled does not put it in an
74 * unknown state
75 */
76 udelay(TIMEOUT_US);
77 return 0;
78 }
79
80 if (sc->gds_hw_ctrl) {
81 status_reg = sc->gds_hw_ctrl;
82 /*
83 * The gds hw controller asserts/de-asserts the status bit soon
84 * after it receives a power on/off request from a master.
85 * The controller then takes around 8 xo cycles to start its
86 * internal state machine and update the status bit. During
87 * this time, the status bit does not reflect the true status
88 * of the core.
89 * Add a delay of 1 us between writing to the SW_COLLAPSE bit
90 * and polling the status bit.
91 */
92 udelay(1);
93 }
94
95 start = ktime_get();
96 do {
97 if (gdsc_is_enabled(sc, status_reg) == en)
98 return 0;
99 } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
100
101 if (gdsc_is_enabled(sc, status_reg) == en)
102 return 0;
103
104 return -ETIMEDOUT;
105 }
106
gdsc_deassert_reset(struct gdsc * sc)107 static inline int gdsc_deassert_reset(struct gdsc *sc)
108 {
109 int i;
110
111 for (i = 0; i < sc->reset_count; i++)
112 sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
113 return 0;
114 }
115
gdsc_assert_reset(struct gdsc * sc)116 static inline int gdsc_assert_reset(struct gdsc *sc)
117 {
118 int i;
119
120 for (i = 0; i < sc->reset_count; i++)
121 sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
122 return 0;
123 }
124
gdsc_force_mem_on(struct gdsc * sc)125 static inline void gdsc_force_mem_on(struct gdsc *sc)
126 {
127 int i;
128 u32 mask = RETAIN_MEM | RETAIN_PERIPH;
129
130 for (i = 0; i < sc->cxc_count; i++)
131 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
132 }
133
gdsc_clear_mem_on(struct gdsc * sc)134 static inline void gdsc_clear_mem_on(struct gdsc *sc)
135 {
136 int i;
137 u32 mask = RETAIN_MEM | RETAIN_PERIPH;
138
139 for (i = 0; i < sc->cxc_count; i++)
140 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
141 }
142
gdsc_enable(struct generic_pm_domain * domain)143 static int gdsc_enable(struct generic_pm_domain *domain)
144 {
145 struct gdsc *sc = domain_to_gdsc(domain);
146 int ret;
147
148 if (sc->pwrsts == PWRSTS_ON)
149 return gdsc_deassert_reset(sc);
150
151 ret = gdsc_toggle_logic(sc, true);
152 if (ret)
153 return ret;
154
155 if (sc->pwrsts & PWRSTS_OFF)
156 gdsc_force_mem_on(sc);
157
158 /*
159 * If clocks to this power domain were already on, they will take an
160 * additional 4 clock cycles to re-enable after the power domain is
161 * enabled. Delay to account for this. A delay is also needed to ensure
162 * clocks are not enabled within 400ns of enabling power to the
163 * memories.
164 */
165 udelay(1);
166
167 return 0;
168 }
169
gdsc_disable(struct generic_pm_domain * domain)170 static int gdsc_disable(struct generic_pm_domain *domain)
171 {
172 struct gdsc *sc = domain_to_gdsc(domain);
173
174 if (sc->pwrsts == PWRSTS_ON)
175 return gdsc_assert_reset(sc);
176
177 if (sc->pwrsts & PWRSTS_OFF)
178 gdsc_clear_mem_on(sc);
179
180 return gdsc_toggle_logic(sc, false);
181 }
182
gdsc_init(struct gdsc * sc)183 static int gdsc_init(struct gdsc *sc)
184 {
185 u32 mask, val;
186 int on, ret;
187 unsigned int reg;
188
189 /*
190 * Disable HW trigger: collapse/restore occur based on registers writes.
191 * Disable SW override: Use hardware state-machine for sequencing.
192 * Configure wait time between states.
193 */
194 mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
195 EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
196 val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
197 ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
198 if (ret)
199 return ret;
200
201 /* Force gdsc ON if only ON state is supported */
202 if (sc->pwrsts == PWRSTS_ON) {
203 ret = gdsc_toggle_logic(sc, true);
204 if (ret)
205 return ret;
206 }
207
208 reg = sc->gds_hw_ctrl ? sc->gds_hw_ctrl : sc->gdscr;
209 on = gdsc_is_enabled(sc, reg);
210 if (on < 0)
211 return on;
212
213 /*
214 * Votable GDSCs can be ON due to Vote from other masters.
215 * If a Votable GDSC is ON, make sure we have a Vote.
216 */
217 if ((sc->flags & VOTABLE) && on)
218 gdsc_enable(&sc->pd);
219
220 if (on || (sc->pwrsts & PWRSTS_RET))
221 gdsc_force_mem_on(sc);
222 else
223 gdsc_clear_mem_on(sc);
224
225 sc->pd.power_off = gdsc_disable;
226 sc->pd.power_on = gdsc_enable;
227 pm_genpd_init(&sc->pd, NULL, !on);
228
229 return 0;
230 }
231
gdsc_register(struct gdsc_desc * desc,struct reset_controller_dev * rcdev,struct regmap * regmap)232 int gdsc_register(struct gdsc_desc *desc,
233 struct reset_controller_dev *rcdev, struct regmap *regmap)
234 {
235 int i, ret;
236 struct genpd_onecell_data *data;
237 struct device *dev = desc->dev;
238 struct gdsc **scs = desc->scs;
239 size_t num = desc->num;
240
241 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
242 if (!data)
243 return -ENOMEM;
244
245 data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
246 GFP_KERNEL);
247 if (!data->domains)
248 return -ENOMEM;
249
250 data->num_domains = num;
251 for (i = 0; i < num; i++) {
252 if (!scs[i])
253 continue;
254 scs[i]->regmap = regmap;
255 scs[i]->rcdev = rcdev;
256 ret = gdsc_init(scs[i]);
257 if (ret)
258 return ret;
259 data->domains[i] = &scs[i]->pd;
260 }
261
262 /* Add subdomains */
263 for (i = 0; i < num; i++) {
264 if (!scs[i])
265 continue;
266 if (scs[i]->parent)
267 pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
268 }
269
270 return of_genpd_add_provider_onecell(dev->of_node, data);
271 }
272
gdsc_unregister(struct gdsc_desc * desc)273 void gdsc_unregister(struct gdsc_desc *desc)
274 {
275 int i;
276 struct device *dev = desc->dev;
277 struct gdsc **scs = desc->scs;
278 size_t num = desc->num;
279
280 /* Remove subdomains */
281 for (i = 0; i < num; i++) {
282 if (!scs[i])
283 continue;
284 if (scs[i]->parent)
285 pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
286 }
287 of_genpd_del_provider(dev->of_node);
288 }
289