1 /* * CAAM control-plane driver backend
2 * Controller-level driver, kernel property detection, initialization
3 *
4 * Copyright 2008-2012 Freescale Semiconductor, Inc.
5 */
6
7 #include <linux/device.h>
8 #include <linux/of_address.h>
9 #include <linux/of_irq.h>
10
11 #include "compat.h"
12 #include "regs.h"
13 #include "intern.h"
14 #include "jr.h"
15 #include "desc_constr.h"
16 #include "error.h"
17 #include "ctrl.h"
18
19 bool caam_little_end;
20 EXPORT_SYMBOL(caam_little_end);
21
22 /*
23 * i.MX targets tend to have clock control subsystems that can
24 * enable/disable clocking to our device.
25 */
26 #ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_IMX
caam_drv_identify_clk(struct device * dev,char * clk_name)27 static inline struct clk *caam_drv_identify_clk(struct device *dev,
28 char *clk_name)
29 {
30 return devm_clk_get(dev, clk_name);
31 }
32 #else
caam_drv_identify_clk(struct device * dev,char * clk_name)33 static inline struct clk *caam_drv_identify_clk(struct device *dev,
34 char *clk_name)
35 {
36 return NULL;
37 }
38 #endif
39
40 /*
41 * Descriptor to instantiate RNG State Handle 0 in normal mode and
42 * load the JDKEK, TDKEK and TDSK registers
43 */
build_instantiation_desc(u32 * desc,int handle,int do_sk)44 static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
45 {
46 u32 *jump_cmd, op_flags;
47
48 init_job_desc(desc, 0);
49
50 op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
51 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT;
52
53 /* INIT RNG in non-test mode */
54 append_operation(desc, op_flags);
55
56 if (!handle && do_sk) {
57 /*
58 * For SH0, Secure Keys must be generated as well
59 */
60
61 /* wait for done */
62 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
63 set_jump_tgt_here(desc, jump_cmd);
64
65 /*
66 * load 1 to clear written reg:
67 * resets the done interrrupt and returns the RNG to idle.
68 */
69 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
70
71 /* Initialize State Handle */
72 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
73 OP_ALG_AAI_RNG4_SK);
74 }
75
76 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
77 }
78
79 /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
build_deinstantiation_desc(u32 * desc,int handle)80 static void build_deinstantiation_desc(u32 *desc, int handle)
81 {
82 init_job_desc(desc, 0);
83
84 /* Uninstantiate State Handle 0 */
85 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
86 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
87
88 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
89 }
90
91 /*
92 * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
93 * the software (no JR/QI used).
94 * @ctrldev - pointer to device
95 * @status - descriptor status, after being run
96 *
97 * Return: - 0 if no error occurred
98 * - -ENODEV if the DECO couldn't be acquired
99 * - -EAGAIN if an error occurred while executing the descriptor
100 */
run_descriptor_deco0(struct device * ctrldev,u32 * desc,u32 * status)101 static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
102 u32 *status)
103 {
104 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
105 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
106 struct caam_deco __iomem *deco = ctrlpriv->deco;
107 unsigned int timeout = 100000;
108 u32 deco_dbg_reg, flags;
109 int i;
110
111
112 if (ctrlpriv->virt_en == 1) {
113 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
114
115 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
116 --timeout)
117 cpu_relax();
118
119 timeout = 100000;
120 }
121
122 clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
123
124 while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
125 --timeout)
126 cpu_relax();
127
128 if (!timeout) {
129 dev_err(ctrldev, "failed to acquire DECO 0\n");
130 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
131 return -ENODEV;
132 }
133
134 for (i = 0; i < desc_len(desc); i++)
135 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));
136
137 flags = DECO_JQCR_WHL;
138 /*
139 * If the descriptor length is longer than 4 words, then the
140 * FOUR bit in JRCTRL register must be set.
141 */
142 if (desc_len(desc) >= 4)
143 flags |= DECO_JQCR_FOUR;
144
145 /* Instruct the DECO to execute it */
146 clrsetbits_32(&deco->jr_ctl_hi, 0, flags);
147
148 timeout = 10000000;
149 do {
150 deco_dbg_reg = rd_reg32(&deco->desc_dbg);
151 /*
152 * If an error occured in the descriptor, then
153 * the DECO status field will be set to 0x0D
154 */
155 if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) ==
156 DESC_DBG_DECO_STAT_HOST_ERR)
157 break;
158 cpu_relax();
159 } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
160
161 *status = rd_reg32(&deco->op_status_hi) &
162 DECO_OP_STATUS_HI_ERR_MASK;
163
164 if (ctrlpriv->virt_en == 1)
165 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
166
167 /* Mark the DECO as free */
168 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
169
170 if (!timeout)
171 return -EAGAIN;
172
173 return 0;
174 }
175
176 /*
177 * instantiate_rng - builds and executes a descriptor on DECO0,
178 * which initializes the RNG block.
179 * @ctrldev - pointer to device
180 * @state_handle_mask - bitmask containing the instantiation status
181 * for the RNG4 state handles which exist in
182 * the RNG4 block: 1 if it's been instantiated
183 * by an external entry, 0 otherwise.
184 * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK;
185 * Caution: this can be done only once; if the keys need to be
186 * regenerated, a POR is required
187 *
188 * Return: - 0 if no error occurred
189 * - -ENOMEM if there isn't enough memory to allocate the descriptor
190 * - -ENODEV if DECO0 couldn't be acquired
191 * - -EAGAIN if an error occurred when executing the descriptor
192 * f.i. there was a RNG hardware error due to not "good enough"
193 * entropy being aquired.
194 */
instantiate_rng(struct device * ctrldev,int state_handle_mask,int gen_sk)195 static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
196 int gen_sk)
197 {
198 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
199 struct caam_ctrl __iomem *ctrl;
200 u32 *desc, status = 0, rdsta_val;
201 int ret = 0, sh_idx;
202
203 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
204 desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL);
205 if (!desc)
206 return -ENOMEM;
207
208 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
209 /*
210 * If the corresponding bit is set, this state handle
211 * was initialized by somebody else, so it's left alone.
212 */
213 if ((1 << sh_idx) & state_handle_mask)
214 continue;
215
216 /* Create the descriptor for instantiating RNG State Handle */
217 build_instantiation_desc(desc, sh_idx, gen_sk);
218
219 /* Try to run it through DECO0 */
220 ret = run_descriptor_deco0(ctrldev, desc, &status);
221
222 /*
223 * If ret is not 0, or descriptor status is not 0, then
224 * something went wrong. No need to try the next state
225 * handle (if available), bail out here.
226 * Also, if for some reason, the State Handle didn't get
227 * instantiated although the descriptor has finished
228 * without any error (HW optimizations for later
229 * CAAM eras), then try again.
230 */
231 if (ret)
232 break;
233
234 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
235 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
236 !(rdsta_val & (1 << sh_idx))) {
237 ret = -EAGAIN;
238 break;
239 }
240
241 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
242 /* Clear the contents before recreating the descriptor */
243 memset(desc, 0x00, CAAM_CMD_SZ * 7);
244 }
245
246 kfree(desc);
247
248 return ret;
249 }
250
251 /*
252 * deinstantiate_rng - builds and executes a descriptor on DECO0,
253 * which deinitializes the RNG block.
254 * @ctrldev - pointer to device
255 * @state_handle_mask - bitmask containing the instantiation status
256 * for the RNG4 state handles which exist in
257 * the RNG4 block: 1 if it's been instantiated
258 *
259 * Return: - 0 if no error occurred
260 * - -ENOMEM if there isn't enough memory to allocate the descriptor
261 * - -ENODEV if DECO0 couldn't be acquired
262 * - -EAGAIN if an error occurred when executing the descriptor
263 */
deinstantiate_rng(struct device * ctrldev,int state_handle_mask)264 static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
265 {
266 u32 *desc, status;
267 int sh_idx, ret = 0;
268
269 desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL);
270 if (!desc)
271 return -ENOMEM;
272
273 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
274 /*
275 * If the corresponding bit is set, then it means the state
276 * handle was initialized by us, and thus it needs to be
277 * deintialized as well
278 */
279 if ((1 << sh_idx) & state_handle_mask) {
280 /*
281 * Create the descriptor for deinstantating this state
282 * handle
283 */
284 build_deinstantiation_desc(desc, sh_idx);
285
286 /* Try to run it through DECO0 */
287 ret = run_descriptor_deco0(ctrldev, desc, &status);
288
289 if (ret ||
290 (status && status != JRSTA_SSRC_JUMP_HALT_CC)) {
291 dev_err(ctrldev,
292 "Failed to deinstantiate RNG4 SH%d\n",
293 sh_idx);
294 break;
295 }
296 dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
297 }
298 }
299
300 kfree(desc);
301
302 return ret;
303 }
304
caam_remove(struct platform_device * pdev)305 static int caam_remove(struct platform_device *pdev)
306 {
307 struct device *ctrldev;
308 struct caam_drv_private *ctrlpriv;
309 struct caam_ctrl __iomem *ctrl;
310 int ring;
311
312 ctrldev = &pdev->dev;
313 ctrlpriv = dev_get_drvdata(ctrldev);
314 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
315
316 /* Remove platform devices for JobRs */
317 for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) {
318 if (ctrlpriv->jrpdev[ring])
319 of_device_unregister(ctrlpriv->jrpdev[ring]);
320 }
321
322 /* De-initialize RNG state handles initialized by this driver. */
323 if (ctrlpriv->rng4_sh_init)
324 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
325
326 /* Shut down debug views */
327 #ifdef CONFIG_DEBUG_FS
328 debugfs_remove_recursive(ctrlpriv->dfs_root);
329 #endif
330
331 /* Unmap controller region */
332 iounmap(ctrl);
333
334 /* shut clocks off before finalizing shutdown */
335 clk_disable_unprepare(ctrlpriv->caam_ipg);
336 clk_disable_unprepare(ctrlpriv->caam_mem);
337 clk_disable_unprepare(ctrlpriv->caam_aclk);
338 clk_disable_unprepare(ctrlpriv->caam_emi_slow);
339
340 return 0;
341 }
342
343 /*
344 * kick_trng - sets the various parameters for enabling the initialization
345 * of the RNG4 block in CAAM
346 * @pdev - pointer to the platform device
347 * @ent_delay - Defines the length (in system clocks) of each entropy sample.
348 */
kick_trng(struct platform_device * pdev,int ent_delay)349 static void kick_trng(struct platform_device *pdev, int ent_delay)
350 {
351 struct device *ctrldev = &pdev->dev;
352 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
353 struct caam_ctrl __iomem *ctrl;
354 struct rng4tst __iomem *r4tst;
355 u32 val;
356
357 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
358 r4tst = &ctrl->r4tst[0];
359
360 /* put RNG4 into program mode */
361 clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM);
362
363 /*
364 * Performance-wise, it does not make sense to
365 * set the delay to a value that is lower
366 * than the last one that worked (i.e. the state handles
367 * were instantiated properly. Thus, instead of wasting
368 * time trying to set the values controlling the sample
369 * frequency, the function simply returns.
370 */
371 val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
372 >> RTSDCTL_ENT_DLY_SHIFT;
373 if (ent_delay <= val) {
374 /* put RNG4 into run mode */
375 clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, 0);
376 return;
377 }
378
379 val = rd_reg32(&r4tst->rtsdctl);
380 val = (val & ~RTSDCTL_ENT_DLY_MASK) |
381 (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
382 wr_reg32(&r4tst->rtsdctl, val);
383 /* min. freq. count, equal to 1/4 of the entropy sample length */
384 wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
385 /* disable maximum frequency count */
386 wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
387 /* read the control register */
388 val = rd_reg32(&r4tst->rtmctl);
389 /*
390 * select raw sampling in both entropy shifter
391 * and statistical checker
392 */
393 clrsetbits_32(&val, 0, RTMCTL_SAMP_MODE_RAW_ES_SC);
394 /* put RNG4 into run mode */
395 clrsetbits_32(&val, RTMCTL_PRGM, 0);
396 /* write back the control register */
397 wr_reg32(&r4tst->rtmctl, val);
398 }
399
400 /**
401 * caam_get_era() - Return the ERA of the SEC on SoC, based
402 * on "sec-era" propery in the DTS. This property is updated by u-boot.
403 **/
caam_get_era(void)404 int caam_get_era(void)
405 {
406 struct device_node *caam_node;
407 int ret;
408 u32 prop;
409
410 caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
411 ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
412 of_node_put(caam_node);
413
414 return ret ? -ENOTSUPP : prop;
415 }
416 EXPORT_SYMBOL(caam_get_era);
417
418 #ifdef CONFIG_DEBUG_FS
caam_debugfs_u64_get(void * data,u64 * val)419 static int caam_debugfs_u64_get(void *data, u64 *val)
420 {
421 *val = caam64_to_cpu(*(u64 *)data);
422 return 0;
423 }
424
caam_debugfs_u32_get(void * data,u64 * val)425 static int caam_debugfs_u32_get(void *data, u64 *val)
426 {
427 *val = caam32_to_cpu(*(u32 *)data);
428 return 0;
429 }
430
431 DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u32_ro, caam_debugfs_u32_get, NULL, "%llu\n");
432 DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u64_ro, caam_debugfs_u64_get, NULL, "%llu\n");
433 #endif
434
435 /* Probe routine for CAAM top (controller) level */
caam_probe(struct platform_device * pdev)436 static int caam_probe(struct platform_device *pdev)
437 {
438 int ret, ring, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
439 u64 caam_id;
440 struct device *dev;
441 struct device_node *nprop, *np;
442 struct caam_ctrl __iomem *ctrl;
443 struct caam_drv_private *ctrlpriv;
444 struct clk *clk;
445 #ifdef CONFIG_DEBUG_FS
446 struct caam_perfmon *perfmon;
447 #endif
448 u32 scfgr, comp_params;
449 u32 cha_vid_ls;
450 int pg_size;
451 int BLOCK_OFFSET = 0;
452
453 ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
454 if (!ctrlpriv)
455 return -ENOMEM;
456
457 dev = &pdev->dev;
458 dev_set_drvdata(dev, ctrlpriv);
459 ctrlpriv->pdev = pdev;
460 nprop = pdev->dev.of_node;
461
462 /* Enable clocking */
463 clk = caam_drv_identify_clk(&pdev->dev, "ipg");
464 if (IS_ERR(clk)) {
465 ret = PTR_ERR(clk);
466 dev_err(&pdev->dev,
467 "can't identify CAAM ipg clk: %d\n", ret);
468 return ret;
469 }
470 ctrlpriv->caam_ipg = clk;
471
472 clk = caam_drv_identify_clk(&pdev->dev, "mem");
473 if (IS_ERR(clk)) {
474 ret = PTR_ERR(clk);
475 dev_err(&pdev->dev,
476 "can't identify CAAM mem clk: %d\n", ret);
477 return ret;
478 }
479 ctrlpriv->caam_mem = clk;
480
481 clk = caam_drv_identify_clk(&pdev->dev, "aclk");
482 if (IS_ERR(clk)) {
483 ret = PTR_ERR(clk);
484 dev_err(&pdev->dev,
485 "can't identify CAAM aclk clk: %d\n", ret);
486 return ret;
487 }
488 ctrlpriv->caam_aclk = clk;
489
490 clk = caam_drv_identify_clk(&pdev->dev, "emi_slow");
491 if (IS_ERR(clk)) {
492 ret = PTR_ERR(clk);
493 dev_err(&pdev->dev,
494 "can't identify CAAM emi_slow clk: %d\n", ret);
495 return ret;
496 }
497 ctrlpriv->caam_emi_slow = clk;
498
499 ret = clk_prepare_enable(ctrlpriv->caam_ipg);
500 if (ret < 0) {
501 dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret);
502 return ret;
503 }
504
505 ret = clk_prepare_enable(ctrlpriv->caam_mem);
506 if (ret < 0) {
507 dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n",
508 ret);
509 goto disable_caam_ipg;
510 }
511
512 ret = clk_prepare_enable(ctrlpriv->caam_aclk);
513 if (ret < 0) {
514 dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret);
515 goto disable_caam_mem;
516 }
517
518 ret = clk_prepare_enable(ctrlpriv->caam_emi_slow);
519 if (ret < 0) {
520 dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n",
521 ret);
522 goto disable_caam_aclk;
523 }
524
525 /* Get configuration properties from device tree */
526 /* First, get register page */
527 ctrl = of_iomap(nprop, 0);
528 if (ctrl == NULL) {
529 dev_err(dev, "caam: of_iomap() failed\n");
530 ret = -ENOMEM;
531 goto disable_caam_emi_slow;
532 }
533
534 caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) &
535 (CSTA_PLEND | CSTA_ALT_PLEND));
536
537 /* Finding the page size for using the CTPR_MS register */
538 comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
539 pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
540
541 /* Allocating the BLOCK_OFFSET based on the supported page size on
542 * the platform
543 */
544 if (pg_size == 0)
545 BLOCK_OFFSET = PG_SIZE_4K;
546 else
547 BLOCK_OFFSET = PG_SIZE_64K;
548
549 ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl;
550 ctrlpriv->assure = (struct caam_assurance __force *)
551 ((uint8_t *)ctrl +
552 BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
553 );
554 ctrlpriv->deco = (struct caam_deco __force *)
555 ((uint8_t *)ctrl +
556 BLOCK_OFFSET * DECO_BLOCK_NUMBER
557 );
558
559 /* Get the IRQ of the controller (for security violations only) */
560 ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
561
562 /*
563 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
564 * long pointers in master configuration register
565 */
566 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_LONG_PTR,
567 MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
568 MCFGR_WDENABLE | MCFGR_LARGE_BURST |
569 (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
570
571 /*
572 * Read the Compile Time paramters and SCFGR to determine
573 * if Virtualization is enabled for this platform
574 */
575 scfgr = rd_reg32(&ctrl->scfgr);
576
577 ctrlpriv->virt_en = 0;
578 if (comp_params & CTPR_MS_VIRT_EN_INCL) {
579 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
580 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
581 */
582 if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
583 (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
584 (scfgr & SCFGR_VIRT_EN)))
585 ctrlpriv->virt_en = 1;
586 } else {
587 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
588 if (comp_params & CTPR_MS_VIRT_EN_POR)
589 ctrlpriv->virt_en = 1;
590 }
591
592 if (ctrlpriv->virt_en == 1)
593 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
594 JRSTART_JR1_START | JRSTART_JR2_START |
595 JRSTART_JR3_START);
596
597 if (sizeof(dma_addr_t) == sizeof(u64))
598 if (of_device_is_compatible(nprop, "fsl,sec-v5.0"))
599 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
600 else
601 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
602 else
603 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
604
605 /*
606 * Detect and enable JobRs
607 * First, find out how many ring spec'ed, allocate references
608 * for all, then go probe each one.
609 */
610 rspec = 0;
611 for_each_available_child_of_node(nprop, np)
612 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
613 of_device_is_compatible(np, "fsl,sec4.0-job-ring"))
614 rspec++;
615
616 ctrlpriv->jrpdev = devm_kcalloc(&pdev->dev, rspec,
617 sizeof(*ctrlpriv->jrpdev), GFP_KERNEL);
618 if (ctrlpriv->jrpdev == NULL) {
619 ret = -ENOMEM;
620 goto iounmap_ctrl;
621 }
622
623 ring = 0;
624 ctrlpriv->total_jobrs = 0;
625 for_each_available_child_of_node(nprop, np)
626 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
627 of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
628 ctrlpriv->jrpdev[ring] =
629 of_platform_device_create(np, NULL, dev);
630 if (!ctrlpriv->jrpdev[ring]) {
631 pr_warn("JR%d Platform device creation error\n",
632 ring);
633 continue;
634 }
635 ctrlpriv->jr[ring] = (struct caam_job_ring __force *)
636 ((uint8_t *)ctrl +
637 (ring + JR_BLOCK_NUMBER) *
638 BLOCK_OFFSET
639 );
640 ctrlpriv->total_jobrs++;
641 ring++;
642 }
643
644 /* Check to see if QI present. If so, enable */
645 ctrlpriv->qi_present =
646 !!(rd_reg32(&ctrl->perfmon.comp_parms_ms) &
647 CTPR_MS_QI_MASK);
648 if (ctrlpriv->qi_present) {
649 ctrlpriv->qi = (struct caam_queue_if __force *)
650 ((uint8_t *)ctrl +
651 BLOCK_OFFSET * QI_BLOCK_NUMBER
652 );
653 /* This is all that's required to physically enable QI */
654 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
655 }
656
657 /* If no QI and no rings specified, quit and go home */
658 if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
659 dev_err(dev, "no queues configured, terminating\n");
660 ret = -ENOMEM;
661 goto caam_remove;
662 }
663
664 cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls);
665
666 /*
667 * If SEC has RNG version >= 4 and RNG state handle has not been
668 * already instantiated, do RNG instantiation
669 */
670 if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
671 ctrlpriv->rng4_sh_init =
672 rd_reg32(&ctrl->r4tst[0].rdsta);
673 /*
674 * If the secure keys (TDKEK, JDKEK, TDSK), were already
675 * generated, signal this to the function that is instantiating
676 * the state handles. An error would occur if RNG4 attempts
677 * to regenerate these keys before the next POR.
678 */
679 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
680 ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
681 do {
682 int inst_handles =
683 rd_reg32(&ctrl->r4tst[0].rdsta) &
684 RDSTA_IFMASK;
685 /*
686 * If either SH were instantiated by somebody else
687 * (e.g. u-boot) then it is assumed that the entropy
688 * parameters are properly set and thus the function
689 * setting these (kick_trng(...)) is skipped.
690 * Also, if a handle was instantiated, do not change
691 * the TRNG parameters.
692 */
693 if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
694 dev_info(dev,
695 "Entropy delay = %u\n",
696 ent_delay);
697 kick_trng(pdev, ent_delay);
698 ent_delay += 400;
699 }
700 /*
701 * if instantiate_rng(...) fails, the loop will rerun
702 * and the kick_trng(...) function will modfiy the
703 * upper and lower limits of the entropy sampling
704 * interval, leading to a sucessful initialization of
705 * the RNG.
706 */
707 ret = instantiate_rng(dev, inst_handles,
708 gen_sk);
709 if (ret == -EAGAIN)
710 /*
711 * if here, the loop will rerun,
712 * so don't hog the CPU
713 */
714 cpu_relax();
715 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
716 if (ret) {
717 dev_err(dev, "failed to instantiate RNG");
718 goto caam_remove;
719 }
720 /*
721 * Set handles init'ed by this module as the complement of the
722 * already initialized ones
723 */
724 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
725
726 /* Enable RDB bit so that RNG works faster */
727 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
728 }
729
730 /* NOTE: RTIC detection ought to go here, around Si time */
731
732 caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
733 (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
734
735 /* Report "alive" for developer to see */
736 dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
737 caam_get_era());
738 dev_info(dev, "job rings = %d, qi = %d\n",
739 ctrlpriv->total_jobrs, ctrlpriv->qi_present);
740
741 #ifdef CONFIG_DEBUG_FS
742 /*
743 * FIXME: needs better naming distinction, as some amalgamation of
744 * "caam" and nprop->full_name. The OF name isn't distinctive,
745 * but does separate instances
746 */
747 perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
748
749 ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL);
750 ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root);
751
752 /* Controller-level - performance monitor counters */
753
754 ctrlpriv->ctl_rq_dequeued =
755 debugfs_create_file("rq_dequeued",
756 S_IRUSR | S_IRGRP | S_IROTH,
757 ctrlpriv->ctl, &perfmon->req_dequeued,
758 &caam_fops_u64_ro);
759 ctrlpriv->ctl_ob_enc_req =
760 debugfs_create_file("ob_rq_encrypted",
761 S_IRUSR | S_IRGRP | S_IROTH,
762 ctrlpriv->ctl, &perfmon->ob_enc_req,
763 &caam_fops_u64_ro);
764 ctrlpriv->ctl_ib_dec_req =
765 debugfs_create_file("ib_rq_decrypted",
766 S_IRUSR | S_IRGRP | S_IROTH,
767 ctrlpriv->ctl, &perfmon->ib_dec_req,
768 &caam_fops_u64_ro);
769 ctrlpriv->ctl_ob_enc_bytes =
770 debugfs_create_file("ob_bytes_encrypted",
771 S_IRUSR | S_IRGRP | S_IROTH,
772 ctrlpriv->ctl, &perfmon->ob_enc_bytes,
773 &caam_fops_u64_ro);
774 ctrlpriv->ctl_ob_prot_bytes =
775 debugfs_create_file("ob_bytes_protected",
776 S_IRUSR | S_IRGRP | S_IROTH,
777 ctrlpriv->ctl, &perfmon->ob_prot_bytes,
778 &caam_fops_u64_ro);
779 ctrlpriv->ctl_ib_dec_bytes =
780 debugfs_create_file("ib_bytes_decrypted",
781 S_IRUSR | S_IRGRP | S_IROTH,
782 ctrlpriv->ctl, &perfmon->ib_dec_bytes,
783 &caam_fops_u64_ro);
784 ctrlpriv->ctl_ib_valid_bytes =
785 debugfs_create_file("ib_bytes_validated",
786 S_IRUSR | S_IRGRP | S_IROTH,
787 ctrlpriv->ctl, &perfmon->ib_valid_bytes,
788 &caam_fops_u64_ro);
789
790 /* Controller level - global status values */
791 ctrlpriv->ctl_faultaddr =
792 debugfs_create_file("fault_addr",
793 S_IRUSR | S_IRGRP | S_IROTH,
794 ctrlpriv->ctl, &perfmon->faultaddr,
795 &caam_fops_u32_ro);
796 ctrlpriv->ctl_faultdetail =
797 debugfs_create_file("fault_detail",
798 S_IRUSR | S_IRGRP | S_IROTH,
799 ctrlpriv->ctl, &perfmon->faultdetail,
800 &caam_fops_u32_ro);
801 ctrlpriv->ctl_faultstatus =
802 debugfs_create_file("fault_status",
803 S_IRUSR | S_IRGRP | S_IROTH,
804 ctrlpriv->ctl, &perfmon->status,
805 &caam_fops_u32_ro);
806
807 /* Internal covering keys (useful in non-secure mode only) */
808 ctrlpriv->ctl_kek_wrap.data = &ctrlpriv->ctrl->kek[0];
809 ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
810 ctrlpriv->ctl_kek = debugfs_create_blob("kek",
811 S_IRUSR |
812 S_IRGRP | S_IROTH,
813 ctrlpriv->ctl,
814 &ctrlpriv->ctl_kek_wrap);
815
816 ctrlpriv->ctl_tkek_wrap.data = &ctrlpriv->ctrl->tkek[0];
817 ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
818 ctrlpriv->ctl_tkek = debugfs_create_blob("tkek",
819 S_IRUSR |
820 S_IRGRP | S_IROTH,
821 ctrlpriv->ctl,
822 &ctrlpriv->ctl_tkek_wrap);
823
824 ctrlpriv->ctl_tdsk_wrap.data = &ctrlpriv->ctrl->tdsk[0];
825 ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32);
826 ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk",
827 S_IRUSR |
828 S_IRGRP | S_IROTH,
829 ctrlpriv->ctl,
830 &ctrlpriv->ctl_tdsk_wrap);
831 #endif
832 return 0;
833
834 caam_remove:
835 caam_remove(pdev);
836 return ret;
837
838 iounmap_ctrl:
839 iounmap(ctrl);
840 disable_caam_emi_slow:
841 clk_disable_unprepare(ctrlpriv->caam_emi_slow);
842 disable_caam_aclk:
843 clk_disable_unprepare(ctrlpriv->caam_aclk);
844 disable_caam_mem:
845 clk_disable_unprepare(ctrlpriv->caam_mem);
846 disable_caam_ipg:
847 clk_disable_unprepare(ctrlpriv->caam_ipg);
848 return ret;
849 }
850
851 static struct of_device_id caam_match[] = {
852 {
853 .compatible = "fsl,sec-v4.0",
854 },
855 {
856 .compatible = "fsl,sec4.0",
857 },
858 {},
859 };
860 MODULE_DEVICE_TABLE(of, caam_match);
861
862 static struct platform_driver caam_driver = {
863 .driver = {
864 .name = "caam",
865 .of_match_table = caam_match,
866 },
867 .probe = caam_probe,
868 .remove = caam_remove,
869 };
870
871 module_platform_driver(caam_driver);
872
873 MODULE_LICENSE("GPL");
874 MODULE_DESCRIPTION("FSL CAAM request backend");
875 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");
876