1 /*
2 This file is provided under a dual BSD/GPLv2 license. When using or
3 redistributing this file, you may do so under either license.
4
5 GPL LICENSE SUMMARY
6 Copyright(c) 2014 Intel Corporation.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of version 2 of the GNU General Public License as
9 published by the Free Software Foundation.
10
11 This program is distributed in the hope that it will be useful, but
12 WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 General Public License for more details.
15
16 Contact Information:
17 qat-linux@intel.com
18
19 BSD LICENSE
20 Copyright(c) 2014 Intel Corporation.
21 Redistribution and use in source and binary forms, with or without
22 modification, are permitted provided that the following conditions
23 are met:
24
25 * Redistributions of source code must retain the above copyright
26 notice, this list of conditions and the following disclaimer.
27 * Redistributions in binary form must reproduce the above copyright
28 notice, this list of conditions and the following disclaimer in
29 the documentation and/or other materials provided with the
30 distribution.
31 * Neither the name of Intel Corporation nor the names of its
32 contributors may be used to endorse or promote products derived
33 from this software without specific prior written permission.
34
35 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
36 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
37 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
38 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
39 OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
40 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
41 LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
42 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
43 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
44 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
45 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
46 */
47 #include "adf_accel_devices.h"
48 #include "adf_common_drv.h"
49 #include "adf_transport_internal.h"
50
51 #define ADF_ARB_NUM 4
52 #define ADF_ARB_REG_SIZE 0x4
53 #define ADF_ARB_WTR_SIZE 0x20
54 #define ADF_ARB_OFFSET 0x30000
55 #define ADF_ARB_REG_SLOT 0x1000
56 #define ADF_ARB_WTR_OFFSET 0x010
57 #define ADF_ARB_RO_EN_OFFSET 0x090
58 #define ADF_ARB_WQCFG_OFFSET 0x100
59 #define ADF_ARB_WRK_2_SER_MAP_OFFSET 0x180
60 #define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
61
62 #define WRITE_CSR_ARB_RINGSRVARBEN(csr_addr, index, value) \
63 ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
64 (ADF_ARB_REG_SLOT * index), value)
65
66 #define WRITE_CSR_ARB_SARCONFIG(csr_addr, index, value) \
67 ADF_CSR_WR(csr_addr, ADF_ARB_OFFSET + \
68 (ADF_ARB_REG_SIZE * index), value)
69
70 #define WRITE_CSR_ARB_WRK_2_SER_MAP(csr_addr, index, value) \
71 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
72 ADF_ARB_WRK_2_SER_MAP_OFFSET) + \
73 (ADF_ARB_REG_SIZE * index), value)
74
75 #define WRITE_CSR_ARB_WQCFG(csr_addr, index, value) \
76 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
77 ADF_ARB_WQCFG_OFFSET) + (ADF_ARB_REG_SIZE * index), value)
78
adf_init_arb(struct adf_accel_dev * accel_dev)79 int adf_init_arb(struct adf_accel_dev *accel_dev)
80 {
81 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
82 void __iomem *csr = accel_dev->transport->banks[0].csr_addr;
83 u32 arb_cfg = 0x1 << 31 | 0x4 << 4 | 0x1;
84 u32 arb, i;
85 const u32 *thd_2_arb_cfg;
86
87 /* Service arb configured for 32 bytes responses and
88 * ring flow control check enabled. */
89 for (arb = 0; arb < ADF_ARB_NUM; arb++)
90 WRITE_CSR_ARB_SARCONFIG(csr, arb, arb_cfg);
91
92 /* Setup worker queue registers */
93 for (i = 0; i < hw_data->num_engines; i++)
94 WRITE_CSR_ARB_WQCFG(csr, i, i);
95
96 /* Map worker threads to service arbiters */
97 hw_data->get_arb_mapping(accel_dev, &thd_2_arb_cfg);
98
99 if (!thd_2_arb_cfg)
100 return -EFAULT;
101
102 for (i = 0; i < hw_data->num_engines; i++)
103 WRITE_CSR_ARB_WRK_2_SER_MAP(csr, i, *(thd_2_arb_cfg + i));
104
105 return 0;
106 }
107 EXPORT_SYMBOL_GPL(adf_init_arb);
108
adf_update_ring_arb(struct adf_etr_ring_data * ring)109 void adf_update_ring_arb(struct adf_etr_ring_data *ring)
110 {
111 WRITE_CSR_ARB_RINGSRVARBEN(ring->bank->csr_addr,
112 ring->bank->bank_number,
113 ring->bank->ring_mask & 0xFF);
114 }
115
adf_exit_arb(struct adf_accel_dev * accel_dev)116 void adf_exit_arb(struct adf_accel_dev *accel_dev)
117 {
118 struct adf_hw_device_data *hw_data = accel_dev->hw_device;
119 void __iomem *csr;
120 unsigned int i;
121
122 if (!accel_dev->transport)
123 return;
124
125 csr = accel_dev->transport->banks[0].csr_addr;
126
127 /* Reset arbiter configuration */
128 for (i = 0; i < ADF_ARB_NUM; i++)
129 WRITE_CSR_ARB_SARCONFIG(csr, i, 0);
130
131 /* Shutdown work queue */
132 for (i = 0; i < hw_data->num_engines; i++)
133 WRITE_CSR_ARB_WQCFG(csr, i, 0);
134
135 /* Unmap worker threads to service arbiters */
136 for (i = 0; i < hw_data->num_engines; i++)
137 WRITE_CSR_ARB_WRK_2_SER_MAP(csr, i, 0);
138
139 /* Disable arbitration on all rings */
140 for (i = 0; i < GET_MAX_BANKS(accel_dev); i++)
141 WRITE_CSR_ARB_RINGSRVARBEN(csr, i, 0);
142 }
143 EXPORT_SYMBOL_GPL(adf_exit_arb);
144